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-rw-r--r--src/core/arm/interpreter/armemu.cpp925
1 files changed, 9 insertions, 916 deletions
diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp
index adc5c3a05..7114313d6 100644
--- a/src/core/arm/interpreter/armemu.cpp
+++ b/src/core/arm/interpreter/armemu.cpp
@@ -16,31 +16,11 @@
16 along with this program; if not, write to the Free Software 16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
18 18
19//#include <util.h> // DEBUG()
20
21#include "core/arm/skyeye_common/arm_regformat.h" 19#include "core/arm/skyeye_common/arm_regformat.h"
22#include "core/arm/skyeye_common/armdefs.h" 20#include "core/arm/skyeye_common/armdefs.h"
23#include "core/arm/skyeye_common/armemu.h" 21#include "core/arm/skyeye_common/armemu.h"
24#include "core/hle/hle.h" 22#include "core/hle/hle.h"
25 23
26//#include "svc.h"
27
28//ichfly
29//#define callstacker 1
30
31//#include "skyeye_callback.h"
32//#include "skyeye_bus.h"
33//#include "sim_control.h"
34//#include "skyeye_pref.h"
35//#include "skyeye.h"
36//#include "skyeye2gdb.h"
37//#include "code_cov.h"
38
39//#include "iwmmxt.h"
40//chy 2003-07-11: for debug instrs
41//extern int skyeye_instr_debug;
42extern FILE *skyeye_logfd;
43
44static ARMword GetDPRegRHS (ARMul_State *, ARMword); 24static ARMword GetDPRegRHS (ARMul_State *, ARMword);
45static ARMword GetDPSRegRHS (ARMul_State *, ARMword); 25static ARMword GetDPSRegRHS (ARMul_State *, ARMword);
46static void WriteR15 (ARMul_State *, ARMword); 26static void WriteR15 (ARMul_State *, ARMword);
@@ -63,25 +43,13 @@ static unsigned MultiplyAdd64 (ARMul_State *, ARMword, int, int);
63static void Handle_Load_Double (ARMul_State *, ARMword); 43static void Handle_Load_Double (ARMul_State *, ARMword);
64static void Handle_Store_Double (ARMul_State *, ARMword); 44static void Handle_Store_Double (ARMul_State *, ARMword);
65 45
66static int 46static int handle_v6_insn (ARMul_State * state, ARMword instr);
67handle_v6_insn (ARMul_State * state, ARMword instr);
68 47
69#define LUNSIGNED (0) /* unsigned operation */ 48#define LUNSIGNED (0) /* unsigned operation */
70#define LSIGNED (1) /* signed operation */ 49#define LSIGNED (1) /* signed operation */
71#define LDEFAULT (0) /* default : do nothing */ 50#define LDEFAULT (0) /* default : do nothing */
72#define LSCC (1) /* set condition codes on result */ 51#define LSCC (1) /* set condition codes on result */
73 52
74#ifdef NEED_UI_LOOP_HOOK
75/* How often to run the ui_loop update, when in use. */
76#define UI_LOOP_POLL_INTERVAL 0x32000
77
78/* Counter for the ui_loop_hook update. */
79static int ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL;
80
81/* Actual hook to call to run through gdb's gui event loop. */
82extern int (*ui_loop_hook) (int);
83#endif /* NEED_UI_LOOP_HOOK */
84
85/* Short-hand macros for LDR/STR. */ 53/* Short-hand macros for LDR/STR. */
86 54
87/* Store post decrement writeback. */ 55/* Store post decrement writeback. */
@@ -290,20 +258,8 @@ extern int (*ui_loop_hook) (int);
290 break; \ 258 break; \
291} 259}
292 260
293/*ywc 2005-03-31*/
294//teawater add for arm2x86 2005.02.17-------------------------------------------
295#ifdef DBCT
296#include "dbct/tb.h"
297#include "dbct/arm2x86_self.h"
298#endif
299//AJ2D--------------------------------------------------------------------------
300
301//Diff register
302unsigned int mirror_register_file[39];
303
304/* EMULATION of ARM6. */ 261/* EMULATION of ARM6. */
305 262
306extern int debugmode;
307int ARMul_ICE_debug(ARMul_State *state,ARMword instr,ARMword addr); 263int ARMul_ICE_debug(ARMul_State *state,ARMword instr,ARMword addr);
308#ifdef MODE32 264#ifdef MODE32
309//chy 2006-04-12, for ICE debug 265//chy 2006-04-12, for ICE debug
@@ -312,59 +268,14 @@ int ARMul_ICE_debug(ARMul_State *state,ARMword instr,ARMword addr)
312 return 0; 268 return 0;
313} 269}
314 270
315static int dump = 0;
316ARMword ARMul_Debug(ARMul_State * state, ARMword pc, ARMword instr) 271ARMword ARMul_Debug(ARMul_State * state, ARMword pc, ARMword instr)
317{ 272{
318 /*printf("[%08x] ", pc);
319 arm11_Disasm32(pc);*/
320
321 /*if (pc >= 0x0010303C && pc <= 0x00103050)
322 {
323 printf("[%08x] = %08X = ", pc, instr);
324 arm11_Disasm32(pc);
325 arm11_Dump();
326 }*/
327
328 //fprintf(stderr,"[%08x]\n", pc);
329
330 //if (pc == 0x00240C88)
331 // arm11_Dump();
332
333 /*if (pc == 0x188e04)
334 {
335 DEBUG("read %08X %08X %016X %08X %08X from %08X", state->Reg[0], state->Reg[1], state->Reg[2] | state->Reg[3] << 32, mem_Read32(state->Reg[13]), mem_Read32(state->Reg[13] + 4), state->Reg[14]);
336 }
337 if (pc == 0x21222c)
338 {
339 arm11_Dump();
340 mem_Dbugdump();
341 }*/
342
343 /*if (pc == 0x0022D168)
344 {
345 int j = 0;
346 }*/
347
348 /*if (state->Reg[4] == 0x00105734)
349 {
350 printf("[%08x] ", pc);
351 arm11_Disasm32(pc);
352 }*/
353
354 return 0; 273 return 0;
355} 274}
356 275
357/* 276ARMword ARMul_Emulate32(ARMul_State* state)
358void chy_debug()
359{
360 printf("SkyEye chy_deubeg begin\n");
361}
362*/
363ARMword
364ARMul_Emulate32 (ARMul_State * state)
365#else 277#else
366ARMword 278ARMword ARMul_Emulate26(ARMul_State* state)
367ARMul_Emulate26 (ARMul_State * state)
368#endif 279#endif
369{ 280{
370 /* The PC pipeline value depends on whether ARM 281 /* The PC pipeline value depends on whether ARM
@@ -383,39 +294,6 @@ ARMul_Emulate26 (ARMul_State * state)
383 ARMword loaded_addr=0; 294 ARMword loaded_addr=0;
384 ARMword have_bp=0; 295 ARMword have_bp=0;
385 296
386#ifdef callstacker
387 char a[256];
388#endif
389 /* shenoubang */
390 static int instr_sum = 0;
391 int reg_index = 0;
392#if DIFF_STATE
393//initialize all mirror register for follow mode
394 for (reg_index = 0; reg_index < 16; reg_index ++) {
395 mirror_register_file[reg_index] = state->Reg[reg_index];
396 }
397 mirror_register_file[CPSR_REG] = state->Cpsr;
398 mirror_register_file[R13_SVC] = state->RegBank[SVCBANK][13];
399 mirror_register_file[R14_SVC] = state->RegBank[SVCBANK][14];
400 mirror_register_file[R13_ABORT] = state->RegBank[ABORTBANK][13];
401 mirror_register_file[R14_ABORT] = state->RegBank[ABORTBANK][14];
402 mirror_register_file[R13_UNDEF] = state->RegBank[UNDEFBANK][13];
403 mirror_register_file[R14_UNDEF] = state->RegBank[UNDEFBANK][14];
404 mirror_register_file[R13_IRQ] = state->RegBank[IRQBANK][13];
405 mirror_register_file[R14_IRQ] = state->RegBank[IRQBANK][14];
406 mirror_register_file[R8_FIRQ] = state->RegBank[FIQBANK][8];
407 mirror_register_file[R9_FIRQ] = state->RegBank[FIQBANK][9];
408 mirror_register_file[R10_FIRQ] = state->RegBank[FIQBANK][10];
409 mirror_register_file[R11_FIRQ] = state->RegBank[FIQBANK][11];
410 mirror_register_file[R12_FIRQ] = state->RegBank[FIQBANK][12];
411 mirror_register_file[R13_FIRQ] = state->RegBank[FIQBANK][13];
412 mirror_register_file[R14_FIRQ] = state->RegBank[FIQBANK][14];
413 mirror_register_file[SPSR_SVC] = state->Spsr[SVCBANK];
414 mirror_register_file[SPSR_ABORT] = state->Spsr[ABORTBANK];
415 mirror_register_file[SPSR_UNDEF] = state->Spsr[UNDEFBANK];
416 mirror_register_file[SPSR_IRQ] = state->Spsr[IRQBANK];
417 mirror_register_file[SPSR_FIRQ] = state->Spsr[FIQBANK];
418#endif
419 /* Execute the next instruction. */ 297 /* Execute the next instruction. */
420 if (state->NextInstr < PRIMEPIPE) { 298 if (state->NextInstr < PRIMEPIPE) {
421 decoded = state->decoded; 299 decoded = state->decoded;
@@ -533,392 +411,38 @@ ARMul_Emulate26 (ARMul_State * state)
533 411
534 //chy 2006-04-12, for ICE debug 412 //chy 2006-04-12, for ICE debug
535 have_bp=ARMul_ICE_debug(state,instr,pc); 413 have_bp=ARMul_ICE_debug(state,instr,pc);
536#if 0 414
537 decoded =
538 ARMul_LoadInstrS (state, pc + (isize), isize);
539#endif
540 decoded_addr=pc+isize; 415 decoded_addr=pc+isize;
541#if 0 416
542 loaded = ARMul_LoadInstrS (state, pc + (isize * 2),
543 isize);
544#endif
545 loaded_addr=pc + isize * 2; 417 loaded_addr=pc + isize * 2;
546 NORMALCYCLE; 418 NORMALCYCLE;
547 if (have_bp) goto TEST_EMULATE; 419 if (have_bp) goto TEST_EMULATE;
548 break; 420 break;
549 } 421 }
550#if 0
551 int idx = 0;
552 printf("pc:%x\n", pc);
553 for (; idx < 17; idx ++) {
554 printf("R%d:%x\t", idx, state->Reg[idx]);
555 }
556 printf("\n");
557#endif
558 422
559 instr = ARMul_LoadInstrN (state, pc, isize); 423 instr = ARMul_LoadInstrN (state, pc, isize);
560 state->last_instr = state->CurrInstr; 424 state->last_instr = state->CurrInstr;
561 state->CurrInstr = instr; 425 state->CurrInstr = instr;
562 ARMul_Debug(state, pc, instr); 426 ARMul_Debug(state, pc, instr);
563#if 0
564 if((state->NumInstrs % 10000000) == 0)
565 printf("---|%p|--- %lld\n", pc, state->NumInstrs);
566 if(state->NumInstrs > (3000000000)) {
567 static int flag = 0;
568 if(pc == 0x8032ccc4) {
569 flag = 300;
570 }
571 if(flag) {
572 int idx = 0;
573 printf("------------------------------------\n");
574 printf("pc:%x\n", pc);
575 for (; idx < 17; idx ++) {
576 printf("R%d:%x\t", idx, state->Reg[idx]);
577 }
578 printf("\nN:%d\t Z:%d\t C:%d\t V:%d\n", state->NFlag, state->ZFlag, state->CFlag, state->VFlag);
579 printf("\n");
580 printf("------------------------------------\n");
581 flag--;
582 }
583 }
584#endif
585#if DIFF_STATE
586 fprintf(state->state_log, "PC:0x%x\n", pc);
587 if (pc && (pc + 8) != state->Reg[15]) {
588 printf("lucky dog\n");
589 printf("pc is %x, R15 is %x\n", pc, state->Reg[15]);
590 //exit(-1);
591 }
592 for (reg_index = 0; reg_index < 16; reg_index ++) {
593 if (state->Reg[reg_index] != mirror_register_file[reg_index]) {
594 fprintf(state->state_log, "R%d:0x%x\n", reg_index, state->Reg[reg_index]);
595 mirror_register_file[reg_index] = state->Reg[reg_index];
596 }
597 }
598 if (state->Cpsr != mirror_register_file[CPSR_REG]) {
599 fprintf(state->state_log, "Cpsr:0x%x\n", state->Cpsr);
600 mirror_register_file[CPSR_REG] = state->Cpsr;
601 }
602 if (state->RegBank[SVCBANK][13] != mirror_register_file[R13_SVC]) {
603 fprintf(state->state_log, "R13_SVC:0x%x\n", state->RegBank[SVCBANK][13]);
604 mirror_register_file[R13_SVC] = state->RegBank[SVCBANK][13];
605 }
606 if (state->RegBank[SVCBANK][14] != mirror_register_file[R14_SVC]) {
607 fprintf(state->state_log, "R14_SVC:0x%x\n", state->RegBank[SVCBANK][14]);
608 mirror_register_file[R14_SVC] = state->RegBank[SVCBANK][14];
609 }
610 if (state->RegBank[ABORTBANK][13] != mirror_register_file[R13_ABORT]) {
611 fprintf(state->state_log, "R13_ABORT:0x%x\n", state->RegBank[ABORTBANK][13]);
612 mirror_register_file[R13_ABORT] = state->RegBank[ABORTBANK][13];
613 }
614 if (state->RegBank[ABORTBANK][14] != mirror_register_file[R14_ABORT]) {
615 fprintf(state->state_log, "R14_ABORT:0x%x\n", state->RegBank[ABORTBANK][14]);
616 mirror_register_file[R14_ABORT] = state->RegBank[ABORTBANK][14];
617 }
618 if (state->RegBank[UNDEFBANK][13] != mirror_register_file[R13_UNDEF]) {
619 fprintf(state->state_log, "R13_UNDEF:0x%x\n", state->RegBank[UNDEFBANK][13]);
620 mirror_register_file[R13_UNDEF] = state->RegBank[UNDEFBANK][13];
621 }
622 if (state->RegBank[UNDEFBANK][14] != mirror_register_file[R14_UNDEF]) {
623 fprintf(state->state_log, "R14_UNDEF:0x%x\n", state->RegBank[UNDEFBANK][14]);
624 mirror_register_file[R14_UNDEF] = state->RegBank[UNDEFBANK][14];
625 }
626 if (state->RegBank[IRQBANK][13] != mirror_register_file[R13_IRQ]) {
627 fprintf(state->state_log, "R13_IRQ:0x%x\n", state->RegBank[IRQBANK][13]);
628 mirror_register_file[R13_IRQ] = state->RegBank[IRQBANK][13];
629 }
630 if (state->RegBank[IRQBANK][14] != mirror_register_file[R14_IRQ]) {
631 fprintf(state->state_log, "R14_IRQ:0x%x\n", state->RegBank[IRQBANK][14]);
632 mirror_register_file[R14_IRQ] = state->RegBank[IRQBANK][14];
633 }
634 if (state->RegBank[FIQBANK][8] != mirror_register_file[R8_FIRQ]) {
635 fprintf(state->state_log, "R8_FIRQ:0x%x\n", state->RegBank[FIQBANK][8]);
636 mirror_register_file[R8_FIRQ] = state->RegBank[FIQBANK][8];
637 }
638 if (state->RegBank[FIQBANK][9] != mirror_register_file[R9_FIRQ]) {
639 fprintf(state->state_log, "R9_FIRQ:0x%x\n", state->RegBank[FIQBANK][9]);
640 mirror_register_file[R9_FIRQ] = state->RegBank[FIQBANK][9];
641 }
642 if (state->RegBank[FIQBANK][10] != mirror_register_file[R10_FIRQ]) {
643 fprintf(state->state_log, "R10_FIRQ:0x%x\n", state->RegBank[FIQBANK][10]);
644 mirror_register_file[R10_FIRQ] = state->RegBank[FIQBANK][10];
645 }
646 if (state->RegBank[FIQBANK][11] != mirror_register_file[R11_FIRQ]) {
647 fprintf(state->state_log, "R11_FIRQ:0x%x\n", state->RegBank[FIQBANK][11]);
648 mirror_register_file[R11_FIRQ] = state->RegBank[FIQBANK][11];
649 }
650 if (state->RegBank[FIQBANK][12] != mirror_register_file[R12_FIRQ]) {
651 fprintf(state->state_log, "R12_FIRQ:0x%x\n", state->RegBank[FIQBANK][12]);
652 mirror_register_file[R12_FIRQ] = state->RegBank[FIQBANK][12];
653 }
654 if (state->RegBank[FIQBANK][13] != mirror_register_file[R13_FIRQ]) {
655 fprintf(state->state_log, "R13_FIRQ:0x%x\n", state->RegBank[FIQBANK][13]);
656 mirror_register_file[R13_FIRQ] = state->RegBank[FIQBANK][13];
657 }
658 if (state->RegBank[FIQBANK][14] != mirror_register_file[R14_FIRQ]) {
659 fprintf(state->state_log, "R14_FIRQ:0x%x\n", state->RegBank[FIQBANK][14]);
660 mirror_register_file[R14_FIRQ] = state->RegBank[FIQBANK][14];
661 }
662 if (state->Spsr[SVCBANK] != mirror_register_file[SPSR_SVC]) {
663 fprintf(state->state_log, "SPSR_SVC:0x%x\n", state->Spsr[SVCBANK]);
664 mirror_register_file[SPSR_SVC] = state->RegBank[SVCBANK];
665 }
666 if (state->Spsr[ABORTBANK] != mirror_register_file[SPSR_ABORT]) {
667 fprintf(state->state_log, "SPSR_ABORT:0x%x\n", state->Spsr[ABORTBANK]);
668 mirror_register_file[SPSR_ABORT] = state->RegBank[ABORTBANK];
669 }
670 if (state->Spsr[UNDEFBANK] != mirror_register_file[SPSR_UNDEF]) {
671 fprintf(state->state_log, "SPSR_UNDEF:0x%x\n", state->Spsr[UNDEFBANK]);
672 mirror_register_file[SPSR_UNDEF] = state->RegBank[UNDEFBANK];
673 }
674 if (state->Spsr[IRQBANK] != mirror_register_file[SPSR_IRQ]) {
675 fprintf(state->state_log, "SPSR_IRQ:0x%x\n", state->Spsr[IRQBANK]);
676 mirror_register_file[SPSR_IRQ] = state->RegBank[IRQBANK];
677 }
678 if (state->Spsr[FIQBANK] != mirror_register_file[SPSR_FIRQ]) {
679 fprintf(state->state_log, "SPSR_FIRQ:0x%x\n", state->Spsr[FIQBANK]);
680 mirror_register_file[SPSR_FIRQ] = state->RegBank[FIQBANK];
681 }
682#endif
683
684#if 0
685 uint32_t alex = 0;
686 static int flagged = 0;
687 if ((flagged == 0) && (pc == 0xb224)) {
688 flagged++;
689 }
690 if ((flagged == 1) && (pc == 0x1a800)) {
691 flagged++;
692 }
693 if (flagged == 3) {
694 printf("---|%p|--- %x\n", pc, state->NumInstrs);
695 for (alex = 0; alex < 15; alex++) {
696 printf("R%02d % 8x\n", alex, state->Reg[alex]);
697 }
698 printf("R%02d % 8x\n", alex, state->Reg[alex] - 8);
699 printf("CPS %x%07x\n", (state->NFlag<<3 | state->ZFlag<<2 | state->CFlag<<1 | state->VFlag), state->Cpsr & 0xfffffff);
700 } else {
701 if (state->NumInstrs < 0x400000) {
702 //exit(-1);
703 }
704 }
705#endif
706
707 /*if (state->EventSet)
708 ARMul_EnvokeEvent (state);*/
709
710#if 0
711 /* do profiling for code coverage */
712 if (skyeye_config.code_cov.prof_on)
713 cov_prof(EXEC_FLAG, pc);
714#endif
715//2003-07-11 chy: for test
716#if 0
717 if (skyeye_config.log.logon >= 1) {
718 if (state->NumInstrs >= skyeye_config.log.start &&
719 state->NumInstrs <= skyeye_config.log.end) {
720 static int mybegin = 0;
721 static int myinstrnum = 0;
722 if (mybegin == 0)
723 mybegin = 1;
724#if 0
725 if (state->NumInstrs == 3695) {
726 printf ("***********SKYEYE: numinstr = 3695\n");
727 }
728 static int mybeg2 = 0;
729 static int mybeg3 = 0;
730 static int mybeg4 = 0;
731 static int mybeg5 = 0;
732
733 if (pc == 0xa0008000) {
734 //mybegin=1;
735 printf ("************SKYEYE: real vmlinux begin now numinstr is %llu ****************\n", state->NumInstrs);
736 }
737 427
738 //chy 2003-09-02 test fiq
739 if (state->NumInstrs == 67347000) {
740 printf ("***********SKYEYE: numinstr = 67347000, begin log\n");
741 mybegin = 1;
742 }
743 if (pc == 0xc00087b4) { //numinstr=67348714
744 mybegin = 1;
745 printf ("************SKYEYE: test irq now numinstr is %llu ****************\n", state->NumInstrs);
746 }
747 if (pc == 0xc00087b8) { //in start_kernel::sti()
748 mybeg4 = 1;
749 printf ("************SKYEYE: startkerenl: sti now numinstr is %llu ********\n", state->NumInstrs);
750 }
751 /*if (pc==0xc001e4f4||pc==0xc001e4f8||pc==0xc001e4fc||pc==0xc001e500||pc==0xffff0004) { //MRA instr */
752 if (pc == 0xc001e500) { //MRA instr
753 mybeg5 = 1;
754 printf ("************SKYEYE: MRA instr now numinstr is %llu ********\n", state->NumInstrs);
755 }
756 if (pc >= 0xc0000000 && mybeg2 == 0) {
757 mybeg2 = 1;
758 printf ("************SKYEYE: enable mmu&cache, now numinstr is %llu **************\n", state->NumInstrs);
759 SKYEYE_OUTREGS (stderr);
760 printf ("************************************************************************\n");
761 }
762 //chy 2003-09-01 test after tlb-flush
763 if (pc == 0xc00261ac) {
764 //sleep(2);
765 mybeg3 = 1;
766 printf ("************SKYEYE: after tlb-flush numinstr is %llu ****************\n", state->NumInstrs);
767 }
768 if (mybeg3 == 1) {
769 SKYEYE_OUTREGS (skyeye_logfd);
770 SKYEYE_OUTMOREREGS (skyeye_logfd);
771 fprintf (skyeye_logfd, "\n");
772 }
773#endif
774 if (mybegin == 1) {
775 //fprintf(skyeye_logfd,"p %x,i %x,d %x,l %x,",pc,instr,decoded,loaded);
776 //chy for test 20050729
777 /*if (state->NumInstrs>=3302294) {
778 if (pc==0x100c9d4 && instr==0xe1b0f00e){
779 chy_debug();
780 printf("*********************************************\n");
781 printf("******SKYEYE N %llx :p %x,i %x\n SKYEYE******\n",state->NumInstrs,pc,instr);
782 printf("*********************************************\n");
783 }
784 */
785 if (skyeye_config.log.logon >= 1)
786 /*
787 fprintf (skyeye_logfd,
788 "N %llx :p %x,i %x,",
789 state->NumInstrs, pc,
790 #ifdef MODET
791 TFLAG ? instr & 0xffff : instr
792 #else
793 instr
794 #endif
795 );
796 */
797 fprintf(skyeye_logfd, "pc=0x%x,r3=0x%x\n", pc, state->Reg[3]);
798 if (skyeye_config.log.logon >= 2)
799 SKYEYE_OUTREGS (skyeye_logfd);
800 if (skyeye_config.log.logon >= 3)
801 SKYEYE_OUTMOREREGS
802 (skyeye_logfd);
803 //fprintf (skyeye_logfd, "\n");
804 if (skyeye_config.log.length > 0) {
805 myinstrnum++;
806 if (myinstrnum >=
807 skyeye_config.log.
808 length) {
809 myinstrnum = 0;
810 fflush (skyeye_logfd);
811 fseek (skyeye_logfd,
812 0L, SEEK_SET);
813 }
814 }
815 }
816 //SKYEYE_OUTREGS(skyeye_logfd);
817 //SKYEYE_OUTMOREREGS(skyeye_logfd);
818 }
819 }
820#endif
821#if 0 /* Enable this for a helpful bit of debugging when tracing is needed. */
822 fprintf (stderr, "pc: %x, instr: %x\n", pc & ~1, instr);
823 if (instr == 0)
824 abort ();
825#endif
826#if 0 /* Enable this code to help track down stack alignment bugs. */
827 {
828 static ARMword old_sp = -1;
829
830 if (old_sp != state->Reg[13]) {
831 old_sp = state->Reg[13];
832 fprintf (stderr,
833 "pc: %08x: SP set to %08x%s\n",
834 pc & ~1, old_sp,
835 (old_sp % 8) ? " [UNALIGNED!]" : "");
836 }
837 }
838#endif
839 /* Any exceptions ? */ 428 /* Any exceptions ? */
840 if (state->NresetSig == LOW) { 429 if (state->NresetSig == LOW) {
841 ARMul_Abort (state, ARMul_ResetV); 430 ARMul_Abort (state, ARMul_ResetV);
842
843 /*added energy_prof statement by ksh in 2004-11-26 */
844 //chy 2005-07-28 for standalone
845 //ARMul_do_energy(state,instr,pc);
846 break; 431 break;
847 } else if (!state->NfiqSig && !FFLAG) { 432 } else if (!state->NfiqSig && !FFLAG) {
848 ARMul_Abort (state, ARMul_FIQV); 433 ARMul_Abort (state, ARMul_FIQV);
849 /*added energy_prof statement by ksh in 2004-11-26 */
850 //chy 2005-07-28 for standalone
851 //ARMul_do_energy(state,instr,pc);
852 break; 434 break;
853 } else if (!state->NirqSig && !IFLAG) { 435 } else if (!state->NirqSig && !IFLAG) {
854 ARMul_Abort (state, ARMul_IRQV); 436 ARMul_Abort (state, ARMul_IRQV);
855 /*added energy_prof statement by ksh in 2004-11-26 */
856 //chy 2005-07-28 for standalone
857 //ARMul_do_energy(state,instr,pc);
858 break; 437 break;
859 } 438 }
860 439
861//teawater add for arm2x86 2005.04.26-------------------------------------------
862#if 0
863// if (state->pc == 0xc011a868 || state->pc == 0xc011a86c) {
864 if (state->NumInstrs == 1671574 || state->NumInstrs == 1671573 || state->NumInstrs == 1671572
865 || state->NumInstrs == 1671575) {
866 for (reg_index = 0; reg_index < 16; reg_index ++) {
867 printf("R%d:%x\t", reg_index, state->Reg[reg_index]);
868 }
869 printf("\n");
870 }
871#endif
872 if (state->tea_pc) {
873 int i;
874
875 if (state->tea_reg_fd) {
876 fprintf (state->tea_reg_fd, "\n");
877 for (i = 0; i < 15; i++) {
878 fprintf (state->tea_reg_fd, "%x,",
879 state->Reg[i]);
880 }
881 fprintf (state->tea_reg_fd, "%x,", pc);
882 state->Cpsr = ARMul_GetCPSR (state);
883 fprintf (state->tea_reg_fd, "%x\n",
884 state->Cpsr);
885 } else {
886 printf ("\n");
887 for (i = 0; i < 15; i++) {
888 printf ("%x,", state->Reg[i]);
889 }
890 printf ("%x,", pc);
891 state->Cpsr = ARMul_GetCPSR (state);
892 printf ("%x\n", state->Cpsr);
893 }
894 }
895//AJ2D--------------------------------------------------------------------------
896
897 /*if (state->CallDebug > 0) {
898 instr = ARMul_Debug (state, pc, instr);
899 if (state->Emulate < ONCE) {
900 state->NextInstr = RESUME;
901 break;
902 }
903 if (state->Debug) {
904 fprintf (stderr,
905 "sim: At %08lx Instr %08lx Mode %02lx\n",
906 pc, instr, state->Mode);
907 (void) fgetc (stdin);
908 }
909 }
910 else*/
911 if (state->Emulate < ONCE) { 440 if (state->Emulate < ONCE) {
912 state->NextInstr = RESUME; 441 state->NextInstr = RESUME;
913 break; 442 break;
914 } 443 }
915 //io_do_cycle (state); 444
916 state->NumInstrs++; 445 state->NumInstrs++;
917#if 0
918 if (state->NumInstrs % 10000000 == 0) {
919 printf("10 MIPS instr have been executed\n");
920 }
921#endif
922 446
923#ifdef MODET 447#ifdef MODET
924 /* Provide Thumb instruction decoding. If the processor is in Thumb 448 /* Provide Thumb instruction decoding. If the processor is in Thumb
@@ -990,12 +514,6 @@ ARMul_Emulate26 (ARMul_State * state)
990 /* clrex do nothing here temporary */ 514 /* clrex do nothing here temporary */
991 if (instr == 0xf57ff01f) { 515 if (instr == 0xf57ff01f) {
992 //printf("clrex \n"); 516 //printf("clrex \n");
993#if 0
994 int i;
995 for(i = 0; i < 128; i++) {
996 state->exclusive_tag_array[i] = 0xffffffff;
997 }
998#endif
999 /* shenoubang 2012-3-14 refer the dyncom_interpreter */ 517 /* shenoubang 2012-3-14 refer the dyncom_interpreter */
1000 state->exclusive_tag_array[0] = 0xFFFFFFFF; 518 state->exclusive_tag_array[0] = 0xFFFFFFFF;
1001 state->exclusive_access_state = 0; 519 state->exclusive_access_state = 0;
@@ -1169,9 +687,9 @@ mainswitch:
1169 Rn = BITS(0, 3); 687 Rn = BITS(0, 3);
1170 lsb = BITS(7, 11); 688 lsb = BITS(7, 11);
1171 msb = BITS(16, 20); //-V519 689 msb = BITS(16, 20); //-V519
1172 if ((Rd == 15)) { 690 if (Rd == 15) {
1173 ARMul_UndefInstr (state, instr); 691 ARMul_UndefInstr (state, instr);
1174 } else if ((Rn == 15)) { 692 } else if (Rn == 15) {
1175 data = state->Reg[Rd]; 693 data = state->Reg[Rd];
1176 tmp_rd = ((ARMword)(data << (31 - lsb)) >> (31 - lsb)); 694 tmp_rd = ((ARMword)(data << (31 - lsb)) >> (31 - lsb));
1177 dst = ((data >> msb) << (msb - lsb)); 695 dst = ((data >> msb) << (msb - lsb));
@@ -3209,16 +2727,6 @@ mainswitch:
3209 break; 2727 break;
3210 2728
3211 case 0x6e: /* Store Byte, WriteBack, Post Inc, Reg. */ 2729 case 0x6e: /* Store Byte, WriteBack, Post Inc, Reg. */
3212#if 0
3213 if (state->is_v6) {
3214 int Rm = 0;
3215 /* utxb */
3216 if (BITS(15, 19) == 0xf && BITS(4, 7) == 0x7) {
3217 Rm = (RHS >> (8 * BITS(10, 11))) & 0xff;
3218 DEST = Rm;
3219 }
3220 }
3221#endif
3222 if (BIT (4)) { 2730 if (BIT (4)) {
3223#ifdef MODE32 2731#ifdef MODE32
3224 if (state->is_v6 2732 if (state->is_v6
@@ -3656,13 +3164,6 @@ mainswitch:
3656#endif 3164#endif
3657 state->Reg[15] = pc + 8 + POSBRANCH; 3165 state->Reg[15] = pc + 8 + POSBRANCH;
3658 FLUSHPIPE; 3166 FLUSHPIPE;
3659
3660#ifdef callstacker
3661 memset(a, 0, 256);
3662 aufloeser(a, state->Reg[15]);
3663 printf("call %08X %08X %s(%08X %08X %08X %08X %08X %08X %08X)\n", state->Reg[14], state->Reg[15], a, state->Reg[0], state->Reg[1], state->Reg[2], state->Reg[3], mem_Read32(state->Reg[13]), mem_Read32(state->Reg[13] - 4),mem_Read32(state->Reg[13] - 8));
3664#endif
3665
3666 break; 3167 break;
3667 3168
3668 /* Branch and Link backward. */ 3169 /* Branch and Link backward. */
@@ -3682,13 +3183,6 @@ mainswitch:
3682#endif 3183#endif
3683 state->Reg[15] = pc + 8 + NEGBRANCH; 3184 state->Reg[15] = pc + 8 + NEGBRANCH;
3684 FLUSHPIPE; 3185 FLUSHPIPE;
3685
3686#ifdef callstacker
3687 memset(a, 0, 256);
3688 aufloeser(a, state->Reg[15]);
3689 printf("call %08X %08X %s(%08X %08X %08X %08X %08X %08X %08X)\n", state->Reg[14], state->Reg[15], a, state->Reg[0], state->Reg[1], state->Reg[2], state->Reg[3], mem_Read32(state->Reg[13]), mem_Read32(state->Reg[13] - 4),mem_Read32(state->Reg[13] - 8));
3690#endif
3691
3692 break; 3186 break;
3693 3187
3694 /* Co-Processor Data Transfers. */ 3188 /* Co-Processor Data Transfers. */
@@ -3909,165 +3403,6 @@ mainswitch:
3909donext: 3403donext:
3910#endif 3404#endif
3911 state->pc = pc; 3405 state->pc = pc;
3912#if 0
3913 /* shenoubang */
3914 instr_sum++;
3915 int i, j;
3916 i = j = 0;
3917 if (instr_sum >= 7388648) {
3918 //if (pc == 0xc0008ab4) {
3919 // printf("instr_sum: %d\n", instr_sum);
3920 // start_kernel : 0xc000895c
3921 printf("--------------------------------------------------\n");
3922 for (i = 0; i < 16; i++) {
3923 printf("[R%02d]:[0x%08x]\t", i, state->Reg[i]);
3924 if ((i % 3) == 2) {
3925 printf("\n");
3926 }
3927 }
3928 printf("[cpr]:[0x%08x]\t[spr0]:[0x%08x]\n", state->Cpsr, state->Spsr[0]);
3929 for (j = 1; j < 7; j++) {
3930 printf("[spr%d]:[0x%08x]\t", j, state->Spsr[j]);
3931 if ((j % 4) == 3) {
3932 printf("\n");
3933 }
3934 }
3935 printf("\n[PC]:[0x%08x]\t[INST]:[0x%08x]\t[COUNT]:[%d]\n", pc, instr, instr_sum);
3936 printf("--------------------------------------------------\n");
3937 }
3938#endif
3939
3940#if 0
3941 fprintf(state->state_log, "PC:0x%x\n", pc);
3942 for (reg_index = 0; reg_index < 16; reg_index ++) {
3943 if (state->Reg[reg_index] != mirror_register_file[reg_index]) {
3944 fprintf(state->state_log, "R%d:0x%x\n", reg_index, state->Reg[reg_index]);
3945 mirror_register_file[reg_index] = state->Reg[reg_index];
3946 }
3947 }
3948 if (state->Cpsr != mirror_register_file[CPSR_REG]) {
3949 fprintf(state->state_log, "Cpsr:0x%x\n", state->Cpsr);
3950 mirror_register_file[CPSR_REG] = state->Cpsr;
3951 }
3952 if (state->RegBank[SVCBANK][13] != mirror_register_file[R13_SVC]) {
3953 fprintf(state->state_log, "R13_SVC:0x%x\n", state->RegBank[SVCBANK][13]);
3954 mirror_register_file[R13_SVC] = state->RegBank[SVCBANK][13];
3955 }
3956 if (state->RegBank[SVCBANK][14] != mirror_register_file[R14_SVC]) {
3957 fprintf(state->state_log, "R14_SVC:0x%x\n", state->RegBank[SVCBANK][14]);
3958 mirror_register_file[R14_SVC] = state->RegBank[SVCBANK][14];
3959 }
3960 if (state->RegBank[ABORTBANK][13] != mirror_register_file[R13_ABORT]) {
3961 fprintf(state->state_log, "R13_ABORT:0x%x\n", state->RegBank[ABORTBANK][13]);
3962 mirror_register_file[R13_ABORT] = state->RegBank[ABORTBANK][13];
3963 }
3964 if (state->RegBank[ABORTBANK][14] != mirror_register_file[R14_ABORT]) {
3965 fprintf(state->state_log, "R14_ABORT:0x%x\n", state->RegBank[ABORTBANK][14]);
3966 mirror_register_file[R14_ABORT] = state->RegBank[ABORTBANK][14];
3967 }
3968 if (state->RegBank[UNDEFBANK][13] != mirror_register_file[R13_UNDEF]) {
3969 fprintf(state->state_log, "R13_UNDEF:0x%x\n", state->RegBank[UNDEFBANK][13]);
3970 mirror_register_file[R13_UNDEF] = state->RegBank[UNDEFBANK][13];
3971 }
3972 if (state->RegBank[UNDEFBANK][14] != mirror_register_file[R14_UNDEF]) {
3973 fprintf(state->state_log, "R14_UNDEF:0x%x\n", state->RegBank[UNDEFBANK][14]);
3974 mirror_register_file[R14_UNDEF] = state->RegBank[UNDEFBANK][14];
3975 }
3976 if (state->RegBank[IRQBANK][13] != mirror_register_file[R13_IRQ]) {
3977 fprintf(state->state_log, "R13_IRQ:0x%x\n", state->RegBank[IRQBANK][13]);
3978 mirror_register_file[R13_IRQ] = state->RegBank[IRQBANK][13];
3979 }
3980 if (state->RegBank[IRQBANK][14] != mirror_register_file[R14_IRQ]) {
3981 fprintf(state->state_log, "R14_IRQ:0x%x\n", state->RegBank[IRQBANK][14]);
3982 mirror_register_file[R14_IRQ] = state->RegBank[IRQBANK][14];
3983 }
3984 if (state->RegBank[FIQBANK][8] != mirror_register_file[R8_FIRQ]) {
3985 fprintf(state->state_log, "R8_FIRQ:0x%x\n", state->RegBank[FIQBANK][8]);
3986 mirror_register_file[R8_FIRQ] = state->RegBank[FIQBANK][8];
3987 }
3988 if (state->RegBank[FIQBANK][9] != mirror_register_file[R9_FIRQ]) {
3989 fprintf(state->state_log, "R9_FIRQ:0x%x\n", state->RegBank[FIQBANK][9]);
3990 mirror_register_file[R9_FIRQ] = state->RegBank[FIQBANK][9];
3991 }
3992 if (state->RegBank[FIQBANK][10] != mirror_register_file[R10_FIRQ]) {
3993 fprintf(state->state_log, "R10_FIRQ:0x%x\n", state->RegBank[FIQBANK][10]);
3994 mirror_register_file[R10_FIRQ] = state->RegBank[FIQBANK][10];
3995 }
3996 if (state->RegBank[FIQBANK][11] != mirror_register_file[R11_FIRQ]) {
3997 fprintf(state->state_log, "R11_FIRQ:0x%x\n", state->RegBank[FIQBANK][11]);
3998 mirror_register_file[R11_FIRQ] = state->RegBank[FIQBANK][11];
3999 }
4000 if (state->RegBank[FIQBANK][12] != mirror_register_file[R12_FIRQ]) {
4001 fprintf(state->state_log, "R12_FIRQ:0x%x\n", state->RegBank[FIQBANK][12]);
4002 mirror_register_file[R12_FIRQ] = state->RegBank[FIQBANK][12];
4003 }
4004 if (state->RegBank[FIQBANK][13] != mirror_register_file[R13_FIRQ]) {
4005 fprintf(state->state_log, "R13_FIRQ:0x%x\n", state->RegBank[FIQBANK][13]);
4006 mirror_register_file[R13_FIRQ] = state->RegBank[FIQBANK][13];
4007 }
4008 if (state->RegBank[FIQBANK][14] != mirror_register_file[R14_FIRQ]) {
4009 fprintf(state->state_log, "R14_FIRQ:0x%x\n", state->RegBank[FIQBANK][14]);
4010 mirror_register_file[R14_FIRQ] = state->RegBank[FIQBANK][14];
4011 }
4012 if (state->Spsr[SVCBANK] != mirror_register_file[SPSR_SVC]) {
4013 fprintf(state->state_log, "SPSR_SVC:0x%x\n", state->Spsr[SVCBANK]);
4014 mirror_register_file[SPSR_SVC] = state->RegBank[SVCBANK];
4015 }
4016 if (state->Spsr[ABORTBANK] != mirror_register_file[SPSR_ABORT]) {
4017 fprintf(state->state_log, "SPSR_ABORT:0x%x\n", state->Spsr[ABORTBANK]);
4018 mirror_register_file[SPSR_ABORT] = state->RegBank[ABORTBANK];
4019 }
4020 if (state->Spsr[UNDEFBANK] != mirror_register_file[SPSR_UNDEF]) {
4021 fprintf(state->state_log, "SPSR_UNDEF:0x%x\n", state->Spsr[UNDEFBANK]);
4022 mirror_register_file[SPSR_UNDEF] = state->RegBank[UNDEFBANK];
4023 }
4024 if (state->Spsr[IRQBANK] != mirror_register_file[SPSR_IRQ]) {
4025 fprintf(state->state_log, "SPSR_IRQ:0x%x\n", state->Spsr[IRQBANK]);
4026 mirror_register_file[SPSR_IRQ] = state->RegBank[IRQBANK];
4027 }
4028 if (state->Spsr[FIQBANK] != mirror_register_file[SPSR_FIRQ]) {
4029 fprintf(state->state_log, "SPSR_FIRQ:0x%x\n", state->Spsr[FIQBANK]);
4030 mirror_register_file[SPSR_FIRQ] = state->RegBank[FIQBANK];
4031 }
4032
4033#endif
4034
4035#ifdef NEED_UI_LOOP_HOOK
4036 if (ui_loop_hook != NULL && ui_loop_hook_counter-- < 0) {
4037 ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL;
4038 ui_loop_hook (0);
4039 }
4040#endif /* NEED_UI_LOOP_HOOK */
4041
4042 /*added energy_prof statement by ksh in 2004-11-26 */
4043 //chy 2005-07-28 for standalone
4044 //ARMul_do_energy(state,instr,pc);
4045//teawater add for record reg value to ./reg.txt 2005.07.10---------------------
4046 if (state->tea_break_ok && pc == state->tea_break_addr) {
4047 //ARMul_Debug (state, 0, 0);
4048 state->tea_break_ok = 0;
4049 } else {
4050 state->tea_break_ok = 1;
4051 }
4052//AJ2D--------------------------------------------------------------------------
4053//chy 2006-04-14 for ctrl-c debug
4054#if 0
4055 if (debugmode) {
4056 if (instr != ARMul_ABORTWORD) {
4057 remote_interrupt_test_time++;
4058 //chy 2006-04-14 2000 should be changed in skyeye_conf ???!!!
4059 if (remote_interrupt_test_time >= 2000) {
4060 remote_interrupt_test_time=0;
4061 if (remote_interrupt()) {
4062 //for test
4063 //printf("SKYEYE: ICE_debug recv Ctrl_C\n");
4064 state->EndCondition = 0;
4065 state->Emulate = STOP;
4066 }
4067 }
4068 }
4069 }
4070#endif
4071 3406
4072 /* jump out every time */ 3407 /* jump out every time */
4073 //state->EndCondition = 0; 3408 //state->EndCondition = 0;
@@ -4076,10 +3411,6 @@ donext:
4076TEST_EMULATE: 3411TEST_EMULATE:
4077 if (state->Emulate == ONCE) 3412 if (state->Emulate == ONCE)
4078 state->Emulate = STOP; 3413 state->Emulate = STOP;
4079 //chy: 2003-08-23: should not use CHANGEMODE !!!!
4080 /* If we have changed mode, allow the PC to advance before stopping. */
4081 // else if (state->Emulate == CHANGEMODE)
4082 // continue;
4083 else if (state->Emulate != RUN) 3414 else if (state->Emulate != RUN)
4084 break; 3415 break;
4085 } 3416 }
@@ -4096,225 +3427,14 @@ exit:
4096 return pc; 3427 return pc;
4097 } 3428 }
4098 3429
4099//teawater add for arm2x86 2005.02.17-------------------------------------------
4100 /*ywc 2005-04-01*/
4101//#include "tb.h"
4102//#include "arm2x86_self.h"
4103
4104 static volatile void (*gen_func) (void); 3430 static volatile void (*gen_func) (void);
4105//static volatile ARMul_State *tmp_st; 3431
4106//static volatile ARMul_State *save_st;
4107 static volatile uint32_t tmp_st; 3432 static volatile uint32_t tmp_st;
4108 static volatile uint32_t save_st; 3433 static volatile uint32_t save_st;
4109 static volatile uint32_t save_T0; 3434 static volatile uint32_t save_T0;
4110 static volatile uint32_t save_T1; 3435 static volatile uint32_t save_T1;
4111 static volatile uint32_t save_T2; 3436 static volatile uint32_t save_T2;
4112 3437
4113#ifdef MODE32
4114#ifdef DBCT
4115//teawater change for debug function 2005.07.09---------------------------------
4116 ARMword
4117 ARMul_Emulate32_dbct (ARMul_State * state) {
4118 static int init = 0;
4119 static FILE *fd;
4120
4121 /*if (!init) {
4122 fd = fopen("./pc.txt", "w");
4123 if (!fd) {
4124 exit(-1);
4125 }
4126 init = 1;
4127 } */
4128
4129 state->Reg[15] += INSN_SIZE;
4130 do {
4131 /*if (skyeye_config.log.logon>=1) {
4132 if (state->NumInstrs>=skyeye_config.log.start && state->NumInstrs<=skyeye_config.log.end) {
4133 static int mybegin=0;
4134 static int myinstrnum=0;
4135
4136 if (mybegin==0) mybegin=1;
4137 if (mybegin==1) {
4138 state->Reg[15] -= INSN_SIZE;
4139 if (skyeye_config.log.logon>=1) fprintf(skyeye_logfd,"N %llx :p %x,i %x,",state->NumInstrs, (state->Reg[15] - INSN_SIZE), instr);
4140 if (skyeye_config.log.logon>=2) SKYEYE_OUTREGS(skyeye_logfd);
4141 if (skyeye_config.log.logon>=3) SKYEYE_OUTMOREREGS(skyeye_logfd);
4142 fprintf(skyeye_logfd,"\n");
4143 if (skyeye_config.log.length>0) {
4144 myinstrnum++;
4145 if (myinstrnum>=skyeye_config.log.length) {
4146 myinstrnum=0;
4147 fflush(skyeye_logfd);
4148 fseek(skyeye_logfd,0L,SEEK_SET);
4149 }
4150 }
4151 state->Reg[15] += INSN_SIZE;
4152 }
4153 }
4154 } */
4155 state->trap = 0;
4156 gen_func =
4157 (void *) tb_find (state, state->Reg[15] - INSN_SIZE);
4158 if (!gen_func) {
4159 //fprintf(stderr, "SKYEYE: tb_find: Error in find the translate block.\n");
4160 //exit(-1);
4161 //TRAP_INSN_ABORT
4162 //TEA_OUT(printf("\n------------\npc:%x\n", state->Reg[15] - INSN_SIZE));
4163 //TEA_OUT(printf("TRAP_INSN_ABORT\n"));
4164//teawater add for xscale(arm v5) 2005.09.01------------------------------------
4165 /*XScale_set_fsr_far(state, ARMul_CP15_R5_MMU_EXCPT, state->Reg[15] - INSN_SIZE);
4166 state->Reg[15] += INSN_SIZE;
4167 ARMul_Abort(state, ARMul_PrefetchAbortV);
4168 state->Reg[15] += INSN_SIZE;
4169 goto next; */
4170 state->trap = TRAP_INSN_ABORT;
4171 goto check;
4172//AJ2D--------------------------------------------------------------------------
4173 }
4174
4175 save_st = (uint32_t) st;
4176 save_T0 = T0;
4177 save_T1 = T1;
4178 save_T2 = T2;
4179 tmp_st = (uint32_t) state;
4180 wmb ();
4181 st = (ARMul_State *) tmp_st;
4182 gen_func ();
4183 st = (ARMul_State *) save_st;
4184 T0 = save_T0;
4185 T1 = save_T1;
4186 T2 = save_T2;
4187
4188 /*if (state->trap != TRAP_OUT) {
4189 state->tea_break_ok = 1;
4190 }
4191 if (state->trap <= TRAP_SET_R15) {
4192 goto next;
4193 } */
4194 //TEA_OUT(printf("\n------------\npc:%x\n", state->Reg[15] - INSN_SIZE));
4195//teawater add check thumb 2005.07.21-------------------------------------------
4196 /*if (TFLAG) {
4197 state->Reg[15] -= 2;
4198 return(state->Reg[15]);
4199 } */
4200//AJ2D--------------------------------------------------------------------------
4201
4202//teawater add for xscale(arm v5) 2005.09.01------------------------------------
4203check:
4204//AJ2D--------------------------------------------------------------------------
4205 switch (state->trap) {
4206 case TRAP_RESET: {
4207 //TEA_OUT(printf("TRAP_RESET\n"));
4208 ARMul_Abort (state, ARMul_ResetV);
4209 state->Reg[15] += INSN_SIZE;
4210 }
4211 break;
4212 case TRAP_UNPREDICTABLE: {
4213 //ARMul_Debug (state, 0, 0);
4214 }
4215 break;
4216 case TRAP_INSN_UNDEF: {
4217 //TEA_OUT(printf("TRAP_INSN_UNDEF\n"));
4218 state->Reg[15] += INSN_SIZE;
4219 ARMul_UndefInstr (state, 0);
4220 state->Reg[15] += INSN_SIZE;
4221 }
4222 break;
4223 case TRAP_SWI: {
4224 //TEA_OUT(printf("TRAP_SWI\n"));
4225 state->Reg[15] += INSN_SIZE;
4226 ARMul_Abort (state, ARMul_SWIV);
4227 state->Reg[15] += INSN_SIZE;
4228 }
4229 break;
4230//teawater add for xscale(arm v5) 2005.09.01------------------------------------
4231 case TRAP_INSN_ABORT: {
4232 /*XScale_set_fsr_far (state,
4233 ARMul_CP15_R5_MMU_EXCPT,
4234 state->Reg[15] -
4235 INSN_SIZE);*/
4236 state->Reg[15] += INSN_SIZE;
4237 ARMul_Abort (state, ARMul_PrefetchAbortV);
4238 state->Reg[15] += INSN_SIZE;
4239 }
4240 break;
4241//AJ2D--------------------------------------------------------------------------
4242 case TRAP_DATA_ABORT: {
4243 //TEA_OUT(printf("TRAP_DATA_ABORT\n"));
4244 state->Reg[15] += INSN_SIZE;
4245 ARMul_Abort (state, ARMul_DataAbortV);
4246 state->Reg[15] += INSN_SIZE;
4247 }
4248 break;
4249 case TRAP_IRQ: {
4250 //TEA_OUT(printf("TRAP_IRQ\n"));
4251 state->Reg[15] += INSN_SIZE;
4252 ARMul_Abort (state, ARMul_IRQV);
4253 state->Reg[15] += INSN_SIZE;
4254 }
4255 break;
4256 case TRAP_FIQ: {
4257 //TEA_OUT(printf("TRAP_FIQ\n"));
4258 state->Reg[15] += INSN_SIZE;
4259 ARMul_Abort (state, ARMul_FIQV);
4260 state->Reg[15] += INSN_SIZE;
4261 }
4262 break;
4263 case TRAP_SETS_R15: {
4264 //TEA_OUT(printf("TRAP_SETS_R15\n"));
4265 /*if (state->Bank > 0) {
4266 state->Cpsr = state->Spsr[state->Bank];
4267 ARMul_CPSRAltered (state);
4268 } */
4269 WriteSR15 (state, state->Reg[15]);
4270 }
4271 break;
4272 case TRAP_SET_CPSR: {
4273 //TEA_OUT(printf("TRAP_SET_CPSR\n"));
4274 //chy 2006-02-15 USERBANK=SYSTEMBANK=0
4275 //chy 2006-02-16 should use Mode to test
4276 //if (state->Bank > 0) {
4277 if (state->Mode != USER26MODE && state->Mode != USER32MODE) {
4278 //ARMul_CPSRAltered (state);
4279 }
4280 state->Reg[15] += INSN_SIZE;
4281 }
4282 break;
4283 case TRAP_OUT: {
4284 //TEA_OUT(printf("TRAP_OUT\n"));
4285 goto out;
4286 }
4287 break;
4288 case TRAP_BREAKPOINT: {
4289 //TEA_OUT(printf("TRAP_BREAKPOINT\n"));
4290 state->Reg[15] -= INSN_SIZE;
4291 if (!ARMul_OSHandleSWI
4292 (state, SWI_Breakpoint)) {
4293 ARMul_Abort (state, ARMul_SWIV);
4294 }
4295 state->Reg[15] += INSN_SIZE;
4296 }
4297 break;
4298 }
4299
4300next:
4301 if (state->Emulate == ONCE) {
4302 state->Emulate = STOP;
4303 break;
4304 } else if (state->Emulate != RUN) {
4305 break;
4306 }
4307 } while (!state->stop_simulator);
4308
4309out:
4310 state->Reg[15] -= INSN_SIZE;
4311 return (state->Reg[15]);
4312 }
4313#endif
4314//AJ2D--------------------------------------------------------------------------
4315#endif
4316//AJ2D--------------------------------------------------------------------------
4317
4318 /* This routine evaluates most Data Processing register RHS's with the S 3438 /* This routine evaluates most Data Processing register RHS's with the S
4319 bit clear. It is intended to be called from the macro DPRegRHS, which 3439 bit clear. It is intended to be called from the macro DPRegRHS, which
4320 filters the common case of an unshifted register with in line code. */ 3440 filters the common case of an unshifted register with in line code. */
@@ -4672,21 +3792,6 @@ out:
4672 return BITS (0, 3) | (BITS (8, 11) << 4); 3792 return BITS (0, 3) | (BITS (8, 11) << 4);
4673 } 3793 }
4674 3794
4675 /* This function does the work of loading a word for a LDR instruction. */
4676#define MEM_LOAD_LOG(description) if (skyeye_config.log.memlogon >= 1) { \
4677 fprintf(skyeye_logfd, \
4678 "m LOAD %s: N %llx :p %x :i %x :a %x :d %x\n", \
4679 description, state->NumInstrs, state->pc, instr, \
4680 address, dest); \
4681 }
4682
4683#define MEM_STORE_LOG(description) if (skyeye_config.log.memlogon >= 1) { \
4684 fprintf(skyeye_logfd, \
4685 "m STORE %s: N %llx :p %x :i %x :a %x :d %x\n", \
4686 description, state->NumInstrs, state->pc, instr, \
4687 address, DEST); \
4688 }
4689
4690 static unsigned 3795 static unsigned
4691 LoadWord (ARMul_State * state, ARMword instr, ARMword address) { 3796 LoadWord (ARMul_State * state, ARMword instr, ARMword address) {
4692 ARMword dest; 3797 ARMword dest;
@@ -4708,8 +3813,6 @@ out:
4708 WRITEDESTB (dest); 3813 WRITEDESTB (dest);
4709 ARMul_Icycles (state, 1, 0L); 3814 ARMul_Icycles (state, 1, 0L);
4710 3815
4711 //MEM_LOAD_LOG("WORD");
4712
4713 return (DESTReg != LHSReg); 3816 return (DESTReg != LHSReg);
4714 } 3817 }
4715 3818
@@ -4739,8 +3842,6 @@ out:
4739 WRITEDEST (dest); 3842 WRITEDEST (dest);
4740 ARMul_Icycles (state, 1, 0L); 3843 ARMul_Icycles (state, 1, 0L);
4741 3844
4742 //MEM_LOAD_LOG("HALFWORD");
4743
4744 return (DESTReg != LHSReg); 3845 return (DESTReg != LHSReg);
4745 } 3846 }
4746 3847
@@ -4770,8 +3871,6 @@ out:
4770 WRITEDEST (dest); 3871 WRITEDEST (dest);
4771 ARMul_Icycles (state, 1, 0L); 3872 ARMul_Icycles (state, 1, 0L);
4772 3873
4773 //MEM_LOAD_LOG("BYTE");
4774
4775 return (DESTReg != LHSReg); 3874 return (DESTReg != LHSReg);
4776 } 3875 }
4777 3876
@@ -4980,8 +4079,6 @@ out:
4980 4079
4981 static unsigned 4080 static unsigned
4982 StoreWord (ARMul_State * state, ARMword instr, ARMword address) { 4081 StoreWord (ARMul_State * state, ARMword instr, ARMword address) {
4983 //MEM_STORE_LOG("WORD");
4984
4985 BUSUSEDINCPCN; 4082 BUSUSEDINCPCN;
4986#ifndef MODE32 4083#ifndef MODE32
4987 if (DESTReg == 15) 4084 if (DESTReg == 15)
@@ -5009,8 +4106,6 @@ out:
5009 4106
5010 static unsigned 4107 static unsigned
5011 StoreHalfWord (ARMul_State * state, ARMword instr, ARMword address) { 4108 StoreHalfWord (ARMul_State * state, ARMword instr, ARMword address) {
5012 //MEM_STORE_LOG("HALFWORD");
5013
5014 BUSUSEDINCPCN; 4109 BUSUSEDINCPCN;
5015 4110
5016#ifndef MODE32 4111#ifndef MODE32
@@ -5041,8 +4136,6 @@ out:
5041 4136
5042 static unsigned 4137 static unsigned
5043 StoreByte (ARMul_State * state, ARMword instr, ARMword address) { 4138 StoreByte (ARMul_State * state, ARMword instr, ARMword address) {
5044 //MEM_STORE_LOG("BYTE");
5045
5046 BUSUSEDINCPCN; 4139 BUSUSEDINCPCN;
5047#ifndef MODE32 4140#ifndef MODE32
5048 if (DESTReg == 15) 4141 if (DESTReg == 15)
HIC SVNT DRACONES