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1/* armdefs.h -- ARMulator common definitions: ARM6 Instruction Emulator.
2 Copyright (C) 1994 Advanced RISC Machines Ltd.
3
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
8
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
17
18#ifndef _ARMDEFS_H_
19#define _ARMDEFS_H_
20
21#include <stdio.h>
22#include <stdlib.h>
23#include <errno.h>
24
25#if EMU_PLATFORM == PLATFORM_WINDOWS
26#include <windows.h>
27#endif
28
29//teawater add for arm2x86 2005.02.14-------------------------------------------
30// koodailar remove it for mingw 2005.12.18----------------
31//anthonylee modify it for portable 2007.01.30
32//#include "portable/mman.h"
33
34#include "arm_regformat.h"
35#include "platform.h"
36#include "skyeye_defs.h"
37
38//AJ2D--------------------------------------------------------------------------
39
40//teawater add for arm2x86 2005.07.03-------------------------------------------
41
42#include <sys/types.h>
43#include <stdio.h>
44#include <stdlib.h>
45#include <string.h>
46#if EMU_PLATFORM == PLATFORM_LINUX
47#include <unistd.h>
48#endif
49#include <errno.h>
50#include <sys/stat.h>
51#include <fcntl.h>
52
53//#include <memory_space.h>
54//AJ2D--------------------------------------------------------------------------
55#if 0
56#if 0
57#define DIFF_STATE 1
58#define __FOLLOW_MODE__ 0
59#else
60#define DIFF_STATE 0
61#define __FOLLOW_MODE__ 1
62#endif
63#endif
64
65#ifndef FALSE
66#define FALSE 0
67#define TRUE 1
68#endif
69
70#define LOW 0
71#define HIGH 1
72#define LOWHIGH 1
73#define HIGHLOW 2
74
75#ifndef u8
76#define u8 unsigned char
77#define u16 unsigned short
78#define u32 unsigned int
79#define u64 unsigned long long
80#endif /*u8 */
81
82//teawater add DBCT_TEST_SPEED 2005.10.04---------------------------------------
83#include <signal.h>
84
85#include "platform.h"
86
87#if EMU_PLATFORM == PLATFORM_LINUX
88#include <sys/time.h>
89#endif
90
91//#define DBCT_TEST_SPEED
92#define DBCT_TEST_SPEED_SEC 10
93//AJ2D--------------------------------------------------------------------------
94
95//teawater add compile switch for DBCT GDB RSP function 2005.10.21--------------
96//#define DBCT_GDBRSP
97//AJ2D--------------------------------------------------------------------------
98
99//#include <skyeye_defs.h>
100//#include <skyeye_types.h>
101
102#define ARM_BYTE_TYPE 0
103#define ARM_HALFWORD_TYPE 1
104#define ARM_WORD_TYPE 2
105
106//the define of cachetype
107#define NONCACHE 0
108#define DATACACHE 1
109#define INSTCACHE 2
110
111#ifndef __STDC__
112typedef char *VoidStar;
113#endif
114
115typedef unsigned long long ARMdword; /* must be 64 bits wide */
116typedef unsigned int ARMword; /* must be 32 bits wide */
117typedef unsigned char ARMbyte; /* must be 8 bits wide */
118typedef unsigned short ARMhword; /* must be 16 bits wide */
119typedef struct ARMul_State ARMul_State;
120typedef struct ARMul_io ARMul_io;
121typedef struct ARMul_Energy ARMul_Energy;
122
123//teawater add for arm2x86 2005.06.24-------------------------------------------
124#include <stdint.h>
125//AJ2D--------------------------------------------------------------------------
126/*
127//chy 2005-05-11
128#ifndef __CYGWIN__
129//teawater add for arm2x86 2005.02.14-------------------------------------------
130typedef unsigned char uint8_t;
131typedef unsigned short uint16_t;
132typedef unsigned int u32;
133#if defined (__x86_64__)
134typedef unsigned long uint64_t;
135#else
136typedef unsigned long long uint64_t;
137#endif
138////AJ2D--------------------------------------------------------------------------
139#endif
140*/
141
142#include "armmmu.h"
143//#include "lcd/skyeye_lcd.h"
144
145
146//#include "skyeye.h"
147//#include "skyeye_device.h"
148//#include "net/skyeye_net.h"
149//#include "skyeye_config.h"
150
151
152typedef unsigned ARMul_CPInits (ARMul_State * state);
153typedef unsigned ARMul_CPExits (ARMul_State * state);
154typedef unsigned ARMul_LDCs (ARMul_State * state, unsigned type,
155 ARMword instr, ARMword value);
156typedef unsigned ARMul_STCs (ARMul_State * state, unsigned type,
157 ARMword instr, ARMword * value);
158typedef unsigned ARMul_MRCs (ARMul_State * state, unsigned type,
159 ARMword instr, ARMword * value);
160typedef unsigned ARMul_MCRs (ARMul_State * state, unsigned type,
161 ARMword instr, ARMword value);
162typedef unsigned ARMul_MRRCs (ARMul_State * state, unsigned type,
163 ARMword instr, ARMword * value1, ARMword * value2);
164typedef unsigned ARMul_MCRRs (ARMul_State * state, unsigned type,
165 ARMword instr, ARMword value1, ARMword value2);
166typedef unsigned ARMul_CDPs (ARMul_State * state, unsigned type,
167 ARMword instr);
168typedef unsigned ARMul_CPReads (ARMul_State * state, unsigned reg,
169 ARMword * value);
170typedef unsigned ARMul_CPWrites (ARMul_State * state, unsigned reg,
171 ARMword value);
172
173
174//added by ksh,2004-3-5
175struct ARMul_io
176{
177 ARMword *instr; //to display the current interrupt state
178 ARMword *net_flag; //to judge if network is enabled
179 ARMword *net_int; //netcard interrupt
180
181 //ywc,2004-04-01
182 ARMword *ts_int;
183 ARMword *ts_is_enable;
184 ARMword *ts_addr_begin;
185 ARMword *ts_addr_end;
186 ARMword *ts_buffer;
187};
188
189/* added by ksh,2004-11-26,some energy profiling */
190struct ARMul_Energy
191{
192 int energy_prof; /* <tktan> BUG200103282109 : for energy profiling */
193 int enable_func_energy; /* <tktan> BUG200105181702 */
194 char *func_energy;
195 int func_display; /* <tktan> BUG200103311509 : for function call display */
196 int func_disp_start; /* <tktan> BUG200104191428 : to start func profiling */
197 char *start_func; /* <tktan> BUG200104191428 */
198
199 FILE *outfile; /* <tktan> BUG200105201531 : direct console to file */
200 long long tcycle, pcycle;
201 float t_energy;
202 void *cur_task; /* <tktan> BUG200103291737 */
203 long long t_mem_cycle, t_idle_cycle, t_uart_cycle;
204 long long p_mem_cycle, p_idle_cycle, p_uart_cycle;
205 long long p_io_update_tcycle;
206 /*record CCCR,to get current core frequency */
207 ARMword cccr;
208};
209#if 0
210#define MAX_BANK 8
211#define MAX_STR 1024
212
213typedef struct mem_bank
214{
215 ARMword (*read_byte) (ARMul_State * state, ARMword addr);
216 void (*write_byte) (ARMul_State * state, ARMword addr, ARMword data);
217 ARMword (*read_halfword) (ARMul_State * state, ARMword addr);
218 void (*write_halfword) (ARMul_State * state, ARMword addr,
219 ARMword data);
220 ARMword (*read_word) (ARMul_State * state, ARMword addr);
221 void (*write_word) (ARMul_State * state, ARMword addr, ARMword data);
222 unsigned int addr, len;
223 char filename[MAX_STR];
224 unsigned type; //chy 2003-09-21: maybe io,ram,rom
225} mem_bank_t;
226typedef struct
227{
228 int bank_num;
229 int current_num; /*current num of bank */
230 mem_bank_t mem_banks[MAX_BANK];
231} mem_config_t;
232#endif
233#define VFP_REG_NUM 64
234struct ARMul_State
235{
236 ARMword Emulate; /* to start and stop emulation */
237 unsigned EndCondition; /* reason for stopping */
238 unsigned ErrorCode; /* type of illegal instruction */
239
240 /* Order of the following register should not be modified */
241 ARMword Reg[16]; /* the current register file */
242 ARMword Cpsr; /* the current psr */
243 ARMword Spsr_copy;
244 ARMword phys_pc;
245 ARMword Reg_usr[2];
246 ARMword Reg_svc[2]; /* R13_SVC R14_SVC */
247 ARMword Reg_abort[2]; /* R13_ABORT R14_ABORT */
248 ARMword Reg_undef[2]; /* R13 UNDEF R14 UNDEF */
249 ARMword Reg_irq[2]; /* R13_IRQ R14_IRQ */
250 ARMword Reg_firq[7]; /* R8---R14 FIRQ */
251 ARMword Spsr[7]; /* the exception psr's */
252 ARMword Mode; /* the current mode */
253 ARMword Bank; /* the current register bank */
254 ARMword exclusive_tag;
255 ARMword exclusive_state;
256 ARMword exclusive_result;
257 ARMword CP15[VFP_BASE - CP15_BASE];
258 ARMword VFP[3]; /* FPSID, FPSCR, and FPEXC */
259 /* VFPv2 and VFPv3-D16 has 16 doubleword registers (D0-D16 or S0-S31).
260 VFPv3-D32/ASIMD may have up to 32 doubleword registers (D0-D31),
261 and only 32 singleword registers are accessible (S0-S31). */
262 ARMword ExtReg[VFP_REG_NUM];
263 /* ---- End of the ordered registers ---- */
264
265 ARMword RegBank[7][16]; /* all the registers */
266 //chy:2003-08-19, used in arm xscale
267 /* 40 bit accumulator. We always keep this 64 bits wide,
268 and move only 40 bits out of it in an MRA insn. */
269 ARMdword Accumulator;
270
271 ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags; /* dummy flags for speed */
272 unsigned long long int icounter, debug_icounter, kernel_icounter;
273 unsigned int shifter_carry_out;
274 //ARMword translate_pc;
275
276 /* add armv6 flags dyf:2010-08-09 */
277 ARMword GEFlag, EFlag, AFlag, QFlags;
278 //chy:2003-08-19, used in arm v5e|xscale
279 ARMword SFlag;
280#ifdef MODET
281 ARMword TFlag; /* Thumb state */
282#endif
283 ARMword instr, pc, temp; /* saved register state */
284 ARMword loaded, decoded; /* saved pipeline state */
285 //chy 2006-04-12 for ICE breakpoint
286 ARMword loaded_addr, decoded_addr; /* saved pipeline state addr*/
287 unsigned int NumScycles, NumNcycles, NumIcycles, NumCcycles, NumFcycles; /* emulated cycles used */
288 unsigned long long NumInstrs; /* the number of instructions executed */
289 unsigned NextInstr;
290 unsigned VectorCatch; /* caught exception mask */
291 unsigned CallDebug; /* set to call the debugger */
292 unsigned CanWatch; /* set by memory interface if its willing to suffer the
293 overhead of checking for watchpoints on each memory
294 access */
295 unsigned int StopHandle;
296
297 char *CommandLine; /* Command Line from ARMsd */
298
299 ARMul_CPInits *CPInit[16]; /* coprocessor initialisers */
300 ARMul_CPExits *CPExit[16]; /* coprocessor finalisers */
301 ARMul_LDCs *LDC[16]; /* LDC instruction */
302 ARMul_STCs *STC[16]; /* STC instruction */
303 ARMul_MRCs *MRC[16]; /* MRC instruction */
304 ARMul_MCRs *MCR[16]; /* MCR instruction */
305 ARMul_MRRCs *MRRC[16]; /* MRRC instruction */
306 ARMul_MCRRs *MCRR[16]; /* MCRR instruction */
307 ARMul_CDPs *CDP[16]; /* CDP instruction */
308 ARMul_CPReads *CPRead[16]; /* Read CP register */
309 ARMul_CPWrites *CPWrite[16]; /* Write CP register */
310 unsigned char *CPData[16]; /* Coprocessor data */
311 unsigned char const *CPRegWords[16]; /* map of coprocessor register sizes */
312
313 unsigned EventSet; /* the number of events in the queue */
314 unsigned int Now; /* time to the nearest cycle */
315 struct EventNode **EventPtr; /* the event list */
316
317 unsigned Debug; /* show instructions as they are executed */
318 unsigned NresetSig; /* reset the processor */
319 unsigned NfiqSig;
320 unsigned NirqSig;
321
322 unsigned abortSig;
323 unsigned NtransSig;
324 unsigned bigendSig;
325 unsigned prog32Sig;
326 unsigned data32Sig;
327 unsigned syscallSig;
328
329/* 2004-05-09 chy
330----------------------------------------------------------
331read ARM Architecture Reference Manual
3322.6.5 Data Abort
333There are three Abort Model in ARM arch.
334
335Early Abort Model: used in some ARMv3 and earlier implementations. In this
336model, base register wirteback occurred for LDC,LDM,STC,STM instructions, and
337the base register was unchanged for all other instructions. (oldest)
338
339Base Restored Abort Model: If a Data Abort occurs in an instruction which
340specifies base register writeback, the value in the base register is
341unchanged. (strongarm, xscale)
342
343Base Updated Abort Model: If a Data Abort occurs in an instruction which
344specifies base register writeback, the base register writeback still occurs.
345(arm720T)
346
347read PART B
348chap2 The System Control Coprocessor CP15
3492.4 Register1:control register
350L(bit 6): in some ARMv3 and earlier implementations, the abort model of the
351processor could be configured:
3520=early Abort Model Selected(now obsolete)
3531=Late Abort Model selceted(same as Base Updated Abort Model)
354
355on later processors, this bit reads as 1 and ignores writes.
356-------------------------------------------------------------
357So, if lateabtSig=1, then it means Late Abort Model(Base Updated Abort Model)
358 if lateabtSig=0, then it means Base Restored Abort Model
359*/
360 unsigned lateabtSig;
361
362 ARMword Vector; /* synthesize aborts in cycle modes */
363 ARMword Aborted; /* sticky flag for aborts */
364 ARMword Reseted; /* sticky flag for Reset */
365 ARMword Inted, LastInted; /* sticky flags for interrupts */
366 ARMword Base; /* extra hand for base writeback */
367 ARMword AbortAddr; /* to keep track of Prefetch aborts */
368
369 const struct Dbg_HostosInterface *hostif;
370
371 int verbose; /* non-zero means print various messages like the banner */
372
373 mmu_state_t mmu;
374 int mmu_inited;
375 //mem_state_t mem;
376 /*remove io_state to skyeye_mach_*.c files */
377 //io_state_t io;
378 /* point to a interrupt pending register. now for skyeye-ne2k.c
379 * later should move somewhere. e.g machine_config_t*/
380
381
382 //chy: 2003-08-11, for different arm core type
383 unsigned is_v4; /* Are we emulating a v4 architecture (or higher) ? */
384 unsigned is_v5; /* Are we emulating a v5 architecture ? */
385 unsigned is_v5e; /* Are we emulating a v5e architecture ? */
386 unsigned is_v6; /* Are we emulating a v6 architecture ? */
387 unsigned is_v7; /* Are we emulating a v7 architecture ? */
388 unsigned is_XScale; /* Are we emulating an XScale architecture ? */
389 unsigned is_iWMMXt; /* Are we emulating an iWMMXt co-processor ? */
390 unsigned is_ep9312; /* Are we emulating a Cirrus Maverick co-processor ? */
391 //chy 2005-09-19
392 unsigned is_pxa27x; /* Are we emulating a Intel PXA27x co-processor ? */
393 //chy: seems only used in xscale's CP14
394 unsigned int LastTime; /* Value of last call to ARMul_Time() */
395 ARMword CP14R0_CCD; /* used to count 64 clock cycles with CP14 R0 bit 3 set */
396
397
398//added by ksh:for handle different machs io 2004-3-5
399 ARMul_io mach_io;
400
401/*added by ksh,2004-11-26,some energy profiling*/
402 ARMul_Energy energy;
403
404//teawater add for next_dis 2004.10.27-----------------------
405 int disassemble;
406//AJ2D------------------------------------------
407
408//teawater add for arm2x86 2005.02.15-------------------------------------------
409 u32 trap;
410 u32 tea_break_addr;
411 u32 tea_break_ok;
412 int tea_pc;
413//AJ2D--------------------------------------------------------------------------
414//teawater add for arm2x86 2005.07.03-------------------------------------------
415
416 /*
417 * 2007-01-24 removed the term-io functions by Anthony Lee,
418 * moved to "device/uart/skyeye_uart_stdio.c".
419 */
420
421//AJ2D--------------------------------------------------------------------------
422//teawater add for arm2x86 2005.07.05-------------------------------------------
423 //arm_arm A2-18
424 int abort_model; //0 Base Restored Abort Model, 1 the Early Abort Model, 2 Base Updated Abort Model
425//AJ2D--------------------------------------------------------------------------
426//teawater change for return if running tb dirty 2005.07.09---------------------
427 void *tb_now;
428//AJ2D--------------------------------------------------------------------------
429
430//teawater add for record reg value to ./reg.txt 2005.07.10---------------------
431 FILE *tea_reg_fd;
432//AJ2D--------------------------------------------------------------------------
433
434/*added by ksh in 2005-10-1*/
435 cpu_config_t *cpu;
436 //mem_config_t *mem_bank;
437
438/* added LPC remap function */
439 int vector_remap_flag;
440 u32 vector_remap_addr;
441 u32 vector_remap_size;
442
443 u32 step;
444 u32 cycle;
445 int stop_simulator;
446 conf_object_t *dyncom_cpu;
447//teawater add DBCT_TEST_SPEED 2005.10.04---------------------------------------
448#ifdef DBCT_TEST_SPEED
449 uint64_t instr_count;
450#endif //DBCT_TEST_SPEED
451// FILE * state_log;
452//diff log
453//#if DIFF_STATE
454 FILE * state_log;
455//#endif
456 /* monitored memory for exclusice access */
457 ARMword exclusive_tag_array[128];
458 /* 1 means exclusive access and 0 means open access */
459 ARMword exclusive_access_state;
460
461 memory_space_intf space;
462 u32 CurrInstr;
463 u32 last_pc; /* the last pc executed */
464 u32 last_instr; /* the last inst executed */
465 u32 WriteAddr[17];
466 u32 WriteData[17];
467 u32 WritePc[17];
468 u32 CurrWrite;
469};
470#define DIFF_WRITE 0
471
472typedef ARMul_State arm_core_t;
473#define ResetPin NresetSig
474#define FIQPin NfiqSig
475#define IRQPin NirqSig
476#define AbortPin abortSig
477#define TransPin NtransSig
478#define BigEndPin bigendSig
479#define Prog32Pin prog32Sig
480#define Data32Pin data32Sig
481#define LateAbortPin lateabtSig
482
483/***************************************************************************\
484* Types of ARM we know about *
485\***************************************************************************/
486
487/* The bitflags */
488#define ARM_Fix26_Prop 0x01
489#define ARM_Nexec_Prop 0x02
490#define ARM_Debug_Prop 0x10
491#define ARM_Isync_Prop ARM_Debug_Prop
492#define ARM_Lock_Prop 0x20
493//chy 2003-08-11
494#define ARM_v4_Prop 0x40
495#define ARM_v5_Prop 0x80
496/*jeff.du 2010-08-05 */
497#define ARM_v6_Prop 0xc0
498
499#define ARM_v5e_Prop 0x100
500#define ARM_XScale_Prop 0x200
501#define ARM_ep9312_Prop 0x400
502#define ARM_iWMMXt_Prop 0x800
503//chy 2005-09-19
504#define ARM_PXA27X_Prop 0x1000
505#define ARM_v7_Prop 0x2000
506
507/* ARM2 family */
508#define ARM2 (ARM_Fix26_Prop)
509#define ARM2as ARM2
510#define ARM61 ARM2
511#define ARM3 ARM2
512
513#ifdef ARM60 /* previous definition in armopts.h */
514#undef ARM60
515#endif
516
517/* ARM6 family */
518#define ARM6 (ARM_Lock_Prop)
519#define ARM60 ARM6
520#define ARM600 ARM6
521#define ARM610 ARM6
522#define ARM620 ARM6
523
524
525/***************************************************************************\
526* Macros to extract instruction fields *
527\***************************************************************************/
528
529#define BIT(n) ( (ARMword)(instr>>(n))&1) /* bit n of instruction */
530#define BITS(m,n) ( (ARMword)(instr<<(31-(n))) >> ((31-(n))+(m)) ) /* bits m to n of instr */
531#define TOPBITS(n) (instr >> (n)) /* bits 31 to n of instr */
532
533/***************************************************************************\
534* The hardware vector addresses *
535\***************************************************************************/
536
537#define ARMResetV 0L
538#define ARMUndefinedInstrV 4L
539#define ARMSWIV 8L
540#define ARMPrefetchAbortV 12L
541#define ARMDataAbortV 16L
542#define ARMAddrExceptnV 20L
543#define ARMIRQV 24L
544#define ARMFIQV 28L
545#define ARMErrorV 32L /* This is an offset, not an address ! */
546
547#define ARMul_ResetV ARMResetV
548#define ARMul_UndefinedInstrV ARMUndefinedInstrV
549#define ARMul_SWIV ARMSWIV
550#define ARMul_PrefetchAbortV ARMPrefetchAbortV
551#define ARMul_DataAbortV ARMDataAbortV
552#define ARMul_AddrExceptnV ARMAddrExceptnV
553#define ARMul_IRQV ARMIRQV
554#define ARMul_FIQV ARMFIQV
555
556/***************************************************************************\
557* Mode and Bank Constants *
558\***************************************************************************/
559
560#define USER26MODE 0L
561#define FIQ26MODE 1L
562#define IRQ26MODE 2L
563#define SVC26MODE 3L
564#define USER32MODE 16L
565#define FIQ32MODE 17L
566#define IRQ32MODE 18L
567#define SVC32MODE 19L
568#define ABORT32MODE 23L
569#define UNDEF32MODE 27L
570//chy 2006-02-15 add system32 mode
571#define SYSTEM32MODE 31L
572
573#define ARM32BITMODE (state->Mode > 3)
574#define ARM26BITMODE (state->Mode <= 3)
575#define ARMMODE (state->Mode)
576#define ARMul_MODEBITS 0x1fL
577#define ARMul_MODE32BIT ARM32BITMODE
578#define ARMul_MODE26BIT ARM26BITMODE
579
580#define USERBANK 0
581#define FIQBANK 1
582#define IRQBANK 2
583#define SVCBANK 3
584#define ABORTBANK 4
585#define UNDEFBANK 5
586#define DUMMYBANK 6
587#define SYSTEMBANK USERBANK
588#define BANK_CAN_ACCESS_SPSR(bank) \
589 ((bank) != USERBANK && (bank) != SYSTEMBANK && (bank) != DUMMYBANK)
590
591
592/***************************************************************************\
593* Definitons of things in the emulator *
594\***************************************************************************/
595#ifdef __cplusplus
596extern "C" {
597#endif
598extern void ARMul_EmulateInit (void);
599extern void ARMul_Reset (ARMul_State * state);
600#ifdef __cplusplus
601 }
602#endif
603extern ARMul_State *ARMul_NewState (ARMul_State * state);
604extern ARMword ARMul_DoProg (ARMul_State * state);
605extern ARMword ARMul_DoInstr (ARMul_State * state);
606/***************************************************************************\
607* Definitons of things for event handling *
608\***************************************************************************/
609
610extern void ARMul_ScheduleEvent (ARMul_State * state, unsigned int delay,
611 unsigned (*func) ());
612extern void ARMul_EnvokeEvent (ARMul_State * state);
613extern unsigned int ARMul_Time (ARMul_State * state);
614
615/***************************************************************************\
616* Useful support routines *
617\***************************************************************************/
618
619extern ARMword ARMul_GetReg (ARMul_State * state, unsigned mode,
620 unsigned reg);
621extern void ARMul_SetReg (ARMul_State * state, unsigned mode, unsigned reg,
622 ARMword value);
623extern ARMword ARMul_GetPC (ARMul_State * state);
624extern ARMword ARMul_GetNextPC (ARMul_State * state);
625extern void ARMul_SetPC (ARMul_State * state, ARMword value);
626extern ARMword ARMul_GetR15 (ARMul_State * state);
627extern void ARMul_SetR15 (ARMul_State * state, ARMword value);
628
629extern ARMword ARMul_GetCPSR (ARMul_State * state);
630extern void ARMul_SetCPSR (ARMul_State * state, ARMword value);
631extern ARMword ARMul_GetSPSR (ARMul_State * state, ARMword mode);
632extern void ARMul_SetSPSR (ARMul_State * state, ARMword mode, ARMword value);
633
634/***************************************************************************\
635* Definitons of things to handle aborts *
636\***************************************************************************/
637
638extern void ARMul_Abort (ARMul_State * state, ARMword address);
639#ifdef MODET
640#define ARMul_ABORTWORD (state->TFlag ? 0xefffdfff : 0xefffffff) /* SWI -1 */
641#define ARMul_PREFETCHABORT(address) if (state->AbortAddr == 1) \
642 state->AbortAddr = (address & (state->TFlag ? ~1L : ~3L))
643#else
644#define ARMul_ABORTWORD 0xefffffff /* SWI -1 */
645#define ARMul_PREFETCHABORT(address) if (state->AbortAddr == 1) \
646 state->AbortAddr = (address & ~3L)
647#endif
648#define ARMul_DATAABORT(address) state->abortSig = HIGH ; \
649 state->Aborted = ARMul_DataAbortV ;
650#define ARMul_CLEARABORT state->abortSig = LOW
651
652/***************************************************************************\
653* Definitons of things in the memory interface *
654\***************************************************************************/
655
656extern unsigned ARMul_MemoryInit (ARMul_State * state,
657 unsigned int initmemsize);
658extern void ARMul_MemoryExit (ARMul_State * state);
659
660extern ARMword ARMul_LoadInstrS (ARMul_State * state, ARMword address,
661 ARMword isize);
662extern ARMword ARMul_LoadInstrN (ARMul_State * state, ARMword address,
663 ARMword isize);
664#ifdef __cplusplus
665extern "C" {
666#endif
667extern ARMword ARMul_ReLoadInstr (ARMul_State * state, ARMword address,
668 ARMword isize);
669#ifdef __cplusplus
670 }
671#endif
672extern ARMword ARMul_LoadWordS (ARMul_State * state, ARMword address);
673extern ARMword ARMul_LoadWordN (ARMul_State * state, ARMword address);
674extern ARMword ARMul_LoadHalfWord (ARMul_State * state, ARMword address);
675extern ARMword ARMul_LoadByte (ARMul_State * state, ARMword address);
676
677extern void ARMul_StoreWordS (ARMul_State * state, ARMword address,
678 ARMword data);
679extern void ARMul_StoreWordN (ARMul_State * state, ARMword address,
680 ARMword data);
681extern void ARMul_StoreHalfWord (ARMul_State * state, ARMword address,
682 ARMword data);
683extern void ARMul_StoreByte (ARMul_State * state, ARMword address,
684 ARMword data);
685
686extern ARMword ARMul_SwapWord (ARMul_State * state, ARMword address,
687 ARMword data);
688extern ARMword ARMul_SwapByte (ARMul_State * state, ARMword address,
689 ARMword data);
690
691extern void ARMul_Icycles (ARMul_State * state, unsigned number,
692 ARMword address);
693extern void ARMul_Ccycles (ARMul_State * state, unsigned number,
694 ARMword address);
695
696extern ARMword ARMul_ReadWord (ARMul_State * state, ARMword address);
697extern ARMword ARMul_ReadByte (ARMul_State * state, ARMword address);
698extern void ARMul_WriteWord (ARMul_State * state, ARMword address,
699 ARMword data);
700extern void ARMul_WriteByte (ARMul_State * state, ARMword address,
701 ARMword data);
702
703extern ARMword ARMul_MemAccess (ARMul_State * state, ARMword, ARMword,
704 ARMword, ARMword, ARMword, ARMword, ARMword,
705 ARMword, ARMword, ARMword);
706
707/***************************************************************************\
708* Definitons of things in the co-processor interface *
709\***************************************************************************/
710
711#define ARMul_FIRST 0
712#define ARMul_TRANSFER 1
713#define ARMul_BUSY 2
714#define ARMul_DATA 3
715#define ARMul_INTERRUPT 4
716#define ARMul_DONE 0
717#define ARMul_CANT 1
718#define ARMul_INC 3
719
720#define ARMul_CP13_R0_FIQ 0x1
721#define ARMul_CP13_R0_IRQ 0x2
722#define ARMul_CP13_R8_PMUS 0x1
723
724#define ARMul_CP14_R0_ENABLE 0x0001
725#define ARMul_CP14_R0_CLKRST 0x0004
726#define ARMul_CP14_R0_CCD 0x0008
727#define ARMul_CP14_R0_INTEN0 0x0010
728#define ARMul_CP14_R0_INTEN1 0x0020
729#define ARMul_CP14_R0_INTEN2 0x0040
730#define ARMul_CP14_R0_FLAG0 0x0100
731#define ARMul_CP14_R0_FLAG1 0x0200
732#define ARMul_CP14_R0_FLAG2 0x0400
733#define ARMul_CP14_R10_MOE_IB 0x0004
734#define ARMul_CP14_R10_MOE_DB 0x0008
735#define ARMul_CP14_R10_MOE_BT 0x000c
736#define ARMul_CP15_R1_ENDIAN 0x0080
737#define ARMul_CP15_R1_ALIGN 0x0002
738#define ARMul_CP15_R5_X 0x0400
739#define ARMul_CP15_R5_ST_ALIGN 0x0001
740#define ARMul_CP15_R5_IMPRE 0x0406
741#define ARMul_CP15_R5_MMU_EXCPT 0x0400
742#define ARMul_CP15_DBCON_M 0x0100
743#define ARMul_CP15_DBCON_E1 0x000c
744#define ARMul_CP15_DBCON_E0 0x0003
745
746extern unsigned ARMul_CoProInit (ARMul_State * state);
747extern void ARMul_CoProExit (ARMul_State * state);
748extern void ARMul_CoProAttach (ARMul_State * state, unsigned number,
749 ARMul_CPInits * init, ARMul_CPExits * exit,
750 ARMul_LDCs * ldc, ARMul_STCs * stc,
751 ARMul_MRCs * mrc, ARMul_MCRs * mcr,
752 ARMul_MRRCs * mrrc, ARMul_MCRRs * mcrr,
753 ARMul_CDPs * cdp,
754 ARMul_CPReads * read, ARMul_CPWrites * write);
755extern void ARMul_CoProDetach (ARMul_State * state, unsigned number);
756
757/***************************************************************************\
758* Definitons of things in the host environment *
759\***************************************************************************/
760
761extern unsigned ARMul_OSInit (ARMul_State * state);
762extern void ARMul_OSExit (ARMul_State * state);
763
764#ifdef __cplusplus
765 extern "C" {
766#endif
767
768extern unsigned ARMul_OSHandleSWI (ARMul_State * state, ARMword number);
769#ifdef __cplusplus
770}
771#endif
772
773
774extern ARMword ARMul_OSLastErrorP (ARMul_State * state);
775
776extern ARMword ARMul_Debug (ARMul_State * state, ARMword pc, ARMword instr);
777extern unsigned ARMul_OSException (ARMul_State * state, ARMword vector,
778 ARMword pc);
779extern int rdi_log;
780
781/***************************************************************************\
782* Host-dependent stuff *
783\***************************************************************************/
784
785#ifdef macintosh
786pascal void SpinCursor (short increment); /* copied from CursorCtl.h */
787# define HOURGLASS SpinCursor( 1 )
788# define HOURGLASS_RATE 1023 /* 2^n - 1 */
789#endif
790
791//teawater add for arm2x86 2005.02.14-------------------------------------------
792/*ywc 2005-03-31*/
793/*
794#include "arm2x86.h"
795#include "arm2x86_dp.h"
796#include "arm2x86_movl.h"
797#include "arm2x86_psr.h"
798#include "arm2x86_shift.h"
799#include "arm2x86_mem.h"
800#include "arm2x86_mul.h"
801#include "arm2x86_test.h"
802#include "arm2x86_other.h"
803#include "list.h"
804#include "tb.h"
805*/
806#define EQ 0
807#define NE 1
808#define CS 2
809#define CC 3
810#define MI 4
811#define PL 5
812#define VS 6
813#define VC 7
814#define HI 8
815#define LS 9
816#define GE 10
817#define LT 11
818#define GT 12
819#define LE 13
820#define AL 14
821#define NV 15
822
823#ifndef NFLAG
824#define NFLAG state->NFlag
825#endif //NFLAG
826
827#ifndef ZFLAG
828#define ZFLAG state->ZFlag
829#endif //ZFLAG
830
831#ifndef CFLAG
832#define CFLAG state->CFlag
833#endif //CFLAG
834
835#ifndef VFLAG
836#define VFLAG state->VFlag
837#endif //VFLAG
838
839#ifndef IFLAG
840#define IFLAG (state->IFFlags >> 1)
841#endif //IFLAG
842
843#ifndef FFLAG
844#define FFLAG (state->IFFlags & 1)
845#endif //FFLAG
846
847#ifndef IFFLAGS
848#define IFFLAGS state->IFFlags
849#endif //VFLAG
850
851#define FLAG_MASK 0xf0000000
852#define NBIT_SHIFT 31
853#define ZBIT_SHIFT 30
854#define CBIT_SHIFT 29
855#define VBIT_SHIFT 28
856#ifdef DBCT
857//teawater change for local tb branch directly jump 2005.10.18------------------
858#include "dbct/list.h"
859#include "dbct/arm2x86.h"
860#include "dbct/arm2x86_dp.h"
861#include "dbct/arm2x86_movl.h"
862#include "dbct/arm2x86_psr.h"
863#include "dbct/arm2x86_shift.h"
864#include "dbct/arm2x86_mem.h"
865#include "dbct/arm2x86_mul.h"
866#include "dbct/arm2x86_test.h"
867#include "dbct/arm2x86_other.h"
868#include "dbct/arm2x86_coproc.h"
869#include "dbct/tb.h"
870#endif
871//AJ2D--------------------------------------------------------------------------
872//AJ2D--------------------------------------------------------------------------
873#define SKYEYE_OUTREGS(fd) { fprintf ((fd), "R %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,C %x,S %x,%x,%x,%x,%x,%x,%x,M %x,B %x,E %x,I %x,P %x,T %x,L %x,D %x,",\
874 state->Reg[0],state->Reg[1],state->Reg[2],state->Reg[3], \
875 state->Reg[4],state->Reg[5],state->Reg[6],state->Reg[7], \
876 state->Reg[8],state->Reg[9],state->Reg[10],state->Reg[11], \
877 state->Reg[12],state->Reg[13],state->Reg[14],state->Reg[15], \
878 state->Cpsr, state->Spsr[0], state->Spsr[1], state->Spsr[2],\
879 state->Spsr[3],state->Spsr[4], state->Spsr[5], state->Spsr[6],\
880 state->Mode,state->Bank,state->ErrorCode,state->instr,state->pc,\
881 state->temp,state->loaded,state->decoded);}
882
883#define SKYEYE_OUTMOREREGS(fd) { fprintf ((fd),"\
884RUs %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,\
885RF %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,\
886RI %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,\
887RS %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,\
888RA %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,\
889RUn %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x\n",\
890 state->RegBank[0][0],state->RegBank[0][1],state->RegBank[0][2],state->RegBank[0][3], \
891 state->RegBank[0][4],state->RegBank[0][5],state->RegBank[0][6],state->RegBank[0][7], \
892 state->RegBank[0][8],state->RegBank[0][9],state->RegBank[0][10],state->RegBank[0][11], \
893 state->RegBank[0][12],state->RegBank[0][13],state->RegBank[0][14],state->RegBank[0][15], \
894 state->RegBank[1][0],state->RegBank[1][1],state->RegBank[1][2],state->RegBank[1][3], \
895 state->RegBank[1][4],state->RegBank[1][5],state->RegBank[1][6],state->RegBank[1][7], \
896 state->RegBank[1][8],state->RegBank[1][9],state->RegBank[1][10],state->RegBank[1][11], \
897 state->RegBank[1][12],state->RegBank[1][13],state->RegBank[1][14],state->RegBank[1][15], \
898 state->RegBank[2][0],state->RegBank[2][1],state->RegBank[2][2],state->RegBank[2][3], \
899 state->RegBank[2][4],state->RegBank[2][5],state->RegBank[2][6],state->RegBank[2][7], \
900 state->RegBank[2][8],state->RegBank[2][9],state->RegBank[2][10],state->RegBank[2][11], \
901 state->RegBank[2][12],state->RegBank[2][13],state->RegBank[2][14],state->RegBank[2][15], \
902 state->RegBank[3][0],state->RegBank[3][1],state->RegBank[3][2],state->RegBank[3][3], \
903 state->RegBank[3][4],state->RegBank[3][5],state->RegBank[3][6],state->RegBank[3][7], \
904 state->RegBank[3][8],state->RegBank[3][9],state->RegBank[3][10],state->RegBank[3][11], \
905 state->RegBank[3][12],state->RegBank[3][13],state->RegBank[3][14],state->RegBank[3][15], \
906 state->RegBank[4][0],state->RegBank[4][1],state->RegBank[4][2],state->RegBank[4][3], \
907 state->RegBank[4][4],state->RegBank[4][5],state->RegBank[4][6],state->RegBank[4][7], \
908 state->RegBank[4][8],state->RegBank[4][9],state->RegBank[4][10],state->RegBank[4][11], \
909 state->RegBank[4][12],state->RegBank[4][13],state->RegBank[4][14],state->RegBank[4][15], \
910 state->RegBank[5][0],state->RegBank[5][1],state->RegBank[5][2],state->RegBank[5][3], \
911 state->RegBank[5][4],state->RegBank[5][5],state->RegBank[5][6],state->RegBank[5][7], \
912 state->RegBank[5][8],state->RegBank[5][9],state->RegBank[5][10],state->RegBank[5][11], \
913 state->RegBank[5][12],state->RegBank[5][13],state->RegBank[5][14],state->RegBank[5][15] \
914 );}
915
916
917#define SA1110 0x6901b110
918#define SA1100 0x4401a100
919#define PXA250 0x69052100
920#define PXA270 0x69054110
921//#define PXA250 0x69052903
922// 0x69052903; //PXA250 B1 from intel 278522-001.pdf
923
924
925extern void ARMul_UndefInstr (ARMul_State *, ARMword);
926extern void ARMul_FixCPSR (ARMul_State *, ARMword, ARMword);
927extern void ARMul_FixSPSR (ARMul_State *, ARMword, ARMword);
928extern void ARMul_ConsolePrint (ARMul_State *, const char *, ...);
929extern void ARMul_SelectProcessor (ARMul_State *, unsigned);
930
931#define DIFF_LOG 0
932#define SAVE_LOG 0
933
934#endif /* _ARMDEFS_H_ */
HIC SVNT DRACONES