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-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index b0efd7194..b8fbe7f3a 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -3700,7 +3700,6 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
3700 #define OPCODE_1 inst_cream->opcode_1 3700 #define OPCODE_1 inst_cream->opcode_1
3701 #define OPCODE_2 inst_cream->opcode_2 3701 #define OPCODE_2 inst_cream->opcode_2
3702 #define CRm inst_cream->crm 3702 #define CRm inst_cream->crm
3703 #define CP15_REG(n) cpu->CP15[CP15(n)]
3704 #define RD cpu->Reg[inst_cream->Rd] 3703 #define RD cpu->Reg[inst_cream->Rd]
3705 #define RD2 cpu->Reg[inst_cream->Rd + 1] 3704 #define RD2 cpu->Reg[inst_cream->Rd + 1]
3706 #define RN cpu->Reg[inst_cream->Rn] 3705 #define RN cpu->Reg[inst_cream->Rn]