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-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp40
1 files changed, 31 insertions, 9 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index fbd6f94f9..96c88c83a 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -23,6 +23,8 @@
23#include "core/arm/skyeye_common/armsupp.h" 23#include "core/arm/skyeye_common/armsupp.h"
24#include "core/arm/skyeye_common/vfp/vfp.h" 24#include "core/arm/skyeye_common/vfp/vfp.h"
25 25
26#include "core/gdbstub/gdbstub.h"
27
26Common::Profiling::TimingCategory profile_execute("DynCom::Execute"); 28Common::Profiling::TimingCategory profile_execute("DynCom::Execute");
27Common::Profiling::TimingCategory profile_decode("DynCom::Decode"); 29Common::Profiling::TimingCategory profile_decode("DynCom::Decode");
28 30
@@ -3548,6 +3550,7 @@ static int InterpreterTranslate(ARMul_State* cpu, int& bb_start, u32 addr) {
3548 CITRA_IGNORE_EXIT(-1); 3550 CITRA_IGNORE_EXIT(-1);
3549 } 3551 }
3550 inst_base = arm_instruction_trans[idx](inst, idx); 3552 inst_base = arm_instruction_trans[idx](inst, idx);
3553
3551translated: 3554translated:
3552 phys_addr += inst_size; 3555 phys_addr += inst_size;
3553 3556
@@ -3580,6 +3583,8 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
3580 Common::Profiling::ScopeTimer timer_execute(profile_execute); 3583 Common::Profiling::ScopeTimer timer_execute(profile_execute);
3581 MICROPROFILE_SCOPE(DynCom_Execute); 3584 MICROPROFILE_SCOPE(DynCom_Execute);
3582 3585
3586 GDBStub::BreakpointAddress breakpoint_data;
3587
3583 #undef RM 3588 #undef RM
3584 #undef RS 3589 #undef RS
3585 3590
@@ -3604,15 +3609,27 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
3604 #define INC_PC(l) ptr += sizeof(arm_inst) + l 3609 #define INC_PC(l) ptr += sizeof(arm_inst) + l
3605 #define INC_PC_STUB ptr += sizeof(arm_inst) 3610 #define INC_PC_STUB ptr += sizeof(arm_inst)
3606 3611
3612#define GDB_BP_CHECK \
3613 cpu->Cpsr &= ~(1 << 5); \
3614 cpu->Cpsr |= cpu->TFlag << 5; \
3615 if (GDBStub::g_server_enabled) { \
3616 if (GDBStub::IsMemoryBreak() || (breakpoint_data.type != GDBStub::BreakpointType::None && PC == breakpoint_data.address)) { \
3617 GDBStub::Break(); \
3618 goto END; \
3619 } \
3620 }
3621
3607// GCC and Clang have a C++ extension to support a lookup table of labels. Otherwise, fallback to a 3622// GCC and Clang have a C++ extension to support a lookup table of labels. Otherwise, fallback to a
3608// clunky switch statement. 3623// clunky switch statement.
3609#if defined __GNUC__ || defined __clang__ 3624#if defined __GNUC__ || defined __clang__
3610#define GOTO_NEXT_INST \ 3625#define GOTO_NEXT_INST \
3626 GDB_BP_CHECK; \
3611 if (num_instrs >= cpu->NumInstrsToExecute) goto END; \ 3627 if (num_instrs >= cpu->NumInstrsToExecute) goto END; \
3612 num_instrs++; \ 3628 num_instrs++; \
3613 goto *InstLabel[inst_base->idx] 3629 goto *InstLabel[inst_base->idx]
3614#else 3630#else
3615#define GOTO_NEXT_INST \ 3631#define GOTO_NEXT_INST \
3632 GDB_BP_CHECK; \
3616 if (num_instrs >= cpu->NumInstrsToExecute) goto END; \ 3633 if (num_instrs >= cpu->NumInstrsToExecute) goto END; \
3617 num_instrs++; \ 3634 num_instrs++; \
3618 switch(inst_base->idx) { \ 3635 switch(inst_base->idx) { \
@@ -3903,6 +3920,11 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
3903 goto END; 3920 goto END;
3904 } 3921 }
3905 3922
3923 // Find breakpoint if one exists within the block
3924 if (GDBStub::g_server_enabled && GDBStub::IsConnected()) {
3925 breakpoint_data = GDBStub::GetNextBreakpointFromAddress(cpu->Reg[15], GDBStub::BreakpointType::Execute);
3926 }
3927
3906 inst_base = (arm_inst *)&inst_buf[ptr]; 3928 inst_base = (arm_inst *)&inst_buf[ptr];
3907 GOTO_NEXT_INST; 3929 GOTO_NEXT_INST;
3908 } 3930 }
@@ -4454,7 +4476,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
4454 ldst_inst* inst_cream = (ldst_inst*)inst_base->component; 4476 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
4455 inst_cream->get_addr(cpu, inst_cream->inst, addr); 4477 inst_cream->get_addr(cpu, inst_cream->inst, addr);
4456 4478
4457 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = Memory::Read8(addr); 4479 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = cpu->ReadMemory8(addr);
4458 4480
4459 if (BITS(inst_cream->inst, 12, 15) == 15) { 4481 if (BITS(inst_cream->inst, 12, 15) == 15) {
4460 INC_PC(sizeof(ldst_inst)); 4482 INC_PC(sizeof(ldst_inst));
@@ -4472,7 +4494,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
4472 ldst_inst* inst_cream = (ldst_inst*)inst_base->component; 4494 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
4473 inst_cream->get_addr(cpu, inst_cream->inst, addr); 4495 inst_cream->get_addr(cpu, inst_cream->inst, addr);
4474 4496
4475 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = Memory::Read8(addr); 4497 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = cpu->ReadMemory8(addr);
4476 4498
4477 if (BITS(inst_cream->inst, 12, 15) == 15) { 4499 if (BITS(inst_cream->inst, 12, 15) == 15) {
4478 INC_PC(sizeof(ldst_inst)); 4500 INC_PC(sizeof(ldst_inst));
@@ -4531,7 +4553,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
4531 4553
4532 cpu->SetExclusiveMemoryAddress(read_addr); 4554 cpu->SetExclusiveMemoryAddress(read_addr);
4533 4555
4534 RD = Memory::Read8(read_addr); 4556 RD = cpu->ReadMemory8(read_addr);
4535 if (inst_cream->Rd == 15) { 4557 if (inst_cream->Rd == 15) {
4536 INC_PC(sizeof(generic_arm_inst)); 4558 INC_PC(sizeof(generic_arm_inst));
4537 goto DISPATCH; 4559 goto DISPATCH;
@@ -4604,7 +4626,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
4604 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 4626 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
4605 ldst_inst* inst_cream = (ldst_inst*)inst_base->component; 4627 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
4606 inst_cream->get_addr(cpu, inst_cream->inst, addr); 4628 inst_cream->get_addr(cpu, inst_cream->inst, addr);
4607 unsigned int value = Memory::Read8(addr); 4629 unsigned int value = cpu->ReadMemory8(addr);
4608 if (BIT(value, 7)) { 4630 if (BIT(value, 7)) {
4609 value |= 0xffffff00; 4631 value |= 0xffffff00;
4610 } 4632 }
@@ -6027,7 +6049,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
6027 ldst_inst* inst_cream = (ldst_inst*)inst_base->component; 6049 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
6028 inst_cream->get_addr(cpu, inst_cream->inst, addr); 6050 inst_cream->get_addr(cpu, inst_cream->inst, addr);
6029 unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xff; 6051 unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xff;
6030 Memory::Write8(addr, value); 6052 cpu->WriteMemory8(addr, value);
6031 } 6053 }
6032 cpu->Reg[15] += cpu->GetInstructionSize(); 6054 cpu->Reg[15] += cpu->GetInstructionSize();
6033 INC_PC(sizeof(ldst_inst)); 6055 INC_PC(sizeof(ldst_inst));
@@ -6040,7 +6062,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
6040 ldst_inst* inst_cream = (ldst_inst*)inst_base->component; 6062 ldst_inst* inst_cream = (ldst_inst*)inst_base->component;
6041 inst_cream->get_addr(cpu, inst_cream->inst, addr); 6063 inst_cream->get_addr(cpu, inst_cream->inst, addr);
6042 unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xff; 6064 unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xff;
6043 Memory::Write8(addr, value); 6065 cpu->WriteMemory8(addr, value);
6044 } 6066 }
6045 cpu->Reg[15] += cpu->GetInstructionSize(); 6067 cpu->Reg[15] += cpu->GetInstructionSize();
6046 INC_PC(sizeof(ldst_inst)); 6068 INC_PC(sizeof(ldst_inst));
@@ -6091,7 +6113,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
6091 6113
6092 if (cpu->IsExclusiveMemoryAccess(write_addr)) { 6114 if (cpu->IsExclusiveMemoryAccess(write_addr)) {
6093 cpu->UnsetExclusiveMemoryAddress(); 6115 cpu->UnsetExclusiveMemoryAddress();
6094 Memory::Write8(write_addr, cpu->Reg[inst_cream->Rm]); 6116 cpu->WriteMemory8(write_addr, cpu->Reg[inst_cream->Rm]);
6095 RD = 0; 6117 RD = 0;
6096 } else { 6118 } else {
6097 // Failed to write due to mutex access 6119 // Failed to write due to mutex access
@@ -6250,8 +6272,8 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
6250 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) { 6272 if (inst_base->cond == ConditionCode::AL || CondPassed(cpu, inst_base->cond)) {
6251 swp_inst* inst_cream = (swp_inst*)inst_base->component; 6273 swp_inst* inst_cream = (swp_inst*)inst_base->component;
6252 addr = RN; 6274 addr = RN;
6253 unsigned int value = Memory::Read8(addr); 6275 unsigned int value = cpu->ReadMemory8(addr);
6254 Memory::Write8(addr, (RM & 0xFF)); 6276 cpu->WriteMemory8(addr, (RM & 0xFF));
6255 RD = value; 6277 RD = value;
6256 } 6278 }
6257 cpu->Reg[15] += cpu->GetInstructionSize(); 6279 cpu->Reg[15] += cpu->GetInstructionSize();