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-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp36
1 files changed, 35 insertions, 1 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index d953adba9..4dd541656 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -1075,6 +1075,10 @@ typedef struct _swp_inst {
1075 unsigned int Rm; 1075 unsigned int Rm;
1076} swp_inst; 1076} swp_inst;
1077 1077
1078typedef struct setend_inst {
1079 unsigned int set_bigend;
1080} setend_inst;
1081
1078typedef struct _b_2_thumb { 1082typedef struct _b_2_thumb {
1079 unsigned int imm; 1083 unsigned int imm;
1080}b_2_thumb; 1084}b_2_thumb;
@@ -2283,7 +2287,20 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(sel)(unsigned int inst, int index)
2283 return inst_base; 2287 return inst_base;
2284} 2288}
2285 2289
2286static ARM_INST_PTR INTERPRETER_TRANSLATE(setend)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SETEND"); } 2290static ARM_INST_PTR INTERPRETER_TRANSLATE(setend)(unsigned int inst, int index)
2291{
2292 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(setend_inst));
2293 setend_inst* const inst_cream = (setend_inst*)inst_base->component;
2294
2295 inst_base->cond = AL;
2296 inst_base->idx = index;
2297 inst_base->br = NON_BRANCH;
2298 inst_base->load_r15 = 0;
2299
2300 inst_cream->set_bigend = BIT(inst, 9);
2301
2302 return inst_base;
2303}
2287 2304
2288static ARM_INST_PTR INTERPRETER_TRANSLATE(shadd8)(unsigned int inst, int index) 2305static ARM_INST_PTR INTERPRETER_TRANSLATE(shadd8)(unsigned int inst, int index)
2289{ 2306{
@@ -5521,6 +5538,23 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
5521 } 5538 }
5522 5539
5523 SETEND_INST: 5540 SETEND_INST:
5541 {
5542 // SETEND is unconditional
5543 setend_inst* const inst_cream = (setend_inst*)inst_base->component;
5544 const bool big_endian = (inst_cream->set_bigend == 1);
5545
5546 if (big_endian)
5547 cpu->Cpsr |= (1 << 9);
5548 else
5549 cpu->Cpsr &= ~(1 << 9);
5550
5551 LOG_WARNING(Core_ARM11, "SETEND %s executed", big_endian ? "BE" : "LE");
5552
5553 cpu->Reg[15] += GET_INST_SIZE(cpu);
5554 INC_PC(sizeof(setend_inst));
5555 FETCH_INST;
5556 GOTO_NEXT_INST;
5557 }
5524 5558
5525 SHADD8_INST: 5559 SHADD8_INST:
5526 SHADD16_INST: 5560 SHADD16_INST: