diff options
| -rw-r--r-- | src/core/arm/interpreter/armemu.cpp | 29 | ||||
| -rw-r--r-- | src/core/hle/service/gsp_gpu.cpp | 26 |
2 files changed, 38 insertions, 17 deletions
diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp index 07d205755..63cfd03c6 100644 --- a/src/core/arm/interpreter/armemu.cpp +++ b/src/core/arm/interpreter/armemu.cpp | |||
| @@ -5681,11 +5681,8 @@ L_stm_s_takeabort: | |||
| 5681 | /* Attempt to emulate an ARMv6 instruction. | 5681 | /* Attempt to emulate an ARMv6 instruction. |
| 5682 | Returns non-zero upon success. */ | 5682 | Returns non-zero upon success. */ |
| 5683 | 5683 | ||
| 5684 | static int | 5684 | static int handle_v6_insn(ARMul_State* state, ARMword instr) { |
| 5685 | handle_v6_insn (ARMul_State * state, ARMword instr) { | 5685 | switch (BITS(20, 27)) { |
| 5686 | ARMword lhs, temp; | ||
| 5687 | |||
| 5688 | switch (BITS (20, 27)) { | ||
| 5689 | case 0x03: | 5686 | case 0x03: |
| 5690 | printf ("Unhandled v6 insn: ldr\n"); | 5687 | printf ("Unhandled v6 insn: ldr\n"); |
| 5691 | break; | 5688 | break; |
| @@ -5719,7 +5716,7 @@ L_stm_s_takeabort: | |||
| 5719 | /* strex */ | 5716 | /* strex */ |
| 5720 | u32 l = LHSReg; | 5717 | u32 l = LHSReg; |
| 5721 | u32 r = RHSReg; | 5718 | u32 r = RHSReg; |
| 5722 | lhs = LHS; | 5719 | u32 lhs = LHS; |
| 5723 | 5720 | ||
| 5724 | bool enter = false; | 5721 | bool enter = false; |
| 5725 | 5722 | ||
| @@ -5744,7 +5741,7 @@ L_stm_s_takeabort: | |||
| 5744 | case 0x19: | 5741 | case 0x19: |
| 5745 | /* ldrex */ | 5742 | /* ldrex */ |
| 5746 | if (BITS(4, 7) == 0x9) { | 5743 | if (BITS(4, 7) == 0x9) { |
| 5747 | lhs = LHS; | 5744 | u32 lhs = LHS; |
| 5748 | 5745 | ||
| 5749 | state->currentexaddr = lhs; | 5746 | state->currentexaddr = lhs; |
| 5750 | state->currentexval = ARMul_ReadWord(state, lhs); | 5747 | state->currentexval = ARMul_ReadWord(state, lhs); |
| @@ -5763,7 +5760,7 @@ L_stm_s_takeabort: | |||
| 5763 | case 0x1c: | 5760 | case 0x1c: |
| 5764 | if (BITS(4, 7) == 0x9) { | 5761 | if (BITS(4, 7) == 0x9) { |
| 5765 | /* strexb */ | 5762 | /* strexb */ |
| 5766 | lhs = LHS; | 5763 | u32 lhs = LHS; |
| 5767 | 5764 | ||
| 5768 | bool enter = false; | 5765 | bool enter = false; |
| 5769 | 5766 | ||
| @@ -5793,11 +5790,11 @@ L_stm_s_takeabort: | |||
| 5793 | case 0x1d: | 5790 | case 0x1d: |
| 5794 | if ((BITS(4, 7)) == 0x9) { | 5791 | if ((BITS(4, 7)) == 0x9) { |
| 5795 | /* ldrexb */ | 5792 | /* ldrexb */ |
| 5796 | temp = LHS; | 5793 | u32 lhs = LHS; |
| 5797 | LoadByte(state, instr, temp, LUNSIGNED); | 5794 | LoadByte(state, instr, lhs, LUNSIGNED); |
| 5798 | 5795 | ||
| 5799 | state->currentexaddr = temp; | 5796 | state->currentexaddr = lhs; |
| 5800 | state->currentexval = (u32)ARMul_ReadByte(state, temp); | 5797 | state->currentexval = (u32)ARMul_ReadByte(state, lhs); |
| 5801 | 5798 | ||
| 5802 | //state->Reg[BITS(12, 15)] = ARMul_LoadByte(state, state->Reg[BITS(16, 19)]); | 5799 | //state->Reg[BITS(12, 15)] = ARMul_LoadByte(state, state->Reg[BITS(16, 19)]); |
| 5803 | //printf("ldrexb\n"); | 5800 | //printf("ldrexb\n"); |
| @@ -6109,7 +6106,7 @@ L_stm_s_takeabort: | |||
| 6109 | break; | 6106 | break; |
| 6110 | } | 6107 | } |
| 6111 | 6108 | ||
| 6112 | Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFF) | ((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFF) & 0xFF; | 6109 | Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFF) | (((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFF) & 0xFF); |
| 6113 | if (Rm & 0x80) | 6110 | if (Rm & 0x80) |
| 6114 | Rm |= 0xffffff00; | 6111 | Rm |= 0xffffff00; |
| 6115 | 6112 | ||
| @@ -6154,7 +6151,7 @@ L_stm_s_takeabort: | |||
| 6154 | if (ror == -1) | 6151 | if (ror == -1) |
| 6155 | break; | 6152 | break; |
| 6156 | 6153 | ||
| 6157 | Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFFFF) | ((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFFFF) & 0xFFFF; | 6154 | Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFFFF) | (((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFFFF) & 0xFFFF); |
| 6158 | if (Rm & 0x8000) | 6155 | if (Rm & 0x8000) |
| 6159 | Rm |= 0xffff0000; | 6156 | Rm |= 0xffff0000; |
| 6160 | 6157 | ||
| @@ -6250,7 +6247,7 @@ L_stm_s_takeabort: | |||
| 6250 | break; | 6247 | break; |
| 6251 | } | 6248 | } |
| 6252 | 6249 | ||
| 6253 | Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFF) | ((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFF) & 0xFF; | 6250 | Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFF) | (((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFF) & 0xFF); |
| 6254 | 6251 | ||
| 6255 | if (BITS(16, 19) == 0xf) | 6252 | if (BITS(16, 19) == 0xf) |
| 6256 | /* UXTB */ | 6253 | /* UXTB */ |
| @@ -6294,7 +6291,7 @@ L_stm_s_takeabort: | |||
| 6294 | if (ror == -1) | 6291 | if (ror == -1) |
| 6295 | break; | 6292 | break; |
| 6296 | 6293 | ||
| 6297 | Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFFFF) | ((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFFFF) & 0xFFFF; | 6294 | Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFFFF) | (((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFFFF) & 0xFFFF); |
| 6298 | 6295 | ||
| 6299 | /* UXT */ | 6296 | /* UXT */ |
| 6300 | /* state->Reg[BITS (12, 15)] = Rm; */ | 6297 | /* state->Reg[BITS (12, 15)] = Rm; */ |
diff --git a/src/core/hle/service/gsp_gpu.cpp b/src/core/hle/service/gsp_gpu.cpp index db8027142..8c9ad2712 100644 --- a/src/core/hle/service/gsp_gpu.cpp +++ b/src/core/hle/service/gsp_gpu.cpp | |||
| @@ -145,6 +145,30 @@ static void SetBufferSwap(Service::Interface* self) { | |||
| 145 | } | 145 | } |
| 146 | 146 | ||
| 147 | /** | 147 | /** |
| 148 | * GSP_GPU::FlushDataCache service function | ||
| 149 | * | ||
| 150 | * This Function is a no-op, We aren't emulating the CPU cache any time soon. | ||
| 151 | * | ||
| 152 | * Inputs: | ||
| 153 | * 1 : Address | ||
| 154 | * 2 : Size | ||
| 155 | * 3 : Value 0, some descriptor for the KProcess Handle | ||
| 156 | * 4 : KProcess handle | ||
| 157 | * Outputs: | ||
| 158 | * 1 : Result of function, 0 on success, otherwise error code | ||
| 159 | */ | ||
| 160 | static void FlushDataCache(Service::Interface* self) { | ||
| 161 | u32* cmd_buff = Kernel::GetCommandBuffer(); | ||
| 162 | u32 address = cmd_buff[1]; | ||
| 163 | u32 size = cmd_buff[2]; | ||
| 164 | u32 process = cmd_buff[4]; | ||
| 165 | |||
| 166 | // TODO(purpasmart96): Verify return header on HW | ||
| 167 | |||
| 168 | cmd_buff[1] = RESULT_SUCCESS.raw; // No error | ||
| 169 | } | ||
| 170 | |||
| 171 | /** | ||
| 148 | * GSP_GPU::RegisterInterruptRelayQueue service function | 172 | * GSP_GPU::RegisterInterruptRelayQueue service function |
| 149 | * Inputs: | 173 | * Inputs: |
| 150 | * 1 : "Flags" field, purpose is unknown | 174 | * 1 : "Flags" field, purpose is unknown |
| @@ -335,7 +359,7 @@ const Interface::FunctionInfo FunctionTable[] = { | |||
| 335 | {0x00050200, SetBufferSwap, "SetBufferSwap"}, | 359 | {0x00050200, SetBufferSwap, "SetBufferSwap"}, |
| 336 | {0x00060082, nullptr, "SetCommandList"}, | 360 | {0x00060082, nullptr, "SetCommandList"}, |
| 337 | {0x000700C2, nullptr, "RequestDma"}, | 361 | {0x000700C2, nullptr, "RequestDma"}, |
| 338 | {0x00080082, nullptr, "FlushDataCache"}, | 362 | {0x00080082, FlushDataCache, "FlushDataCache"}, |
| 339 | {0x00090082, nullptr, "InvalidateDataCache"}, | 363 | {0x00090082, nullptr, "InvalidateDataCache"}, |
| 340 | {0x000A0044, nullptr, "RegisterInterruptEvents"}, | 364 | {0x000A0044, nullptr, "RegisterInterruptEvents"}, |
| 341 | {0x000B0040, nullptr, "SetLcdForceBlack"}, | 365 | {0x000B0040, nullptr, "SetLcdForceBlack"}, |