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-rw-r--r--src/video_core/renderer_vulkan/fixed_pipeline_state.cpp3
-rw-r--r--src/video_core/renderer_vulkan/fixed_pipeline_state.h10
-rw-r--r--src/video_core/renderer_vulkan/vk_graphics_pipeline.cpp5
-rw-r--r--src/video_core/renderer_vulkan/vk_pipeline_cache.cpp3
-rw-r--r--src/video_core/renderer_vulkan/vk_rasterizer.cpp11
-rw-r--r--src/video_core/renderer_vulkan/vk_rasterizer.h1
6 files changed, 7 insertions, 26 deletions
diff --git a/src/video_core/renderer_vulkan/fixed_pipeline_state.cpp b/src/video_core/renderer_vulkan/fixed_pipeline_state.cpp
index 81a39a3b8..da5c550ea 100644
--- a/src/video_core/renderer_vulkan/fixed_pipeline_state.cpp
+++ b/src/video_core/renderer_vulkan/fixed_pipeline_state.cpp
@@ -58,6 +58,7 @@ void FixedPipelineState::Fill(const Maxwell& regs, bool has_extended_dynamic_sta
58 logic_op_enable.Assign(regs.logic_op.enable != 0 ? 1 : 0); 58 logic_op_enable.Assign(regs.logic_op.enable != 0 ? 1 : 0);
59 logic_op.Assign(PackLogicOp(regs.logic_op.operation)); 59 logic_op.Assign(PackLogicOp(regs.logic_op.operation));
60 rasterize_enable.Assign(regs.rasterize_enable != 0 ? 1 : 0); 60 rasterize_enable.Assign(regs.rasterize_enable != 0 ? 1 : 0);
61 topology.Assign(regs.draw.topology);
61 62
62 std::memcpy(&point_size, &regs.point_size, sizeof(point_size)); // TODO: C++20 std::bit_cast 63 std::memcpy(&point_size, &regs.point_size, sizeof(point_size)); // TODO: C++20 std::bit_cast
63 64
@@ -131,7 +132,6 @@ void FixedPipelineState::BlendingAttachment::Fill(const Maxwell& regs, std::size
131} 132}
132 133
133void FixedPipelineState::DynamicState::Fill(const Maxwell& regs) { 134void FixedPipelineState::DynamicState::Fill(const Maxwell& regs) {
134 const u32 topology_index = static_cast<u32>(regs.draw.topology.Value());
135 u32 packed_front_face = PackFrontFace(regs.front_face); 135 u32 packed_front_face = PackFrontFace(regs.front_face);
136 if (regs.screen_y_control.triangle_rast_flip != 0) { 136 if (regs.screen_y_control.triangle_rast_flip != 0) {
137 // Flip front face 137 // Flip front face
@@ -161,7 +161,6 @@ void FixedPipelineState::DynamicState::Fill(const Maxwell& regs) {
161 depth_test_enable.Assign(regs.depth_test_enable); 161 depth_test_enable.Assign(regs.depth_test_enable);
162 front_face.Assign(packed_front_face); 162 front_face.Assign(packed_front_face);
163 depth_test_func.Assign(PackComparisonOp(regs.depth_test_func)); 163 depth_test_func.Assign(PackComparisonOp(regs.depth_test_func));
164 topology.Assign(topology_index);
165 cull_face.Assign(PackCullFace(regs.cull_face)); 164 cull_face.Assign(PackCullFace(regs.cull_face));
166 cull_enable.Assign(regs.cull_test_enabled != 0 ? 1 : 0); 165 cull_enable.Assign(regs.cull_test_enabled != 0 ? 1 : 0);
167 166
diff --git a/src/video_core/renderer_vulkan/fixed_pipeline_state.h b/src/video_core/renderer_vulkan/fixed_pipeline_state.h
index cdcbb65f5..2c18eeaae 100644
--- a/src/video_core/renderer_vulkan/fixed_pipeline_state.h
+++ b/src/video_core/renderer_vulkan/fixed_pipeline_state.h
@@ -150,9 +150,8 @@ struct FixedPipelineState {
150 }; 150 };
151 union { 151 union {
152 u32 raw2; 152 u32 raw2;
153 BitField<0, 4, u32> topology; 153 BitField<0, 2, u32> cull_face;
154 BitField<4, 2, u32> cull_face; 154 BitField<2, 1, u32> cull_enable;
155 BitField<6, 1, u32> cull_enable;
156 }; 155 };
157 std::array<VertexBinding, Maxwell::NumVertexArrays> vertex_bindings; 156 std::array<VertexBinding, Maxwell::NumVertexArrays> vertex_bindings;
158 157
@@ -169,10 +168,6 @@ struct FixedPipelineState {
169 Maxwell::FrontFace FrontFace() const noexcept { 168 Maxwell::FrontFace FrontFace() const noexcept {
170 return UnpackFrontFace(front_face.Value()); 169 return UnpackFrontFace(front_face.Value());
171 } 170 }
172
173 constexpr Maxwell::PrimitiveTopology Topology() const noexcept {
174 return static_cast<Maxwell::PrimitiveTopology>(topology.Value());
175 }
176 }; 171 };
177 172
178 union { 173 union {
@@ -190,6 +185,7 @@ struct FixedPipelineState {
190 BitField<18, 1, u32> logic_op_enable; 185 BitField<18, 1, u32> logic_op_enable;
191 BitField<19, 4, u32> logic_op; 186 BitField<19, 4, u32> logic_op;
192 BitField<23, 1, u32> rasterize_enable; 187 BitField<23, 1, u32> rasterize_enable;
188 BitField<24, 4, Maxwell::PrimitiveTopology> topology;
193 }; 189 };
194 u32 point_size; 190 u32 point_size;
195 std::array<u32, Maxwell::NumVertexArrays> binding_divisors; 191 std::array<u32, Maxwell::NumVertexArrays> binding_divisors;
diff --git a/src/video_core/renderer_vulkan/vk_graphics_pipeline.cpp b/src/video_core/renderer_vulkan/vk_graphics_pipeline.cpp
index a4b9e7ef5..696eaeb5f 100644
--- a/src/video_core/renderer_vulkan/vk_graphics_pipeline.cpp
+++ b/src/video_core/renderer_vulkan/vk_graphics_pipeline.cpp
@@ -261,12 +261,12 @@ vk::Pipeline VKGraphicsPipeline::CreatePipeline(const RenderPassParams& renderpa
261 vertex_input_ci.pNext = &input_divisor_ci; 261 vertex_input_ci.pNext = &input_divisor_ci;
262 } 262 }
263 263
264 const auto input_assembly_topology = MaxwellToVK::PrimitiveTopology(device, dynamic.Topology()); 264 const auto input_assembly_topology = MaxwellToVK::PrimitiveTopology(device, state.topology);
265 const VkPipelineInputAssemblyStateCreateInfo input_assembly_ci{ 265 const VkPipelineInputAssemblyStateCreateInfo input_assembly_ci{
266 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO, 266 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
267 .pNext = nullptr, 267 .pNext = nullptr,
268 .flags = 0, 268 .flags = 0,
269 .topology = MaxwellToVK::PrimitiveTopology(device, dynamic.Topology()), 269 .topology = MaxwellToVK::PrimitiveTopology(device, state.topology),
270 .primitiveRestartEnable = state.primitive_restart_enable != 0 && 270 .primitiveRestartEnable = state.primitive_restart_enable != 0 &&
271 SupportsPrimitiveRestart(input_assembly_topology), 271 SupportsPrimitiveRestart(input_assembly_topology),
272 }; 272 };
@@ -400,7 +400,6 @@ vk::Pipeline VKGraphicsPipeline::CreatePipeline(const RenderPassParams& renderpa
400 static constexpr std::array extended{ 400 static constexpr std::array extended{
401 VK_DYNAMIC_STATE_CULL_MODE_EXT, 401 VK_DYNAMIC_STATE_CULL_MODE_EXT,
402 VK_DYNAMIC_STATE_FRONT_FACE_EXT, 402 VK_DYNAMIC_STATE_FRONT_FACE_EXT,
403 VK_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY_EXT,
404 VK_DYNAMIC_STATE_VERTEX_INPUT_BINDING_STRIDE_EXT, 403 VK_DYNAMIC_STATE_VERTEX_INPUT_BINDING_STRIDE_EXT,
405 VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT, 404 VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT,
406 VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT, 405 VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT,
diff --git a/src/video_core/renderer_vulkan/vk_pipeline_cache.cpp b/src/video_core/renderer_vulkan/vk_pipeline_cache.cpp
index 5c038f4bc..dedc9c466 100644
--- a/src/video_core/renderer_vulkan/vk_pipeline_cache.cpp
+++ b/src/video_core/renderer_vulkan/vk_pipeline_cache.cpp
@@ -331,8 +331,7 @@ void VKPipelineCache::OnShaderRemoval(Shader* shader) {
331std::pair<SPIRVProgram, std::vector<VkDescriptorSetLayoutBinding>> 331std::pair<SPIRVProgram, std::vector<VkDescriptorSetLayoutBinding>>
332VKPipelineCache::DecompileShaders(const FixedPipelineState& fixed_state) { 332VKPipelineCache::DecompileShaders(const FixedPipelineState& fixed_state) {
333 Specialization specialization; 333 Specialization specialization;
334 if (fixed_state.dynamic_state.Topology() == Maxwell::PrimitiveTopology::Points || 334 if (fixed_state.topology == Maxwell::PrimitiveTopology::Points) {
335 device.IsExtExtendedDynamicStateSupported()) {
336 float point_size; 335 float point_size;
337 std::memcpy(&point_size, &fixed_state.point_size, sizeof(float)); 336 std::memcpy(&point_size, &fixed_state.point_size, sizeof(float));
338 specialization.point_size = point_size; 337 specialization.point_size = point_size;
diff --git a/src/video_core/renderer_vulkan/vk_rasterizer.cpp b/src/video_core/renderer_vulkan/vk_rasterizer.cpp
index f3c2483c8..e0fb8693f 100644
--- a/src/video_core/renderer_vulkan/vk_rasterizer.cpp
+++ b/src/video_core/renderer_vulkan/vk_rasterizer.cpp
@@ -948,7 +948,6 @@ void RasterizerVulkan::UpdateDynamicStates() {
948 UpdateDepthWriteEnable(regs); 948 UpdateDepthWriteEnable(regs);
949 UpdateDepthCompareOp(regs); 949 UpdateDepthCompareOp(regs);
950 UpdateFrontFace(regs); 950 UpdateFrontFace(regs);
951 UpdatePrimitiveTopology(regs);
952 UpdateStencilOp(regs); 951 UpdateStencilOp(regs);
953 UpdateStencilTestEnable(regs); 952 UpdateStencilTestEnable(regs);
954 } 953 }
@@ -1418,16 +1417,6 @@ void RasterizerVulkan::UpdateFrontFace(Tegra::Engines::Maxwell3D::Regs& regs) {
1418 [front_face](vk::CommandBuffer cmdbuf) { cmdbuf.SetFrontFaceEXT(front_face); }); 1417 [front_face](vk::CommandBuffer cmdbuf) { cmdbuf.SetFrontFaceEXT(front_face); });
1419} 1418}
1420 1419
1421void RasterizerVulkan::UpdatePrimitiveTopology(Tegra::Engines::Maxwell3D::Regs& regs) {
1422 const Maxwell::PrimitiveTopology primitive_topology = regs.draw.topology.Value();
1423 if (!state_tracker.ChangePrimitiveTopology(primitive_topology)) {
1424 return;
1425 }
1426 scheduler.Record([this, primitive_topology](vk::CommandBuffer cmdbuf) {
1427 cmdbuf.SetPrimitiveTopologyEXT(MaxwellToVK::PrimitiveTopology(device, primitive_topology));
1428 });
1429}
1430
1431void RasterizerVulkan::UpdateStencilOp(Tegra::Engines::Maxwell3D::Regs& regs) { 1420void RasterizerVulkan::UpdateStencilOp(Tegra::Engines::Maxwell3D::Regs& regs) {
1432 if (!state_tracker.TouchStencilOp()) { 1421 if (!state_tracker.TouchStencilOp()) {
1433 return; 1422 return;
diff --git a/src/video_core/renderer_vulkan/vk_rasterizer.h b/src/video_core/renderer_vulkan/vk_rasterizer.h
index b47c8fc13..237e51fa4 100644
--- a/src/video_core/renderer_vulkan/vk_rasterizer.h
+++ b/src/video_core/renderer_vulkan/vk_rasterizer.h
@@ -259,7 +259,6 @@ private:
259 void UpdateDepthWriteEnable(Tegra::Engines::Maxwell3D::Regs& regs); 259 void UpdateDepthWriteEnable(Tegra::Engines::Maxwell3D::Regs& regs);
260 void UpdateDepthCompareOp(Tegra::Engines::Maxwell3D::Regs& regs); 260 void UpdateDepthCompareOp(Tegra::Engines::Maxwell3D::Regs& regs);
261 void UpdateFrontFace(Tegra::Engines::Maxwell3D::Regs& regs); 261 void UpdateFrontFace(Tegra::Engines::Maxwell3D::Regs& regs);
262 void UpdatePrimitiveTopology(Tegra::Engines::Maxwell3D::Regs& regs);
263 void UpdateStencilOp(Tegra::Engines::Maxwell3D::Regs& regs); 262 void UpdateStencilOp(Tegra::Engines::Maxwell3D::Regs& regs);
264 void UpdateStencilTestEnable(Tegra::Engines::Maxwell3D::Regs& regs); 263 void UpdateStencilTestEnable(Tegra::Engines::Maxwell3D::Regs& regs);
265 264