diff options
| -rw-r--r-- | src/shader_recompiler/backend/spirv/emit_spirv_context_get_set.cpp | 8 | ||||
| -rw-r--r-- | src/shader_recompiler/frontend/maxwell/translate/impl/texture_mipmap_level.cpp | 7 |
2 files changed, 3 insertions, 12 deletions
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_context_get_set.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_context_get_set.cpp index fee510f7b..07c2b7b8a 100644 --- a/src/shader_recompiler/backend/spirv/emit_spirv_context_get_set.cpp +++ b/src/shader_recompiler/backend/spirv/emit_spirv_context_get_set.cpp | |||
| @@ -339,9 +339,7 @@ Id EmitGetAttribute(EmitContext& ctx, IR::Attribute attr, Id vertex) { | |||
| 339 | if (ctx.profile.support_vertex_instance_id) { | 339 | if (ctx.profile.support_vertex_instance_id) { |
| 340 | return ctx.OpBitcast(ctx.F32[1], ctx.OpLoad(ctx.U32[1], ctx.vertex_id)); | 340 | return ctx.OpBitcast(ctx.F32[1], ctx.OpLoad(ctx.U32[1], ctx.vertex_id)); |
| 341 | } else { | 341 | } else { |
| 342 | const Id index{ctx.OpLoad(ctx.U32[1], ctx.vertex_index)}; | 342 | return ctx.OpBitcast(ctx.F32[1], ctx.OpLoad(ctx.U32[1], ctx.vertex_index)); |
| 343 | const Id base{ctx.OpLoad(ctx.U32[1], ctx.base_vertex)}; | ||
| 344 | return ctx.OpBitcast(ctx.F32[1], ctx.OpISub(ctx.U32[1], index, base)); | ||
| 345 | } | 343 | } |
| 346 | case IR::Attribute::BaseInstance: | 344 | case IR::Attribute::BaseInstance: |
| 347 | return ctx.OpBitcast(ctx.F32[1], ctx.OpLoad(ctx.U32[1], ctx.base_instance)); | 345 | return ctx.OpBitcast(ctx.F32[1], ctx.OpLoad(ctx.U32[1], ctx.base_instance)); |
| @@ -386,9 +384,7 @@ Id EmitGetAttributeU32(EmitContext& ctx, IR::Attribute attr, Id) { | |||
| 386 | if (ctx.profile.support_vertex_instance_id) { | 384 | if (ctx.profile.support_vertex_instance_id) { |
| 387 | return ctx.OpLoad(ctx.U32[1], ctx.vertex_id); | 385 | return ctx.OpLoad(ctx.U32[1], ctx.vertex_id); |
| 388 | } else { | 386 | } else { |
| 389 | const Id index{ctx.OpLoad(ctx.U32[1], ctx.vertex_index)}; | 387 | return ctx.OpLoad(ctx.U32[1], ctx.vertex_index); |
| 390 | const Id base{ctx.OpLoad(ctx.U32[1], ctx.base_vertex)}; | ||
| 391 | return ctx.OpISub(ctx.U32[1], index, base); | ||
| 392 | } | 388 | } |
| 393 | case IR::Attribute::BaseInstance: | 389 | case IR::Attribute::BaseInstance: |
| 394 | return ctx.OpLoad(ctx.U32[1], ctx.base_instance); | 390 | return ctx.OpLoad(ctx.U32[1], ctx.base_instance); |
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/texture_mipmap_level.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/texture_mipmap_level.cpp index 639da1e9c..eeb49444f 100644 --- a/src/shader_recompiler/frontend/maxwell/translate/impl/texture_mipmap_level.cpp +++ b/src/shader_recompiler/frontend/maxwell/translate/impl/texture_mipmap_level.cpp | |||
| @@ -102,12 +102,7 @@ void Impl(TranslatorVisitor& v, u64 insn, bool is_bindless) { | |||
| 102 | } | 102 | } |
| 103 | IR::F32 value{v.ir.CompositeExtract(sample, element)}; | 103 | IR::F32 value{v.ir.CompositeExtract(sample, element)}; |
| 104 | if (element < 2) { | 104 | if (element < 2) { |
| 105 | IR::U32 casted_value; | 105 | IR::U32 casted_value = v.ir.ConvertFToU(32, value); |
| 106 | if (element == 0) { | ||
| 107 | casted_value = v.ir.ConvertFToU(32, value); | ||
| 108 | } else { | ||
| 109 | casted_value = v.ir.ConvertFToS(16, value); | ||
| 110 | } | ||
| 111 | v.X(dest_reg, v.ir.ShiftLeftLogical(casted_value, v.ir.Imm32(8))); | 106 | v.X(dest_reg, v.ir.ShiftLeftLogical(casted_value, v.ir.Imm32(8))); |
| 112 | } else { | 107 | } else { |
| 113 | v.F(dest_reg, value); | 108 | v.F(dest_reg, value); |