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-rw-r--r--src/video_core/shader/node.h4
-rw-r--r--src/video_core/shader/shader_ir.cpp46
-rw-r--r--src/video_core/shader/shader_ir.h3
3 files changed, 50 insertions, 3 deletions
diff --git a/src/video_core/shader/node.h b/src/video_core/shader/node.h
index 8f230d57a..11a8a3f70 100644
--- a/src/video_core/shader/node.h
+++ b/src/video_core/shader/node.h
@@ -464,6 +464,10 @@ public:
464 return operands.size(); 464 return operands.size();
465 } 465 }
466 466
467 NodeBlock GetOperands() const {
468 return operands;
469 }
470
467 const Node& operator[](std::size_t operand_index) const { 471 const Node& operator[](std::size_t operand_index) const {
468 return operands.at(operand_index); 472 return operands.at(operand_index);
469 } 473 }
diff --git a/src/video_core/shader/shader_ir.cpp b/src/video_core/shader/shader_ir.cpp
index 29d794b34..14206d3ae 100644
--- a/src/video_core/shader/shader_ir.cpp
+++ b/src/video_core/shader/shader_ir.cpp
@@ -387,9 +387,49 @@ void ShaderIR::SetInternalFlagsFromInteger(NodeBlock& bb, Node value, bool sets_
387 if (!sets_cc) { 387 if (!sets_cc) {
388 return; 388 return;
389 } 389 }
390 Node zerop = Operation(OperationCode::LogicalIEqual, std::move(value), Immediate(0)); 390 switch (value->index()) {
391 SetInternalFlag(bb, InternalFlag::Zero, std::move(zerop)); 391 case 0:
392 LOG_WARNING(HW_GPU, "Condition codes implementation is incomplete"); 392 Iterop(bb, value);
393 break;
394 case 2:
395 if (const auto gpr = std::get_if<GprNode>(value.get())) {
396 LOG_WARNING(HW_GPU, "GprNode: index={}", gpr->GetIndex());
397 Node zerop = Operation(OperationCode::LogicalIEqual, std::move(value),
398 Immediate(gpr->GetIndex()));
399 SetInternalFlag(bb, InternalFlag::Zero, std::move(zerop));
400 }
401 break;
402
403 default:
404 Node zerop = Operation(OperationCode::LogicalIEqual, std::move(value), Immediate(0));
405 SetInternalFlag(bb, InternalFlag::Zero, std::move(zerop));
406 LOG_WARNING(HW_GPU, "Node Type: {}", value->index());
407 break;
408 }
409}
410
411void ShaderIR::Iterop(NodeBlock& nb, Node var) {
412 if (const auto op = std::get_if<OperationNode>(var.get())) {
413 if (op->GetOperandsCount() > 0) {
414 for (auto& opss : op->GetOperands()) {
415 switch (opss->index()) {
416 case 0:
417 return Iterop(nb, opss);
418 case 2:
419 if (const auto gpr = std::get_if<GprNode>(opss.get())) {
420 LOG_WARNING(HW_GPU, "Child GprNode: index={}", gpr->GetIndex());
421 Node zerop = Operation(OperationCode::LogicalIEqual, std::move(opss),
422 Immediate(gpr->GetIndex()));
423 SetInternalFlag(nb, InternalFlag::Zero, std::move(zerop));
424 }
425 break;
426 default:
427 LOG_WARNING(HW_GPU, "Child Node Type: {}", opss->index());
428 break;
429 }
430 }
431 }
432 }
393} 433}
394 434
395Node ShaderIR::BitfieldExtract(Node value, u32 offset, u32 bits) { 435Node ShaderIR::BitfieldExtract(Node value, u32 offset, u32 bits) {
diff --git a/src/video_core/shader/shader_ir.h b/src/video_core/shader/shader_ir.h
index 3a98b2104..2484b1c6a 100644
--- a/src/video_core/shader/shader_ir.h
+++ b/src/video_core/shader/shader_ir.h
@@ -346,6 +346,9 @@ private:
346 /// Access a bindless image sampler. 346 /// Access a bindless image sampler.
347 Image& GetBindlessImage(Tegra::Shader::Register reg, Tegra::Shader::ImageType type); 347 Image& GetBindlessImage(Tegra::Shader::Register reg, Tegra::Shader::ImageType type);
348 348
349 /// Recursive Iteration over the OperationNode operands
350 void Iterop(NodeBlock& nb, Node var);
351
349 /// Extracts a sequence of bits from a node 352 /// Extracts a sequence of bits from a node
350 Node BitfieldExtract(Node value, u32 offset, u32 bits); 353 Node BitfieldExtract(Node value, u32 offset, u32 bits);
351 354