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-rw-r--r--src/core/arm/dynarmic/arm_dynarmic_32.cpp6
-rw-r--r--src/core/arm/dynarmic/arm_dynarmic_64.cpp6
2 files changed, 12 insertions, 0 deletions
diff --git a/src/core/arm/dynarmic/arm_dynarmic_32.cpp b/src/core/arm/dynarmic/arm_dynarmic_32.cpp
index 6c4c8e9e4..c650a4dfb 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_32.cpp
+++ b/src/core/arm/dynarmic/arm_dynarmic_32.cpp
@@ -255,6 +255,9 @@ void ARM_Dynarmic_32::ChangeProcessorID(std::size_t new_core_id) {
255} 255}
256 256
257void ARM_Dynarmic_32::SaveContext(ThreadContext32& ctx) { 257void ARM_Dynarmic_32::SaveContext(ThreadContext32& ctx) {
258 if (!jit) {
259 return;
260 }
258 Dynarmic::A32::Context context; 261 Dynarmic::A32::Context context;
259 jit->SaveContext(context); 262 jit->SaveContext(context);
260 ctx.cpu_registers = context.Regs(); 263 ctx.cpu_registers = context.Regs();
@@ -264,6 +267,9 @@ void ARM_Dynarmic_32::SaveContext(ThreadContext32& ctx) {
264} 267}
265 268
266void ARM_Dynarmic_32::LoadContext(const ThreadContext32& ctx) { 269void ARM_Dynarmic_32::LoadContext(const ThreadContext32& ctx) {
270 if (!jit) {
271 return;
272 }
267 Dynarmic::A32::Context context; 273 Dynarmic::A32::Context context;
268 context.Regs() = ctx.cpu_registers; 274 context.Regs() = ctx.cpu_registers;
269 context.ExtRegs() = ctx.extension_registers; 275 context.ExtRegs() = ctx.extension_registers;
diff --git a/src/core/arm/dynarmic/arm_dynarmic_64.cpp b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
index 4c5ebca22..ae5566ab8 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_64.cpp
+++ b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
@@ -294,6 +294,9 @@ void ARM_Dynarmic_64::ChangeProcessorID(std::size_t new_core_id) {
294} 294}
295 295
296void ARM_Dynarmic_64::SaveContext(ThreadContext64& ctx) { 296void ARM_Dynarmic_64::SaveContext(ThreadContext64& ctx) {
297 if (!jit) {
298 return;
299 }
297 ctx.cpu_registers = jit->GetRegisters(); 300 ctx.cpu_registers = jit->GetRegisters();
298 ctx.sp = jit->GetSP(); 301 ctx.sp = jit->GetSP();
299 ctx.pc = jit->GetPC(); 302 ctx.pc = jit->GetPC();
@@ -305,6 +308,9 @@ void ARM_Dynarmic_64::SaveContext(ThreadContext64& ctx) {
305} 308}
306 309
307void ARM_Dynarmic_64::LoadContext(const ThreadContext64& ctx) { 310void ARM_Dynarmic_64::LoadContext(const ThreadContext64& ctx) {
311 if (!jit) {
312 return;
313 }
308 jit->SetRegisters(ctx.cpu_registers); 314 jit->SetRegisters(ctx.cpu_registers);
309 jit->SetSP(ctx.sp); 315 jit->SetSP(ctx.sp);
310 jit->SetPC(ctx.pc); 316 jit->SetPC(ctx.pc);