3 files changed, 115 insertions, 67 deletions

diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp
index 1a589e39c..b9ac8b9ad 100644
--- a/src/core/arm/interpreter/armemu.cpp
+++ b/src/core/arm/interpreter/armemu.cpp
@@ -1356,7 +1356,13 @@ mainswitch:
                     }
                     break;
 
-                case 0x04:      /* SUB reg */
+                case 0x04: /* SUB reg */
+                    // Signifies UMAAL
+                    if (state->is_v6 && BITS(4, 7) == 0x09) {
+                        if (handle_v6_insn(state, instr))
+                            break;
+                    }
+
 #ifdef MODET
                     if (BITS (4, 7) == 0xB) {
                         /* STRH immediate offset, no write-back, down, post indexed.  */
@@ -3103,12 +3109,18 @@ mainswitch:
                         state->Reg[idest] = (state->Reg[rfis] & 0xFFFF) | ((state->Reg[rlast] << ishi) & 0xFFFF0000);
                         break;
                     } else if ((instr & 0x70) == 0x50) { //pkhtb
-                        u8 idest = BITS(12, 15);
-                        u8 rfis = BITS(16, 19);
-                        u8 rlast = BITS(0, 3);
-                        u8 ishi = BITS(7, 11);
-                        if (ishi == 0)ishi = 0x20;
-                        state->Reg[idest] = (((int)(state->Reg[rlast]) >> (int)(ishi))& 0xFFFF) | ((state->Reg[rfis]) & 0xFFFF0000);
+                        const u8 rd_idx = BITS(12, 15);
+                        const u8 rn_idx = BITS(16, 19);
+                        const u8 rm_idx = BITS(0, 3);
+                        const u8 imm5 = BITS(7, 11);
+
+                        ARMword val;
+                        if (imm5 >= 32)
+                            val = (state->Reg[rm_idx] >> 31);
+                        else
+                            val = (state->Reg[rm_idx] >> imm5);
+
+                        state->Reg[rd_idx] = (val & 0xFFFF) | ((state->Reg[rn_idx]) & 0xFFFF0000);
                         break;
                     } else if (BIT (4)) {
 #ifdef MODE32
@@ -5677,8 +5689,24 @@ L_stm_s_takeabort:
         case 0x03:
             printf ("Unhandled v6 insn: ldr\n");
             break;
-        case 0x04:
-            printf ("Unhandled v6 insn: umaal\n");
+        case 0x04: // UMAAL
+            {
+                const u8 rm_idx = BITS(8, 11);
+                const u8 rn_idx = BITS(0, 3);
+                const u8 rd_lo_idx = BITS(12, 15);
+                const u8 rd_hi_idx = BITS(16, 19);
+
+                const u32 rm_val = state->Reg[rm_idx];
+                const u32 rn_val = state->Reg[rn_idx];
+                const u32 rd_lo_val = state->Reg[rd_lo_idx];
+                const u32 rd_hi_val = state->Reg[rd_hi_idx];
+
+                const u64 result = (rn_val * rm_val) + rd_lo_val + rd_hi_val;
+
+                state->Reg[rd_lo_idx] = (result & 0xFFFFFFFF);
+                state->Reg[rd_hi_idx] = ((result >> 32) & 0xFFFFFFFF);
+                return 1;
+            }
             break;
         case 0x06:
             printf ("Unhandled v6 insn: mls/str\n");
@@ -5799,49 +5827,38 @@ L_stm_s_takeabort:
         case 0x3f:
             printf ("Unhandled v6 insn: rbit\n");
             break;
-        case 0x61:
-            if ((instr & 0xFF0) == 0xf70) { //ssub16
-                u8 tar = BITS(12, 15);
-                u8 src1 = BITS(16, 19);
-                u8 src2 = BITS(0, 3);
-                s16 a1 = (state->Reg[src1] & 0xFFFF);
-                s16 a2 = ((state->Reg[src1] >> 0x10) & 0xFFFF);
-                s16 b1 = (state->Reg[src2] & 0xFFFF);
-                s16 b2 = ((state->Reg[src2] >> 0x10) & 0xFFFF);
-                                state->Reg[tar] = ((a1 - a2) & 0xFFFF) | (((b1 - b2) & 0xFFFF) << 0x10);
-                return 1;
-            } else if ((instr & 0xFF0) == 0xf10) { //sadd16
+        case 0x61: // SSUB16, SADD16, SSAX, and SASX
+            if ((instr & 0xFF0) == 0xf70 || (instr & 0xFF0) == 0xf10 ||
+                (instr & 0xFF0) == 0xf50 || (instr & 0xFF0) == 0xf30)
+            {
                 const u8 rd_idx = BITS(12, 15);
                 const u8 rm_idx = BITS(0, 3);
                 const u8 rn_idx = BITS(16, 19);
-                const s16 rm_lo = (state->Reg[rm_idx] & 0xFFFF);
-                const s16 rm_hi = ((state->Reg[rm_idx] >> 16) & 0xFFFF);
                 const s16 rn_lo = (state->Reg[rn_idx] & 0xFFFF);
                 const s16 rn_hi = ((state->Reg[rn_idx] >> 16) & 0xFFFF);
+                const s16 rm_lo = (state->Reg[rm_idx] & 0xFFFF);
+                const s16 rm_hi = ((state->Reg[rm_idx] >> 16) & 0xFFFF);
 
-                state->Reg[rd_idx] = ((rn_lo + rm_lo) & 0xFFFF) | (((rn_hi + rm_hi) & 0xFFFF) << 16);
-                return 1;
-            } else if ((instr & 0xFF0) == 0xf50) { //ssax
-                u8 tar = BITS(12, 15);
-                u8 src1 = BITS(16, 19);
-                u8 src2 = BITS(0, 3);
-                s16 a1 = (state->Reg[src1] & 0xFFFF);
-                s16 a2 = ((state->Reg[src1] >> 0x10) & 0xFFFF);
-                s16 b1 = (state->Reg[src2] & 0xFFFF);
-                s16 b2 = ((state->Reg[src2] >> 0x10) & 0xFFFF);
-                                state->Reg[tar] = ((a1 + b2) & 0xFFFF) | (((a2 - b1) & 0xFFFF) << 0x10);
-                return 1;
-            } else if ((instr & 0xFF0) == 0xf30) { //sasx
-                u8 tar = BITS(12, 15);
-                u8 src1 = BITS(16, 19);
-                u8 src2 = BITS(0, 3);
-                s16 a1 = (state->Reg[src1] & 0xFFFF);
-                s16 a2 = ((state->Reg[src1] >> 0x10) & 0xFFFF);
-                s16 b1 = (state->Reg[src2] & 0xFFFF);
-                s16 b2 = ((state->Reg[src2] >> 0x10) & 0xFFFF);
-                                state->Reg[tar] = ((a1 - b2) & 0xFFFF) | (((a2 + b1) & 0xFFFF) << 0x10);
+                // SSUB16
+                if ((instr & 0xFF0) == 0xf70) {
+                    state->Reg[rd_idx] = ((rn_lo - rm_lo) & 0xFFFF) | (((rn_hi - rm_hi) & 0xFFFF) << 16);
+                }
+                // SADD16
+                else if ((instr & 0xFF0) == 0xf10) {
+                    state->Reg[rd_idx] = ((rn_lo + rm_lo) & 0xFFFF) | (((rn_hi + rm_hi) & 0xFFFF) << 16);
+                }
+                // SSAX
+                else if ((instr & 0xFF0) == 0xf50) {
+                    state->Reg[rd_idx] = ((rn_lo + rm_hi) & 0xFFFF) | (((rn_hi - rm_lo) & 0xFFFF) << 16);
+                }
+                // SASX
+                else {
+                    state->Reg[rd_idx] = ((rn_lo - rm_hi) & 0xFFFF) | (((rn_hi + rm_lo) & 0xFFFF) << 16);
+                }
                 return 1;
-            } else printf ("Unhandled v6 insn: sadd/ssub/ssax/sasx\n");
+            } else {
+                printf("Unhandled v6 insn: %08x", BITS(20, 27));
+            }
             break;
         case 0x62: // QSUB16 and QADD16
             if ((instr & 0xFF0) == 0xf70 || (instr & 0xFF0) == 0xf10) {
@@ -5930,11 +5947,29 @@ L_stm_s_takeabort:
                         b2 = ((u8)(from >> 8) + (u8)(to >> 8));
                         b3 = ((u8)(from >> 16) + (u8)(to >> 16));
                         b4 = ((u8)(from >> 24) + (u8)(to >> 24));
-                        if (b1 & 0xffffff00) state->Cpsr |= (1 << 16);
-                        if (b2 & 0xffffff00) state->Cpsr |= (1 << 17);
-                        if (b3 & 0xffffff00) state->Cpsr |= (1 << 18);
-                        if (b4 & 0xffffff00) state->Cpsr |= (1 << 19);
+
+                        if (b1 & 0xffffff00)
+                            state->Cpsr |= (1 << 16);
+                        else
+                            state->Cpsr &= ~(1 << 16);
+
+                        if (b2 & 0xffffff00)
+                            state->Cpsr |= (1 << 17);
+                        else
+                            state->Cpsr &= ~(1 << 17);
+
+                        if (b3 & 0xffffff00)
+                            state->Cpsr |= (1 << 18);
+                        else
+                            state->Cpsr &= ~(1 << 18);
+
+
+                        if (b4 & 0xffffff00)
+                            state->Cpsr |= (1 << 19);
+                        else
+                            state->Cpsr &= ~(1 << 19);
                     }
+
                     state->Reg[rd] = (u32)(b1 | (b2 & 0xff) << 8 | (b3 & 0xff) << 16 | (b4 & 0xff) << 24);
                     return 1;
                 }
@@ -6049,7 +6084,7 @@ L_stm_s_takeabort:
                                 break;
                         }
 
-                        Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFF);
+                        Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFF) | ((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFF) & 0xFF;
                         if (Rm & 0x80)
                                 Rm |= 0xffffff00;
 
@@ -6058,11 +6093,12 @@ L_stm_s_takeabort:
                                 state->Reg[BITS(12, 15)] = Rm;
                         else
                                 /* SXTAB */
-                                state->Reg[BITS(12, 15)] += Rm;
+                                state->Reg[BITS(12, 15)] = state->Reg[BITS(16, 19)] + Rm;
 
                         return 1;
                 }
-                case 0x6b: {
+                case 0x6b:
+                {
                         ARMword Rm;
                         int ror = -1;
 
@@ -6080,10 +6116,10 @@ L_stm_s_takeabort:
                                         ror = 24;
                                         break;
 
-                                case 0xf3:
+                                case 0xf3: // REV
                                         DEST = ((RHS & 0xFF) << 24) | ((RHS & 0xFF00)) << 8 | ((RHS & 0xFF0000) >> 8) | ((RHS & 0xFF000000) >> 24);
                                         return 1;
-                                case 0xfb:
+                                case 0xfb: // REV16
                                         DEST = ((RHS & 0xFF) << 8) | ((RHS & 0xFF00)) >> 8 | ((RHS & 0xFF0000) << 8) | ((RHS & 0xFF000000) >> 8);
                                         return 1;
                                 default:
@@ -6093,7 +6129,7 @@ L_stm_s_takeabort:
                         if (ror == -1)
                                 break;
 
-                        Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFFFF);
+                        Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFFFF) | ((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFFFF) & 0xFFFF;
                         if (Rm & 0x8000)
                                 Rm |= 0xffff0000;
 
@@ -6180,7 +6216,7 @@ L_stm_s_takeabort:
                                 break;
                         }
 
-                        Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFF);
+                        Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFF) | ((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFF) & 0xFF;
 
                         if (BITS(16, 19) == 0xf)
                                 /* UXTB */
@@ -6210,9 +6246,13 @@ L_stm_s_takeabort:
                                         ror = 24;
                                         break;
 
-                                case 0xfb:
-                                        printf("Unhandled v6 insn: revsh\n");
-                                        return 0;
+                                case 0xfb: // REVSH
+                                {
+                                        DEST = ((RHS & 0xFF) << 8) | ((RHS & 0xFF00) >> 8);
+                                        if (DEST & 0x8000)
+                                                DEST |= 0xffff0000;
+                                        return 1;
+                                }
                                 default:
                                         break;
                         }
@@ -6220,13 +6260,13 @@ L_stm_s_takeabort:
                         if (ror == -1)
                                 break;
 
-                        Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFFFF);
+                        Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFFFF) | ((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFFFF) & 0xFFFF;
 
                         /* UXT */
                         /* state->Reg[BITS (12, 15)] = Rm; */
                         /* dyf add */
                         if (BITS(16, 19) == 0xf) {
-                                state->Reg[BITS(12, 15)] = (Rm >> (8 * BITS(10, 11))) & 0x0000FFFF;
+                                state->Reg[BITS(12, 15)] = Rm;
                         }
                         else {
                                 /* UXTAH */
@@ -6234,7 +6274,7 @@ L_stm_s_takeabort:
                                 //            printf("rd is %x rn is %x rm is %x rotate is %x\n", state->Reg[BITS (12, 15)], state->Reg[BITS (16, 19)]
                                 //                   , Rm, BITS(10, 11));
                                 //            printf("icounter is %lld\n", state->NumInstrs);
-                                state->Reg[BITS(12, 15)] = (state->Reg[BITS(16, 19)] >> (8 * (BITS(10, 11)))) + Rm;
+                                state->Reg[BITS(12, 15)] = state->Reg[BITS(16, 19)] + Rm;
                                 //        printf("rd is %x\n", state->Reg[BITS (12, 15)]);
                                 //        exit(-1);
                         }
diff --git a/src/core/hle/kernel/shared_memory.h b/src/core/hle/kernel/shared_memory.h
index 304cf5b67..bb778ec26 100644
--- a/src/core/hle/kernel/shared_memory.h
+++ b/src/core/hle/kernel/shared_memory.h
@@ -12,11 +12,15 @@ namespace Kernel {
 
 /// Permissions for mapped shared memory blocks
 enum class MemoryPermission : u32 {
-    None        = 0,
-    Read        = (1u <<  0),
-    Write       = (1u <<  1),
-    ReadWrite   = (Read | Write),
-    DontCare    = (1u << 28)
+    None             = 0,
+    Read             = (1u <<  0),
+    Write            = (1u <<  1),
+    ReadWrite        = (Read | Write),
+    Execute          = (1u <<  2),
+    ReadExecute      = (Read | Execute),
+    WriteExecute     = (Write | Execute),
+    ReadWriteExecute = (Read | Write | Execute),
+    DontCare         = (1u << 28)
 };
 
 /**
diff --git a/src/core/hle/svc.cpp b/src/core/hle/svc.cpp
index 15cc240f4..47e9bf77e 100644
--- a/src/core/hle/svc.cpp
+++ b/src/core/hle/svc.cpp
@@ -64,6 +64,10 @@ static Result MapMemoryBlock(Handle handle, u32 addr, u32 permissions, u32 other
     case Kernel::MemoryPermission::Read:
     case Kernel::MemoryPermission::Write:
     case Kernel::MemoryPermission::ReadWrite:
+    case Kernel::MemoryPermission::Execute:
+    case Kernel::MemoryPermission::ReadExecute:
+    case Kernel::MemoryPermission::WriteExecute:
+    case Kernel::MemoryPermission::ReadWriteExecute:
     case Kernel::MemoryPermission::DontCare:
         Kernel::MapSharedMemory(handle, addr, permissions_type,
             static_cast<Kernel::MemoryPermission>(other_permissions));