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-rw-r--r--src/video_core/engines/maxwell_3d.cpp6
-rw-r--r--src/video_core/engines/maxwell_3d.h4
2 files changed, 5 insertions, 5 deletions
diff --git a/src/video_core/engines/maxwell_3d.cpp b/src/video_core/engines/maxwell_3d.cpp
index bc40f8d98..4306b894f 100644
--- a/src/video_core/engines/maxwell_3d.cpp
+++ b/src/video_core/engines/maxwell_3d.cpp
@@ -33,9 +33,6 @@ void Maxwell3D::CallMacroMethod(u32 method, std::vector<u32> parameters) {
33} 33}
34 34
35void Maxwell3D::WriteReg(u32 method, u32 value, u32 remaining_params) { 35void Maxwell3D::WriteReg(u32 method, u32 value, u32 remaining_params) {
36 ASSERT_MSG(method < Regs::NUM_REGS,
37 "Invalid Maxwell3D register, increase the size of the Regs structure");
38
39 auto debug_context = Core::System::GetInstance().GetGPUDebugContext(); 36 auto debug_context = Core::System::GetInstance().GetGPUDebugContext();
40 37
41 // It is an error to write to a register other than the current macro's ARG register before it 38 // It is an error to write to a register other than the current macro's ARG register before it
@@ -64,6 +61,9 @@ void Maxwell3D::WriteReg(u32 method, u32 value, u32 remaining_params) {
64 return; 61 return;
65 } 62 }
66 63
64 ASSERT_MSG(method < Regs::NUM_REGS,
65 "Invalid Maxwell3D register, increase the size of the Regs structure");
66
67 if (debug_context) { 67 if (debug_context) {
68 debug_context->OnEvent(Tegra::DebugContext::Event::MaxwellCommandLoaded, nullptr); 68 debug_context->OnEvent(Tegra::DebugContext::Event::MaxwellCommandLoaded, nullptr);
69 } 69 }
diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h
index 8edc3cd38..5cf62fb01 100644
--- a/src/video_core/engines/maxwell_3d.h
+++ b/src/video_core/engines/maxwell_3d.h
@@ -31,7 +31,7 @@ public:
31 /// Register structure of the Maxwell3D engine. 31 /// Register structure of the Maxwell3D engine.
32 /// TODO(Subv): This structure will need to be made bigger as more registers are discovered. 32 /// TODO(Subv): This structure will need to be made bigger as more registers are discovered.
33 struct Regs { 33 struct Regs {
34 static constexpr size_t NUM_REGS = 0xE36; 34 static constexpr size_t NUM_REGS = 0xE00;
35 35
36 static constexpr size_t NumRenderTargets = 8; 36 static constexpr size_t NumRenderTargets = 8;
37 static constexpr size_t NumViewports = 16; 37 static constexpr size_t NumViewports = 16;
@@ -613,7 +613,7 @@ public:
613 u32 size[MaxShaderStage]; 613 u32 size[MaxShaderStage];
614 } tex_info_buffers; 614 } tex_info_buffers;
615 615
616 INSERT_PADDING_WORDS(0x102); 616 INSERT_PADDING_WORDS(0xCC);
617 }; 617 };
618 std::array<u32, NUM_REGS> reg_array; 618 std::array<u32, NUM_REGS> reg_array;
619 }; 619 };