diff options
| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom_dec.h | 45 |
1 files changed, 2 insertions, 43 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_dec.h b/src/core/arm/dyncom/arm_dyncom_dec.h index 58784aeea..ee8ff5992 100644 --- a/src/core/arm/dyncom/arm_dyncom_dec.h +++ b/src/core/arm/dyncom/arm_dyncom_dec.h | |||
| @@ -6,14 +6,6 @@ | |||
| 6 | 6 | ||
| 7 | #define BITS(a,b) ((instr >> (a)) & ((1 << (1+(b)-(a)))-1)) | 7 | #define BITS(a,b) ((instr >> (a)) & ((1 << (1+(b)-(a)))-1)) |
| 8 | #define BIT(n) ((instr >> (n)) & 1) | 8 | #define BIT(n) ((instr >> (n)) & 1) |
| 9 | #define BAD do { printf("meet BAD at %s, instr is %x\n", __FUNCTION__, instr ); } while(0); | ||
| 10 | #define ptr_N cpu->ptr_N | ||
| 11 | #define ptr_Z cpu->ptr_Z | ||
| 12 | #define ptr_C cpu->ptr_C | ||
| 13 | #define ptr_V cpu->ptr_V | ||
| 14 | #define ptr_I cpu->ptr_I | ||
| 15 | #define ptr_T cpu->ptr_T | ||
| 16 | #define ptr_CPSR cpu->ptr_gpr[16] | ||
| 17 | 9 | ||
| 18 | // For MUL instructions | 10 | // For MUL instructions |
| 19 | #define RDHi ((instr >> 16) & 0xF) | 11 | #define RDHi ((instr >> 16) & 0xF) |
| @@ -49,24 +41,6 @@ | |||
| 49 | #define SBIT BIT(20) | 41 | #define SBIT BIT(20) |
| 50 | #define DESTReg (BITS (12, 15)) | 42 | #define DESTReg (BITS (12, 15)) |
| 51 | 43 | ||
| 52 | // They are in unused state, give a corrent value when using | ||
| 53 | #define IS_V5E 0 | ||
| 54 | #define IS_V5 0 | ||
| 55 | #define IS_V6 0 | ||
| 56 | #define LHSReg 0 | ||
| 57 | |||
| 58 | // Temp define the using the pc reg need implement a flow | ||
| 59 | #define STORE_CHECK_RD_PC ADD(R(RD), CONST(INSTR_SIZE * 2)) | ||
| 60 | |||
| 61 | #define OPERAND operand(cpu,instr,bb,NULL) | ||
| 62 | #define SCO_OPERAND(sco) operand(cpu,instr,bb,sco) | ||
| 63 | #define BOPERAND boperand(instr) | ||
| 64 | |||
| 65 | #define CHECK_RN_PC (RN == 15 ? ADD(AND(R(RN), CONST(~0x1)), CONST(INSTR_SIZE * 2)) : R(RN)) | ||
| 66 | #define CHECK_RN_PC_WA (RN == 15 ? ADD(AND(R(RN), CONST(~0x3)), CONST(INSTR_SIZE * 2)) : R(RN)) | ||
| 67 | |||
| 68 | #define GET_USER_MODE() (OR(ICMP_EQ(R(MODE_REG), CONST(USER32MODE)), ICMP_EQ(R(MODE_REG), CONST(SYSTEM32MODE)))) | ||
| 69 | |||
| 70 | int decode_arm_instr(uint32_t instr, int32_t *idx); | 44 | int decode_arm_instr(uint32_t instr, int32_t *idx); |
| 71 | 45 | ||
| 72 | enum DECODE_STATUS { | 46 | enum DECODE_STATUS { |
| @@ -83,23 +57,8 @@ struct instruction_set_encoding_item { | |||
| 83 | 57 | ||
| 84 | typedef struct instruction_set_encoding_item ISEITEM; | 58 | typedef struct instruction_set_encoding_item ISEITEM; |
| 85 | 59 | ||
| 86 | #define RECORD_WB(value, flag) { cpu->dyncom_engine->wb_value = value;cpu->dyncom_engine->wb_flag = flag; } | 60 | // ARM versions |
| 87 | #define INIT_WB(wb_value, wb_flag) RECORD_WB(wb_value, wb_flag) | 61 | enum { |
| 88 | |||
| 89 | #define EXECUTE_WB(base_reg) { if(cpu->dyncom_engine->wb_flag) LET(base_reg, cpu->dyncom_engine->wb_value); } | ||
| 90 | |||
| 91 | inline int get_reg_count(uint32_t instr) { | ||
| 92 | int i = BITS(0, 15); | ||
| 93 | int count = 0; | ||
| 94 | while (i) { | ||
| 95 | if (i & 1) | ||
| 96 | count++; | ||
| 97 | i = i >> 1; | ||
| 98 | } | ||
| 99 | return count; | ||
| 100 | } | ||
| 101 | |||
| 102 | enum ARMVER { | ||
| 103 | INVALID = 0, | 62 | INVALID = 0, |
| 104 | ARMALL, | 63 | ARMALL, |
| 105 | ARMV4, | 64 | ARMV4, |