diff options
| -rw-r--r-- | src/core/arm/arm_interface.h | 3 | ||||
| -rw-r--r-- | src/core/arm/dynarmic/arm_dynarmic_32.cpp | 4 | ||||
| -rw-r--r-- | src/core/arm/dynarmic/arm_dynarmic_32.h | 1 | ||||
| -rw-r--r-- | src/core/arm/dynarmic/arm_dynarmic_64.cpp | 4 | ||||
| -rw-r--r-- | src/core/arm/dynarmic/arm_dynarmic_64.h | 1 | ||||
| -rw-r--r-- | src/core/core.cpp | 4 | ||||
| -rw-r--r-- | src/core/core.h | 3 |
7 files changed, 0 insertions, 20 deletions
diff --git a/src/core/arm/arm_interface.h b/src/core/arm/arm_interface.h index bcec4b3b8..8ce973a77 100644 --- a/src/core/arm/arm_interface.h +++ b/src/core/arm/arm_interface.h | |||
| @@ -174,9 +174,6 @@ public: | |||
| 174 | /// Clears the exclusive monitor's state. | 174 | /// Clears the exclusive monitor's state. |
| 175 | virtual void ClearExclusiveState() = 0; | 175 | virtual void ClearExclusiveState() = 0; |
| 176 | 176 | ||
| 177 | /// Prepare core for thread reschedule (if needed to correctly handle state) | ||
| 178 | virtual void PrepareReschedule() = 0; | ||
| 179 | |||
| 180 | /// Signal an interrupt and ask the core to halt as soon as possible. | 177 | /// Signal an interrupt and ask the core to halt as soon as possible. |
| 181 | virtual void SignalInterrupt() = 0; | 178 | virtual void SignalInterrupt() = 0; |
| 182 | 179 | ||
diff --git a/src/core/arm/dynarmic/arm_dynarmic_32.cpp b/src/core/arm/dynarmic/arm_dynarmic_32.cpp index 60e9edff2..781a77f6f 100644 --- a/src/core/arm/dynarmic/arm_dynarmic_32.cpp +++ b/src/core/arm/dynarmic/arm_dynarmic_32.cpp | |||
| @@ -327,10 +327,6 @@ void ARM_Dynarmic_32::LoadContext(const ThreadContext32& ctx) { | |||
| 327 | jit.load()->LoadContext(context); | 327 | jit.load()->LoadContext(context); |
| 328 | } | 328 | } |
| 329 | 329 | ||
| 330 | void ARM_Dynarmic_32::PrepareReschedule() { | ||
| 331 | jit.load()->HaltExecution(break_loop); | ||
| 332 | } | ||
| 333 | |||
| 334 | void ARM_Dynarmic_32::SignalInterrupt() { | 330 | void ARM_Dynarmic_32::SignalInterrupt() { |
| 335 | jit.load()->HaltExecution(break_loop); | 331 | jit.load()->HaltExecution(break_loop); |
| 336 | } | 332 | } |
diff --git a/src/core/arm/dynarmic/arm_dynarmic_32.h b/src/core/arm/dynarmic/arm_dynarmic_32.h index a25c9d277..abfe76644 100644 --- a/src/core/arm/dynarmic/arm_dynarmic_32.h +++ b/src/core/arm/dynarmic/arm_dynarmic_32.h | |||
| @@ -57,7 +57,6 @@ public: | |||
| 57 | void LoadContext(const ThreadContext32& ctx) override; | 57 | void LoadContext(const ThreadContext32& ctx) override; |
| 58 | void LoadContext(const ThreadContext64& ctx) override {} | 58 | void LoadContext(const ThreadContext64& ctx) override {} |
| 59 | 59 | ||
| 60 | void PrepareReschedule() override; | ||
| 61 | void SignalInterrupt() override; | 60 | void SignalInterrupt() override; |
| 62 | void ClearExclusiveState() override; | 61 | void ClearExclusiveState() override; |
| 63 | 62 | ||
diff --git a/src/core/arm/dynarmic/arm_dynarmic_64.cpp b/src/core/arm/dynarmic/arm_dynarmic_64.cpp index d8d3a38db..1b1334598 100644 --- a/src/core/arm/dynarmic/arm_dynarmic_64.cpp +++ b/src/core/arm/dynarmic/arm_dynarmic_64.cpp | |||
| @@ -395,10 +395,6 @@ void ARM_Dynarmic_64::LoadContext(const ThreadContext64& ctx) { | |||
| 395 | SetTPIDR_EL0(ctx.tpidr); | 395 | SetTPIDR_EL0(ctx.tpidr); |
| 396 | } | 396 | } |
| 397 | 397 | ||
| 398 | void ARM_Dynarmic_64::PrepareReschedule() { | ||
| 399 | jit.load()->HaltExecution(break_loop); | ||
| 400 | } | ||
| 401 | |||
| 402 | void ARM_Dynarmic_64::SignalInterrupt() { | 398 | void ARM_Dynarmic_64::SignalInterrupt() { |
| 403 | jit.load()->HaltExecution(break_loop); | 399 | jit.load()->HaltExecution(break_loop); |
| 404 | } | 400 | } |
diff --git a/src/core/arm/dynarmic/arm_dynarmic_64.h b/src/core/arm/dynarmic/arm_dynarmic_64.h index 9680c7b99..01a7e4dad 100644 --- a/src/core/arm/dynarmic/arm_dynarmic_64.h +++ b/src/core/arm/dynarmic/arm_dynarmic_64.h | |||
| @@ -51,7 +51,6 @@ public: | |||
| 51 | void LoadContext(const ThreadContext32& ctx) override {} | 51 | void LoadContext(const ThreadContext32& ctx) override {} |
| 52 | void LoadContext(const ThreadContext64& ctx) override; | 52 | void LoadContext(const ThreadContext64& ctx) override; |
| 53 | 53 | ||
| 54 | void PrepareReschedule() override; | ||
| 55 | void SignalInterrupt() override; | 54 | void SignalInterrupt() override; |
| 56 | void ClearExclusiveState() override; | 55 | void ClearExclusiveState() override; |
| 57 | 56 | ||
diff --git a/src/core/core.cpp b/src/core/core.cpp index b5e2bcae2..8a887904d 100644 --- a/src/core/core.cpp +++ b/src/core/core.cpp | |||
| @@ -505,10 +505,6 @@ bool System::IsPoweredOn() const { | |||
| 505 | return impl->is_powered_on.load(std::memory_order::relaxed); | 505 | return impl->is_powered_on.load(std::memory_order::relaxed); |
| 506 | } | 506 | } |
| 507 | 507 | ||
| 508 | void System::PrepareReschedule() { | ||
| 509 | // Deprecated, does nothing, kept for backward compatibility. | ||
| 510 | } | ||
| 511 | |||
| 512 | void System::PrepareReschedule(const u32 core_index) { | 508 | void System::PrepareReschedule(const u32 core_index) { |
| 513 | impl->kernel.PrepareReschedule(core_index); | 509 | impl->kernel.PrepareReschedule(core_index); |
| 514 | } | 510 | } |
diff --git a/src/core/core.h b/src/core/core.h index 52ff90359..4a0c7dc84 100644 --- a/src/core/core.h +++ b/src/core/core.h | |||
| @@ -194,9 +194,6 @@ public: | |||
| 194 | [[nodiscard]] const Core::TelemetrySession& TelemetrySession() const; | 194 | [[nodiscard]] const Core::TelemetrySession& TelemetrySession() const; |
| 195 | 195 | ||
| 196 | /// Prepare the core emulation for a reschedule | 196 | /// Prepare the core emulation for a reschedule |
| 197 | void PrepareReschedule(); | ||
| 198 | |||
| 199 | /// Prepare the core emulation for a reschedule | ||
| 200 | void PrepareReschedule(u32 core_index); | 197 | void PrepareReschedule(u32 core_index); |
| 201 | 198 | ||
| 202 | /// Gets and resets core performance statistics | 199 | /// Gets and resets core performance statistics |