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-rw-r--r--src/core/arm/dyncom/arm_dyncom_dec.cpp6
-rw-r--r--src/core/arm/dyncom/arm_dyncom_dec.h6
2 files changed, 5 insertions, 7 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_dec.cpp b/src/core/arm/dyncom/arm_dyncom_dec.cpp
index 48fc1c683..ee4288314 100644
--- a/src/core/arm/dyncom/arm_dyncom_dec.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_dec.cpp
@@ -5,7 +5,7 @@
5#include "core/arm/dyncom/arm_dyncom_dec.h" 5#include "core/arm/dyncom/arm_dyncom_dec.h"
6#include "core/arm/skyeye_common/armsupp.h" 6#include "core/arm/skyeye_common/armsupp.h"
7 7
8const ISEITEM arm_instruction[] = { 8const InstructionSetEncodingItem arm_instruction[] = {
9 { "vmla", 4, ARMVFP2, { 23, 27, 0x1C, 20, 21, 0x0, 9, 11, 0x5, 4, 4, 0 }}, 9 { "vmla", 4, ARMVFP2, { 23, 27, 0x1C, 20, 21, 0x0, 9, 11, 0x5, 4, 4, 0 }},
10 { "vmls", 7, ARMVFP2, { 28, 31, 0xF, 25, 27, 0x1, 23, 23, 1, 11, 11, 0, 8, 9, 0x2, 6, 6, 1, 4, 4, 0 }}, 10 { "vmls", 7, ARMVFP2, { 28, 31, 0xF, 25, 27, 0x1, 23, 23, 1, 11, 11, 0, 8, 9, 0x2, 6, 6, 1, 4, 4, 0 }},
11 { "vnmla", 4, ARMVFP2, { 23, 27, 0x1C, 20, 21, 0x1, 9, 11, 0x5, 4, 4, 0 }}, 11 { "vnmla", 4, ARMVFP2, { 23, 27, 0x1C, 20, 21, 0x1, 9, 11, 0x5, 4, 4, 0 }},
@@ -207,7 +207,7 @@ const ISEITEM arm_instruction[] = {
207 { "bbl", 1, 0, { 25, 27, 0x00000005 }}, 207 { "bbl", 1, 0, { 25, 27, 0x00000005 }},
208}; 208};
209 209
210const ISEITEM arm_exclusion_code[] = { 210const InstructionSetEncodingItem arm_exclusion_code[] = {
211 { "vmla", 0, ARMVFP2, { 0 }}, 211 { "vmla", 0, ARMVFP2, { 0 }},
212 { "vmls", 0, ARMVFP2, { 0 }}, 212 { "vmls", 0, ARMVFP2, { 0 }},
213 { "vnmla", 0, ARMVFP2, { 0 }}, 213 { "vnmla", 0, ARMVFP2, { 0 }},
@@ -417,7 +417,7 @@ const ISEITEM arm_exclusion_code[] = {
417ARMDecodeStatus DecodeARMInstruction(u32 instr, s32* idx) { 417ARMDecodeStatus DecodeARMInstruction(u32 instr, s32* idx) {
418 int n = 0; 418 int n = 0;
419 int base = 0; 419 int base = 0;
420 int instr_slots = sizeof(arm_instruction) / sizeof(ISEITEM); 420 int instr_slots = sizeof(arm_instruction) / sizeof(InstructionSetEncodingItem);
421 ARMDecodeStatus ret = ARMDecodeStatus::FAILURE; 421 ARMDecodeStatus ret = ARMDecodeStatus::FAILURE;
422 422
423 for (int i = 0; i < instr_slots; i++) { 423 for (int i = 0; i < instr_slots; i++) {
diff --git a/src/core/arm/dyncom/arm_dyncom_dec.h b/src/core/arm/dyncom/arm_dyncom_dec.h
index 80d910218..d7170e0fc 100644
--- a/src/core/arm/dyncom/arm_dyncom_dec.h
+++ b/src/core/arm/dyncom/arm_dyncom_dec.h
@@ -13,15 +13,13 @@ enum class ARMDecodeStatus {
13 13
14ARMDecodeStatus DecodeARMInstruction(u32 instr, s32* idx); 14ARMDecodeStatus DecodeARMInstruction(u32 instr, s32* idx);
15 15
16struct instruction_set_encoding_item { 16struct InstructionSetEncodingItem {
17 const char *name; 17 const char *name;
18 int attribute_value; 18 int attribute_value;
19 int version; 19 int version;
20 u32 content[21]; 20 u32 content[21];
21}; 21};
22 22
23typedef struct instruction_set_encoding_item ISEITEM;
24
25// ARM versions 23// ARM versions
26enum { 24enum {
27 INVALID = 0, 25 INVALID = 0,
@@ -38,4 +36,4 @@ enum {
38 ARMV6K, 36 ARMV6K,
39}; 37};
40 38
41extern const ISEITEM arm_instruction[]; 39extern const InstructionSetEncodingItem arm_instruction[];