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-rw-r--r--src/core/arm/interpreter/arm_interpreter.cpp6
-rw-r--r--src/core/arm/interpreter/armdefs.h5
-rw-r--r--src/core/arm/interpreter/armemu.cpp9218
-rw-r--r--src/core/arm/interpreter/armemu.h29
-rw-r--r--src/core/arm/interpreter/arminit.cpp744
-rw-r--r--src/core/arm/interpreter/armsupp.cpp1220
6 files changed, 5303 insertions, 5919 deletions
diff --git a/src/core/arm/interpreter/arm_interpreter.cpp b/src/core/arm/interpreter/arm_interpreter.cpp
index 0e893f182..d35a3ae17 100644
--- a/src/core/arm/interpreter/arm_interpreter.cpp
+++ b/src/core/arm/interpreter/arm_interpreter.cpp
@@ -12,6 +12,8 @@ ARM_Interpreter::ARM_Interpreter() {
12 state = new ARMul_State; 12 state = new ARMul_State;
13 13
14 ARMul_EmulateInit(); 14 ARMul_EmulateInit();
15 memset(state, 0, sizeof(ARMul_State));
16
15 ARMul_NewState(state); 17 ARMul_NewState(state);
16 18
17 state->abort_model = 0; 19 state->abort_model = 0;
@@ -23,12 +25,14 @@ ARM_Interpreter::ARM_Interpreter() {
23 mmu_init(state); 25 mmu_init(state);
24 26
25 // Reset the core to initial state 27 // Reset the core to initial state
28 ARMul_CoProInit(state);
26 ARMul_Reset(state); 29 ARMul_Reset(state);
27 state->NextInstr = 0; 30 state->NextInstr = RESUME;
28 state->Emulate = 3; 31 state->Emulate = 3;
29 32
30 state->pc = state->Reg[15] = 0x00000000; 33 state->pc = state->Reg[15] = 0x00000000;
31 state->Reg[13] = 0x10000000; // Set stack pointer to the top of the stack 34 state->Reg[13] = 0x10000000; // Set stack pointer to the top of the stack
35 state->servaddr = 0xFFFF0000;
32} 36}
33 37
34ARM_Interpreter::~ARM_Interpreter() { 38ARM_Interpreter::~ARM_Interpreter() {
diff --git a/src/core/arm/interpreter/armdefs.h b/src/core/arm/interpreter/armdefs.h
index 1ff560fe7..dd5983be3 100644
--- a/src/core/arm/interpreter/armdefs.h
+++ b/src/core/arm/interpreter/armdefs.h
@@ -278,6 +278,11 @@ struct ARMul_State
278 unsigned int NumScycles, NumNcycles, NumIcycles, NumCcycles, NumFcycles; /* emulated cycles used */ 278 unsigned int NumScycles, NumNcycles, NumIcycles, NumCcycles, NumFcycles; /* emulated cycles used */
279 unsigned long long NumInstrs; /* the number of instructions executed */ 279 unsigned long long NumInstrs; /* the number of instructions executed */
280 unsigned NumInstrsToExecute; 280 unsigned NumInstrsToExecute;
281
282 ARMword currentexaddr;
283 ARMword currentexval;
284 ARMword servaddr;
285
281 unsigned NextInstr; 286 unsigned NextInstr;
282 unsigned VectorCatch; /* caught exception mask */ 287 unsigned VectorCatch; /* caught exception mask */
283 unsigned CallDebug; /* set to call the debugger */ 288 unsigned CallDebug; /* set to call the debugger */
diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp
index f3c14e608..f9130ef88 100644
--- a/src/core/arm/interpreter/armemu.cpp
+++ b/src/core/arm/interpreter/armemu.cpp
@@ -1,29 +1,35 @@
1/* armemu.c -- Main instruction emulation: ARM7 Instruction Emulator. 1/* armemu.c -- Main instruction emulation: ARM7 Instruction Emulator.
2 Copyright (C) 1994 Advanced RISC Machines Ltd. 2 Copyright (C) 1994 Advanced RISC Machines Ltd.
3 Modifications to add arch. v4 support by <jsmith@cygnus.com>. 3 Modifications to add arch. v4 support by <jsmith@cygnus.com>.
4 4
5 This program is free software; you can redistribute it and/or modify 5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by 6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or 7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version. 8 (at your option) any later version.
9 9
10 This program is distributed in the hope that it will be useful, 10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of 11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details. 13 GNU General Public License for more details.
14 14
15 You should have received a copy of the GNU General Public License 15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software 16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
18 18
19#include "core/hle/hle.h" 19//#include <util.h> // DEBUG()
20 20
21#include "arm_regformat.h" 21#include "arm_regformat.h"
22#include "armdefs.h" 22#include "armdefs.h"
23#include "armemu.h" 23#include "armemu.h"
24#include "armos.h" 24#include "core/hle/hle.h"
25 25
26#define ARMul_Debug(x,y,z) 0 // Disabling this /bunnei 26//#include "svc.h"
27
28//ichfly
29//#define callstacker 1
30
31
32//#include "armos.h"
27 33
28//#include "skyeye_callback.h" 34//#include "skyeye_callback.h"
29//#include "skyeye_bus.h" 35//#include "skyeye_bus.h"
@@ -59,6 +65,7 @@ static unsigned Multiply64 (ARMul_State *, ARMword, int, int);
59static unsigned MultiplyAdd64 (ARMul_State *, ARMword, int, int); 65static unsigned MultiplyAdd64 (ARMul_State *, ARMword, int, int);
60static void Handle_Load_Double (ARMul_State *, ARMword); 66static void Handle_Load_Double (ARMul_State *, ARMword);
61static void Handle_Store_Double (ARMul_State *, ARMword); 67static void Handle_Store_Double (ARMul_State *, ARMword);
68
62void 69void
63XScale_set_fsr_far (ARMul_State * state, ARMword fsr, ARMword _far); 70XScale_set_fsr_far (ARMul_State * state, ARMword fsr, ARMword _far);
64int 71int
@@ -69,10 +76,10 @@ unsigned xscale_cp15_cp_access_allowed (ARMul_State * state, unsigned reg,
69static int 76static int
70handle_v6_insn (ARMul_State * state, ARMword instr); 77handle_v6_insn (ARMul_State * state, ARMword instr);
71 78
72#define LUNSIGNED (0) /* unsigned operation */ 79#define LUNSIGNED (0) /* unsigned operation */
73#define LSIGNED (1) /* signed operation */ 80#define LSIGNED (1) /* signed operation */
74#define LDEFAULT (0) /* default : do nothing */ 81#define LDEFAULT (0) /* default : do nothing */
75#define LSCC (1) /* set condition codes on result */ 82#define LSCC (1) /* set condition codes on result */
76 83
77#ifdef NEED_UI_LOOP_HOOK 84#ifdef NEED_UI_LOOP_HOOK
78/* How often to run the ui_loop update, when in use. */ 85/* How often to run the ui_loop update, when in use. */
@@ -122,175 +129,175 @@ extern int (*ui_loop_hook) (int);
122/* Load post decrement writeback. */ 129/* Load post decrement writeback. */
123#define LHPOSTDOWN() \ 130#define LHPOSTDOWN() \
124{ \ 131{ \
125 int done = 1; \ 132 int done = 1; \
126 lhs = LHS; \ 133 lhs = LHS; \
127 temp = lhs - GetLS7RHS (state, instr); \ 134 temp = lhs - GetLS7RHS (state, instr); \
128 \ 135 \
129 switch (BITS (5, 6)) \ 136 switch (BITS (5, 6)) \
130 { \ 137 { \
131 case 1: /* H */ \ 138 case 1: /* H */ \
132 if (LoadHalfWord (state, instr, lhs, LUNSIGNED)) \ 139 if (LoadHalfWord (state, instr, lhs, LUNSIGNED)) \
133 LSBase = temp; \ 140 LSBase = temp; \
134 break; \ 141 break; \
135 case 2: /* SB */ \ 142 case 2: /* SB */ \
136 if (LoadByte (state, instr, lhs, LSIGNED)) \ 143 if (LoadByte (state, instr, lhs, LSIGNED)) \
137 LSBase = temp; \ 144 LSBase = temp; \
138 break; \ 145 break; \
139 case 3: /* SH */ \ 146 case 3: /* SH */ \
140 if (LoadHalfWord (state, instr, lhs, LSIGNED)) \ 147 if (LoadHalfWord (state, instr, lhs, LSIGNED)) \
141 LSBase = temp; \ 148 LSBase = temp; \
142 break; \ 149 break; \
143 case 0: /* SWP handled elsewhere. */ \ 150 case 0: /* SWP handled elsewhere. */ \
144 default: \ 151 default: \
145 done = 0; \ 152 done = 0; \
146 break; \ 153 break; \
147 } \ 154 } \
148 if (done) \ 155 if (done) \
149 break; \ 156 break; \
150} 157}
151 158
152/* Load post increment writeback. */ 159/* Load post increment writeback. */
153#define LHPOSTUP() \ 160#define LHPOSTUP() \
154{ \ 161{ \
155 int done = 1; \ 162 int done = 1; \
156 lhs = LHS; \ 163 lhs = LHS; \
157 temp = lhs + GetLS7RHS (state, instr); \ 164 temp = lhs + GetLS7RHS (state, instr); \
158 \ 165 \
159 switch (BITS (5, 6)) \ 166 switch (BITS (5, 6)) \
160 { \ 167 { \
161 case 1: /* H */ \ 168 case 1: /* H */ \
162 if (LoadHalfWord (state, instr, lhs, LUNSIGNED)) \ 169 if (LoadHalfWord (state, instr, lhs, LUNSIGNED)) \
163 LSBase = temp; \ 170 LSBase = temp; \
164 break; \ 171 break; \
165 case 2: /* SB */ \ 172 case 2: /* SB */ \
166 if (LoadByte (state, instr, lhs, LSIGNED)) \ 173 if (LoadByte (state, instr, lhs, LSIGNED)) \
167 LSBase = temp; \ 174 LSBase = temp; \
168 break; \ 175 break; \
169 case 3: /* SH */ \ 176 case 3: /* SH */ \
170 if (LoadHalfWord (state, instr, lhs, LSIGNED)) \ 177 if (LoadHalfWord (state, instr, lhs, LSIGNED)) \
171 LSBase = temp; \ 178 LSBase = temp; \
172 break; \ 179 break; \
173 case 0: /* SWP handled elsewhere. */ \ 180 case 0: /* SWP handled elsewhere. */ \
174 default: \ 181 default: \
175 done = 0; \ 182 done = 0; \
176 break; \ 183 break; \
177 } \ 184 } \
178 if (done) \ 185 if (done) \
179 break; \ 186 break; \
180} 187}
181 188
182/* Load pre decrement. */ 189/* Load pre decrement. */
183#define LHPREDOWN() \ 190#define LHPREDOWN() \
184{ \ 191{ \
185 int done = 1; \ 192 int done = 1; \
186 \ 193 \
187 temp = LHS - GetLS7RHS (state, instr); \ 194 temp = LHS - GetLS7RHS (state, instr); \
188 switch (BITS (5, 6)) \ 195 switch (BITS (5, 6)) \
189 { \ 196 { \
190 case 1: /* H */ \ 197 case 1: /* H */ \
191 (void) LoadHalfWord (state, instr, temp, LUNSIGNED); \ 198 (void) LoadHalfWord (state, instr, temp, LUNSIGNED); \
192 break; \ 199 break; \
193 case 2: /* SB */ \ 200 case 2: /* SB */ \
194 (void) LoadByte (state, instr, temp, LSIGNED); \ 201 (void) LoadByte (state, instr, temp, LSIGNED); \
195 break; \ 202 break; \
196 case 3: /* SH */ \ 203 case 3: /* SH */ \
197 (void) LoadHalfWord (state, instr, temp, LSIGNED); \ 204 (void) LoadHalfWord (state, instr, temp, LSIGNED); \
198 break; \ 205 break; \
199 case 0: \ 206 case 0: \
200 /* SWP handled elsewhere. */ \ 207 /* SWP handled elsewhere. */ \
201 default: \ 208 default: \
202 done = 0; \ 209 done = 0; \
203 break; \ 210 break; \
204 } \ 211 } \
205 if (done) \ 212 if (done) \
206 break; \ 213 break; \
207} 214}
208 215
209/* Load pre decrement writeback. */ 216/* Load pre decrement writeback. */
210#define LHPREDOWNWB() \ 217#define LHPREDOWNWB() \
211{ \ 218{ \
212 int done = 1; \ 219 int done = 1; \
213 \ 220 \
214 temp = LHS - GetLS7RHS (state, instr); \ 221 temp = LHS - GetLS7RHS (state, instr); \
215 switch (BITS (5, 6)) \ 222 switch (BITS (5, 6)) \
216 { \ 223 { \
217 case 1: /* H */ \ 224 case 1: /* H */ \
218 if (LoadHalfWord (state, instr, temp, LUNSIGNED)) \ 225 if (LoadHalfWord (state, instr, temp, LUNSIGNED)) \
219 LSBase = temp; \ 226 LSBase = temp; \
220 break; \ 227 break; \
221 case 2: /* SB */ \ 228 case 2: /* SB */ \
222 if (LoadByte (state, instr, temp, LSIGNED)) \ 229 if (LoadByte (state, instr, temp, LSIGNED)) \
223 LSBase = temp; \ 230 LSBase = temp; \
224 break; \ 231 break; \
225 case 3: /* SH */ \ 232 case 3: /* SH */ \
226 if (LoadHalfWord (state, instr, temp, LSIGNED)) \ 233 if (LoadHalfWord (state, instr, temp, LSIGNED)) \
227 LSBase = temp; \ 234 LSBase = temp; \
228 break; \ 235 break; \
229 case 0: \ 236 case 0: \
230 /* SWP handled elsewhere. */ \ 237 /* SWP handled elsewhere. */ \
231 default: \ 238 default: \
232 done = 0; \ 239 done = 0; \
233 break; \ 240 break; \
234 } \ 241 } \
235 if (done) \ 242 if (done) \
236 break; \ 243 break; \
237} 244}
238 245
239/* Load pre increment. */ 246/* Load pre increment. */
240#define LHPREUP() \ 247#define LHPREUP() \
241{ \ 248{ \
242 int done = 1; \ 249 int done = 1; \
243 \ 250 \
244 temp = LHS + GetLS7RHS (state, instr); \ 251 temp = LHS + GetLS7RHS (state, instr); \
245 switch (BITS (5, 6)) \ 252 switch (BITS (5, 6)) \
246 { \ 253 { \
247 case 1: /* H */ \ 254 case 1: /* H */ \
248 (void) LoadHalfWord (state, instr, temp, LUNSIGNED); \ 255 (void) LoadHalfWord (state, instr, temp, LUNSIGNED); \
249 break; \ 256 break; \
250 case 2: /* SB */ \ 257 case 2: /* SB */ \
251 (void) LoadByte (state, instr, temp, LSIGNED); \ 258 (void) LoadByte (state, instr, temp, LSIGNED); \
252 break; \ 259 break; \
253 case 3: /* SH */ \ 260 case 3: /* SH */ \
254 (void) LoadHalfWord (state, instr, temp, LSIGNED); \ 261 (void) LoadHalfWord (state, instr, temp, LSIGNED); \
255 break; \ 262 break; \
256 case 0: \ 263 case 0: \
257 /* SWP handled elsewhere. */ \ 264 /* SWP handled elsewhere. */ \
258 default: \ 265 default: \
259 done = 0; \ 266 done = 0; \
260 break; \ 267 break; \
261 } \ 268 } \
262 if (done) \ 269 if (done) \
263 break; \ 270 break; \
264} 271}
265 272
266/* Load pre increment writeback. */ 273/* Load pre increment writeback. */
267#define LHPREUPWB() \ 274#define LHPREUPWB() \
268{ \ 275{ \
269 int done = 1; \ 276 int done = 1; \
270 \ 277 \
271 temp = LHS + GetLS7RHS (state, instr); \ 278 temp = LHS + GetLS7RHS (state, instr); \
272 switch (BITS (5, 6)) \ 279 switch (BITS (5, 6)) \
273 { \ 280 { \
274 case 1: /* H */ \ 281 case 1: /* H */ \
275 if (LoadHalfWord (state, instr, temp, LUNSIGNED)) \ 282 if (LoadHalfWord (state, instr, temp, LUNSIGNED)) \
276 LSBase = temp; \ 283 LSBase = temp; \
277 break; \ 284 break; \
278 case 2: /* SB */ \ 285 case 2: /* SB */ \
279 if (LoadByte (state, instr, temp, LSIGNED)) \ 286 if (LoadByte (state, instr, temp, LSIGNED)) \
280 LSBase = temp; \ 287 LSBase = temp; \
281 break; \ 288 break; \
282 case 3: /* SH */ \ 289 case 3: /* SH */ \
283 if (LoadHalfWord (state, instr, temp, LSIGNED)) \ 290 if (LoadHalfWord (state, instr, temp, LSIGNED)) \
284 LSBase = temp; \ 291 LSBase = temp; \
285 break; \ 292 break; \
286 case 0: \ 293 case 0: \
287 /* SWP handled elsewhere. */ \ 294 /* SWP handled elsewhere. */ \
288 default: \ 295 default: \
289 done = 0; \ 296 done = 0; \
290 break; \ 297 break; \
291 } \ 298 } \
292 if (done) \ 299 if (done) \
293 break; \ 300 break; \
294} 301}
295 302
296/*ywc 2005-03-31*/ 303/*ywc 2005-03-31*/
@@ -306,60 +313,62 @@ unsigned int mirror_register_file[39];
306 313
307/* EMULATION of ARM6. */ 314/* EMULATION of ARM6. */
308 315
309/* The PC pipeline value depends on whether ARM
310 or Thumb instructions are being executed. */
311ARMword isize;
312
313extern int debugmode; 316extern int debugmode;
314int ARMul_ICE_debug(ARMul_State *state,ARMword instr,ARMword addr); 317int ARMul_ICE_debug(ARMul_State *state,ARMword instr,ARMword addr);
315#ifdef MODE32 318#ifdef MODE32
316//chy 2006-04-12, for ICE debug 319//chy 2006-04-12, for ICE debug
317int ARMul_ICE_debug(ARMul_State *state,ARMword instr,ARMword addr) 320int ARMul_ICE_debug(ARMul_State *state,ARMword instr,ARMword addr)
318{ 321{
319 int i; 322 return 0;
320#if 0 323}
321 if (debugmode) { 324
322 if (instr == ARMul_ABORTWORD) return 0; 325static int dump = 0;
323 for (i = 0; i < skyeye_ice.num_bps; i++) { 326ARMword ARMul_Debug(ARMul_State * state, ARMword pc, ARMword instr)
324 if (skyeye_ice.bps[i] == addr) { 327{
325 //for test 328 /*printf("[%08x] ", pc);
326 //printf("SKYEYE: ICE_debug bps [%d]== 0x%x\n", i,addr); 329 arm11_Disasm32(pc);*/
327 state->EndCondition = 0; 330
328 state->Emulate = STOP; 331 /*if (pc >= 0x0010303C && pc <= 0x00103050)
329 return 1;
330 }
331 }
332 if (skyeye_ice.tps_status==TRACE_STARTED)
333 { 332 {
334 for (i = 0; i < skyeye_ice.num_tps; i++) 333 printf("[%08x] = %08X = ", pc, instr);
335 { 334 arm11_Disasm32(pc);
336 if (((skyeye_ice.tps[i].tp_address==addr)&&(skyeye_ice.tps[i].status==TRACEPOINT_ENABLED))||(skyeye_ice.tps[i].status==TRACEPOINT_STEPPING)) 335 arm11_Dump();
337 { 336 }*/
338 handle_tracepoint(i); 337
339 } 338 //fprintf(stderr,"[%08x]\n", pc);
340 } 339
340 //if (pc == 0x00240C88)
341 // arm11_Dump();
342
343 /*if (pc == 0x188e04)
344 {
345 DEBUG("read %08X %08X %016X %08X %08X from %08X", state->Reg[0], state->Reg[1], state->Reg[2] | state->Reg[3] << 32, mem_Read32(state->Reg[13]), mem_Read32(state->Reg[13] + 4), state->Reg[14]);
341 } 346 }
342 } 347 if (pc == 0x21222c)
343 /* do profiling for code coverage */ 348 {
344 if (skyeye_config.code_cov.prof_on) 349 arm11_Dump();
345 cov_prof(EXEC_FLAG, addr); 350 mem_Dbugdump();
346#endif 351 }*/
347 /* chech if we need to run some callback functions at this time */ 352
348 //generic_arch_t* arch_instance = get_arch_instance(""); 353
349 //exec_callback(Step_callback, arch_instance); 354 /*if (pc == 0x0022D168)
350 //if (!SIM_is_running()) { 355 {
351 // if (instr == ARMul_ABORTWORD) return 0; 356 int j = 0;
352 // state->EndCondition = 0; 357 }*/
353 // state->Emulate = STOP; 358
354 // return 1; 359 /*if (state->Reg[4] == 0x00105734)
355 //} 360 {
361 printf("[%08x] ", pc);
362 arm11_Disasm32(pc);
363 }*/
364
356 return 0; 365 return 0;
357} 366}
358 367
359/* 368/*
360void chy_debug() 369void chy_debug()
361{ 370{
362 printf("SkyEye chy_deubeg begin\n"); 371 printf("SkyEye chy_deubeg begin\n");
363} 372}
364*/ 373*/
365ARMword 374ARMword
@@ -369,25 +378,32 @@ ARMword
369ARMul_Emulate26 (ARMul_State * state) 378ARMul_Emulate26 (ARMul_State * state)
370#endif 379#endif
371{ 380{
372 ARMword instr; /* The current instruction. */ 381 /* The PC pipeline value depends on whether ARM
373 ARMword dest = 0; /* Almost the DestBus. */ 382 or Thumb instructions are being
374 ARMword temp; /* Ubiquitous third hand. */ 383 d. */
375 ARMword pc = 0; /* The address of the current instruction. */ 384 ARMword isize;
376 ARMword lhs; /* Almost the ABus and BBus. */ 385 ARMword instr; /* The current instruction. */
386 ARMword dest = 0; /* Almost the DestBus. */
387 ARMword temp; /* Ubiquitous third hand. */
388 ARMword pc = 0; /* The address of the current instruction. */
389 ARMword lhs; /* Almost the ABus and BBus. */
377 ARMword rhs; 390 ARMword rhs;
378 ARMword decoded = 0; /* Instruction pipeline. */ 391 ARMword decoded = 0; /* Instruction pipeline. */
379 ARMword loaded = 0; 392 ARMword loaded = 0;
380 ARMword decoded_addr=0; 393 ARMword decoded_addr=0;
381 ARMword loaded_addr=0; 394 ARMword loaded_addr=0;
382 ARMword have_bp=0; 395 ARMword have_bp=0;
383 396
397#ifdef callstacker
398 char a[256];
399#endif
384 /* shenoubang */ 400 /* shenoubang */
385 static int instr_sum = 0; 401 static int instr_sum = 0;
386 int reg_index = 0; 402 int reg_index = 0;
387#if DIFF_STATE 403#if DIFF_STATE
388//initialize all mirror register for follow mode 404//initialize all mirror register for follow mode
389 for (reg_index = 0; reg_index < 16; reg_index ++) { 405 for (reg_index = 0; reg_index < 16; reg_index ++) {
390 mirror_register_file[reg_index] = state->Reg[reg_index]; 406 mirror_register_file[reg_index] = state->Reg[reg_index];
391 } 407 }
392 mirror_register_file[CPSR_REG] = state->Cpsr; 408 mirror_register_file[CPSR_REG] = state->Cpsr;
393 mirror_register_file[R13_SVC] = state->RegBank[SVCBANK][13]; 409 mirror_register_file[R13_SVC] = state->RegBank[SVCBANK][13];
@@ -422,10 +438,10 @@ ARMul_Emulate26 (ARMul_State * state)
422 } 438 }
423 439
424 do { 440 do {
425 //print_func_name(state->pc); 441 //print_func_name(state->pc);
426 /* Just keep going. */ 442 /* Just keep going. */
427 isize = INSN_SIZE; 443 isize = INSN_SIZE;
428 444
429 switch (state->NextInstr) { 445 switch (state->NextInstr) {
430 case SEQ: 446 case SEQ:
431 /* Advance the pipeline, and an S cycle. */ 447 /* Advance the pipeline, and an S cycle. */
@@ -437,7 +453,7 @@ ARMul_Emulate26 (ARMul_State * state)
437 decoded = loaded; 453 decoded = loaded;
438 decoded_addr=loaded_addr; 454 decoded_addr=loaded_addr;
439 //loaded = ARMul_LoadInstrS (state, pc + (isize * 2), 455 //loaded = ARMul_LoadInstrS (state, pc + (isize * 2),
440 // isize); 456 // isize);
441 loaded_addr=pc + (isize * 2); 457 loaded_addr=pc + (isize * 2);
442 if (have_bp) goto TEST_EMULATE; 458 if (have_bp) goto TEST_EMULATE;
443 break; 459 break;
@@ -452,7 +468,7 @@ ARMul_Emulate26 (ARMul_State * state)
452 decoded = loaded; 468 decoded = loaded;
453 decoded_addr=loaded_addr; 469 decoded_addr=loaded_addr;
454 //loaded = ARMul_LoadInstrN (state, pc + (isize * 2), 470 //loaded = ARMul_LoadInstrN (state, pc + (isize * 2),
455 // isize); 471 // isize);
456 loaded_addr=pc + (isize * 2); 472 loaded_addr=pc + (isize * 2);
457 NORMALCYCLE; 473 NORMALCYCLE;
458 if (have_bp) goto TEST_EMULATE; 474 if (have_bp) goto TEST_EMULATE;
@@ -467,7 +483,7 @@ ARMul_Emulate26 (ARMul_State * state)
467 decoded = loaded; 483 decoded = loaded;
468 decoded_addr=loaded_addr; 484 decoded_addr=loaded_addr;
469 //loaded = ARMul_LoadInstrS (state, pc + (isize * 2), 485 //loaded = ARMul_LoadInstrS (state, pc + (isize * 2),
470 // isize); 486 // isize);
471 loaded_addr=pc + (isize * 2); 487 loaded_addr=pc + (isize * 2);
472 NORMALCYCLE; 488 NORMALCYCLE;
473 if (have_bp) goto TEST_EMULATE; 489 if (have_bp) goto TEST_EMULATE;
@@ -482,7 +498,7 @@ ARMul_Emulate26 (ARMul_State * state)
482 decoded = loaded; 498 decoded = loaded;
483 decoded_addr=loaded_addr; 499 decoded_addr=loaded_addr;
484 //loaded = ARMul_LoadInstrN (state, pc + (isize * 2), 500 //loaded = ARMul_LoadInstrN (state, pc + (isize * 2),
485 // isize); 501 // isize);
486 loaded_addr=pc + (isize * 2); 502 loaded_addr=pc + (isize * 2);
487 NORMALCYCLE; 503 NORMALCYCLE;
488 if (have_bp) goto TEST_EMULATE; 504 if (have_bp) goto TEST_EMULATE;
@@ -504,10 +520,10 @@ ARMul_Emulate26 (ARMul_State * state)
504 //chy 2006-04-12, for ICE debug 520 //chy 2006-04-12, for ICE debug
505 have_bp=ARMul_ICE_debug(state,instr,pc); 521 have_bp=ARMul_ICE_debug(state,instr,pc);
506 //decoded = 522 //decoded =
507 // ARMul_ReLoadInstr (state, pc + isize, isize); 523 // ARMul_ReLoadInstr (state, pc + isize, isize);
508 decoded_addr=pc+isize; 524 decoded_addr=pc+isize;
509 //loaded = ARMul_ReLoadInstr (state, pc + isize * 2, 525 //loaded = ARMul_ReLoadInstr (state, pc + isize * 2,
510 // isize); 526 // isize);
511 loaded_addr=pc + isize * 2; 527 loaded_addr=pc + isize * 2;
512 NORMALCYCLE; 528 NORMALCYCLE;
513 if (have_bp) goto TEST_EMULATE; 529 if (have_bp) goto TEST_EMULATE;
@@ -527,15 +543,15 @@ ARMul_Emulate26 (ARMul_State * state)
527 instr = ARMul_LoadInstrN (state, pc, isize); 543 instr = ARMul_LoadInstrN (state, pc, isize);
528 //chy 2006-04-12, for ICE debug 544 //chy 2006-04-12, for ICE debug
529 have_bp=ARMul_ICE_debug(state,instr,pc); 545 have_bp=ARMul_ICE_debug(state,instr,pc);
530 #if 0 546#if 0
531 decoded = 547 decoded =
532 ARMul_LoadInstrS (state, pc + (isize), isize); 548 ARMul_LoadInstrS (state, pc + (isize), isize);
533 #endif 549#endif
534 decoded_addr=pc+isize; 550 decoded_addr=pc+isize;
535 #if 0 551#if 0
536 loaded = ARMul_LoadInstrS (state, pc + (isize * 2), 552 loaded = ARMul_LoadInstrS (state, pc + (isize * 2),
537 isize); 553 isize);
538 #endif 554#endif
539 loaded_addr=pc + isize * 2; 555 loaded_addr=pc + isize * 2;
540 NORMALCYCLE; 556 NORMALCYCLE;
541 if (have_bp) goto TEST_EMULATE; 557 if (have_bp) goto TEST_EMULATE;
@@ -544,164 +560,161 @@ ARMul_Emulate26 (ARMul_State * state)
544#if 0 560#if 0
545 int idx = 0; 561 int idx = 0;
546 printf("pc:%x\n", pc); 562 printf("pc:%x\n", pc);
547 for (;idx < 17; idx ++) { 563 for (; idx < 17; idx ++) {
548 printf("R%d:%x\t", idx, state->Reg[idx]); 564 printf("R%d:%x\t", idx, state->Reg[idx]);
549 } 565 }
550 printf("\n"); 566 printf("\n");
551#endif 567#endif
552 instr = ARMul_LoadInstrN (state, pc, isize); 568 instr = ARMul_LoadInstrN (state, pc, isize);
553 state->last_instr = state->CurrInstr; 569 state->last_instr = state->CurrInstr;
554 state->CurrInstr = instr; 570 state->CurrInstr = instr;
571 ARMul_Debug(state, pc, instr);
555#if 0 572#if 0
556 if((state->NumInstrs % 10000000) == 0) 573 if((state->NumInstrs % 10000000) == 0)
557 printf("---|%p|--- %lld\n", pc, state->NumInstrs); 574 printf("---|%p|--- %lld\n", pc, state->NumInstrs);
558 if(state->NumInstrs > (3000000000)){ 575 if(state->NumInstrs > (3000000000)) {
559 static int flag = 0; 576 static int flag = 0;
560 if(pc == 0x8032ccc4){ 577 if(pc == 0x8032ccc4) {
561 flag = 300; 578 flag = 300;
562 } 579 }
563 if(flag){ 580 if(flag) {
564 int idx = 0; 581 int idx = 0;
565 printf("------------------------------------\n"); 582 printf("------------------------------------\n");
566 printf("pc:%x\n", pc); 583 printf("pc:%x\n", pc);
567 for (;idx < 17; idx ++) { 584 for (; idx < 17; idx ++) {
568 printf("R%d:%x\t", idx, state->Reg[idx]); 585 printf("R%d:%x\t", idx, state->Reg[idx]);
569 } 586 }
570 printf("\nN:%d\t Z:%d\t C:%d\t V:%d\n", state->NFlag, state->ZFlag, state->CFlag, state->VFlag); 587 printf("\nN:%d\t Z:%d\t C:%d\t V:%d\n", state->NFlag, state->ZFlag, state->CFlag, state->VFlag);
571 printf("\n"); 588 printf("\n");
572 printf("------------------------------------\n"); 589 printf("------------------------------------\n");
573 flag--; 590 flag--;
591 }
574 } 592 }
575 } 593#endif
576#endif
577#if DIFF_STATE 594#if DIFF_STATE
578 fprintf(state->state_log, "PC:0x%x\n", pc); 595 fprintf(state->state_log, "PC:0x%x\n", pc);
579 if (pc && (pc + 8) != state->Reg[15]) { 596 if (pc && (pc + 8) != state->Reg[15]) {
580 printf("lucky dog\n"); 597 printf("lucky dog\n");
581 printf("pc is %x, R15 is %x\n", pc, state->Reg[15]); 598 printf("pc is %x, R15 is %x\n", pc, state->Reg[15]);
582 //exit(-1); 599 //exit(-1);
583 } 600 }
584 for (reg_index = 0; reg_index < 16; reg_index ++) { 601 for (reg_index = 0; reg_index < 16; reg_index ++) {
585 if (state->Reg[reg_index] != mirror_register_file[reg_index]) { 602 if (state->Reg[reg_index] != mirror_register_file[reg_index]) {
586 fprintf(state->state_log, "R%d:0x%x\n", reg_index, state->Reg[reg_index]); 603 fprintf(state->state_log, "R%d:0x%x\n", reg_index, state->Reg[reg_index]);
587 mirror_register_file[reg_index] = state->Reg[reg_index]; 604 mirror_register_file[reg_index] = state->Reg[reg_index];
588 } 605 }
589 } 606 }
590 if (state->Cpsr != mirror_register_file[CPSR_REG]) { 607 if (state->Cpsr != mirror_register_file[CPSR_REG]) {
591 fprintf(state->state_log, "Cpsr:0x%x\n", state->Cpsr); 608 fprintf(state->state_log, "Cpsr:0x%x\n", state->Cpsr);
592 mirror_register_file[CPSR_REG] = state->Cpsr; 609 mirror_register_file[CPSR_REG] = state->Cpsr;
593 } 610 }
594 if (state->RegBank[SVCBANK][13] != mirror_register_file[R13_SVC]) { 611 if (state->RegBank[SVCBANK][13] != mirror_register_file[R13_SVC]) {
595 fprintf(state->state_log, "R13_SVC:0x%x\n", state->RegBank[SVCBANK][13]); 612 fprintf(state->state_log, "R13_SVC:0x%x\n", state->RegBank[SVCBANK][13]);
596 mirror_register_file[R13_SVC] = state->RegBank[SVCBANK][13]; 613 mirror_register_file[R13_SVC] = state->RegBank[SVCBANK][13];
597 } 614 }
598 if (state->RegBank[SVCBANK][14] != mirror_register_file[R14_SVC]) { 615 if (state->RegBank[SVCBANK][14] != mirror_register_file[R14_SVC]) {
599 fprintf(state->state_log, "R14_SVC:0x%x\n", state->RegBank[SVCBANK][14]); 616 fprintf(state->state_log, "R14_SVC:0x%x\n", state->RegBank[SVCBANK][14]);
600 mirror_register_file[R14_SVC] = state->RegBank[SVCBANK][14]; 617 mirror_register_file[R14_SVC] = state->RegBank[SVCBANK][14];
601 } 618 }
602 if (state->RegBank[ABORTBANK][13] != mirror_register_file[R13_ABORT]) { 619 if (state->RegBank[ABORTBANK][13] != mirror_register_file[R13_ABORT]) {
603 fprintf(state->state_log, "R13_ABORT:0x%x\n", state->RegBank[ABORTBANK][13]); 620 fprintf(state->state_log, "R13_ABORT:0x%x\n", state->RegBank[ABORTBANK][13]);
604 mirror_register_file[R13_ABORT] = state->RegBank[ABORTBANK][13]; 621 mirror_register_file[R13_ABORT] = state->RegBank[ABORTBANK][13];
605 } 622 }
606 if (state->RegBank[ABORTBANK][14] != mirror_register_file[R14_ABORT]) { 623 if (state->RegBank[ABORTBANK][14] != mirror_register_file[R14_ABORT]) {
607 fprintf(state->state_log, "R14_ABORT:0x%x\n", state->RegBank[ABORTBANK][14]); 624 fprintf(state->state_log, "R14_ABORT:0x%x\n", state->RegBank[ABORTBANK][14]);
608 mirror_register_file[R14_ABORT] = state->RegBank[ABORTBANK][14]; 625 mirror_register_file[R14_ABORT] = state->RegBank[ABORTBANK][14];
609 } 626 }
610 if (state->RegBank[UNDEFBANK][13] != mirror_register_file[R13_UNDEF]) { 627 if (state->RegBank[UNDEFBANK][13] != mirror_register_file[R13_UNDEF]) {
611 fprintf(state->state_log, "R13_UNDEF:0x%x\n", state->RegBank[UNDEFBANK][13]); 628 fprintf(state->state_log, "R13_UNDEF:0x%x\n", state->RegBank[UNDEFBANK][13]);
612 mirror_register_file[R13_UNDEF] = state->RegBank[UNDEFBANK][13]; 629 mirror_register_file[R13_UNDEF] = state->RegBank[UNDEFBANK][13];
613 } 630 }
614 if (state->RegBank[UNDEFBANK][14] != mirror_register_file[R14_UNDEF]) { 631 if (state->RegBank[UNDEFBANK][14] != mirror_register_file[R14_UNDEF]) {
615 fprintf(state->state_log, "R14_UNDEF:0x%x\n", state->RegBank[UNDEFBANK][14]); 632 fprintf(state->state_log, "R14_UNDEF:0x%x\n", state->RegBank[UNDEFBANK][14]);
616 mirror_register_file[R14_UNDEF] = state->RegBank[UNDEFBANK][14]; 633 mirror_register_file[R14_UNDEF] = state->RegBank[UNDEFBANK][14];
617 } 634 }
618 if (state->RegBank[IRQBANK][13] != mirror_register_file[R13_IRQ]) { 635 if (state->RegBank[IRQBANK][13] != mirror_register_file[R13_IRQ]) {
619 fprintf(state->state_log, "R13_IRQ:0x%x\n", state->RegBank[IRQBANK][13]); 636 fprintf(state->state_log, "R13_IRQ:0x%x\n", state->RegBank[IRQBANK][13]);
620 mirror_register_file[R13_IRQ] = state->RegBank[IRQBANK][13]; 637 mirror_register_file[R13_IRQ] = state->RegBank[IRQBANK][13];
621 } 638 }
622 if (state->RegBank[IRQBANK][14] != mirror_register_file[R14_IRQ]) { 639 if (state->RegBank[IRQBANK][14] != mirror_register_file[R14_IRQ]) {
623 fprintf(state->state_log, "R14_IRQ:0x%x\n", state->RegBank[IRQBANK][14]); 640 fprintf(state->state_log, "R14_IRQ:0x%x\n", state->RegBank[IRQBANK][14]);
624 mirror_register_file[R14_IRQ] = state->RegBank[IRQBANK][14]; 641 mirror_register_file[R14_IRQ] = state->RegBank[IRQBANK][14];
625 } 642 }
626 if (state->RegBank[FIQBANK][8] != mirror_register_file[R8_FIRQ]) { 643 if (state->RegBank[FIQBANK][8] != mirror_register_file[R8_FIRQ]) {
627 fprintf(state->state_log, "R8_FIRQ:0x%x\n", state->RegBank[FIQBANK][8]); 644 fprintf(state->state_log, "R8_FIRQ:0x%x\n", state->RegBank[FIQBANK][8]);
628 mirror_register_file[R8_FIRQ] = state->RegBank[FIQBANK][8]; 645 mirror_register_file[R8_FIRQ] = state->RegBank[FIQBANK][8];
629 } 646 }
630 if (state->RegBank[FIQBANK][9] != mirror_register_file[R9_FIRQ]) { 647 if (state->RegBank[FIQBANK][9] != mirror_register_file[R9_FIRQ]) {
631 fprintf(state->state_log, "R9_FIRQ:0x%x\n", state->RegBank[FIQBANK][9]); 648 fprintf(state->state_log, "R9_FIRQ:0x%x\n", state->RegBank[FIQBANK][9]);
632 mirror_register_file[R9_FIRQ] = state->RegBank[FIQBANK][9]; 649 mirror_register_file[R9_FIRQ] = state->RegBank[FIQBANK][9];
633 } 650 }
634 if (state->RegBank[FIQBANK][10] != mirror_register_file[R10_FIRQ]) { 651 if (state->RegBank[FIQBANK][10] != mirror_register_file[R10_FIRQ]) {
635 fprintf(state->state_log, "R10_FIRQ:0x%x\n", state->RegBank[FIQBANK][10]); 652 fprintf(state->state_log, "R10_FIRQ:0x%x\n", state->RegBank[FIQBANK][10]);
636 mirror_register_file[R10_FIRQ] = state->RegBank[FIQBANK][10]; 653 mirror_register_file[R10_FIRQ] = state->RegBank[FIQBANK][10];
637 } 654 }
638 if (state->RegBank[FIQBANK][11] != mirror_register_file[R11_FIRQ]) { 655 if (state->RegBank[FIQBANK][11] != mirror_register_file[R11_FIRQ]) {
639 fprintf(state->state_log, "R11_FIRQ:0x%x\n", state->RegBank[FIQBANK][11]); 656 fprintf(state->state_log, "R11_FIRQ:0x%x\n", state->RegBank[FIQBANK][11]);
640 mirror_register_file[R11_FIRQ] = state->RegBank[FIQBANK][11]; 657 mirror_register_file[R11_FIRQ] = state->RegBank[FIQBANK][11];
641 } 658 }
642 if (state->RegBank[FIQBANK][12] != mirror_register_file[R12_FIRQ]) { 659 if (state->RegBank[FIQBANK][12] != mirror_register_file[R12_FIRQ]) {
643 fprintf(state->state_log, "R12_FIRQ:0x%x\n", state->RegBank[FIQBANK][12]); 660 fprintf(state->state_log, "R12_FIRQ:0x%x\n", state->RegBank[FIQBANK][12]);
644 mirror_register_file[R12_FIRQ] = state->RegBank[FIQBANK][12]; 661 mirror_register_file[R12_FIRQ] = state->RegBank[FIQBANK][12];
645 } 662 }
646 if (state->RegBank[FIQBANK][13] != mirror_register_file[R13_FIRQ]) { 663 if (state->RegBank[FIQBANK][13] != mirror_register_file[R13_FIRQ]) {
647 fprintf(state->state_log, "R13_FIRQ:0x%x\n", state->RegBank[FIQBANK][13]); 664 fprintf(state->state_log, "R13_FIRQ:0x%x\n", state->RegBank[FIQBANK][13]);
648 mirror_register_file[R13_FIRQ] = state->RegBank[FIQBANK][13]; 665 mirror_register_file[R13_FIRQ] = state->RegBank[FIQBANK][13];
649 } 666 }
650 if (state->RegBank[FIQBANK][14] != mirror_register_file[R14_FIRQ]) { 667 if (state->RegBank[FIQBANK][14] != mirror_register_file[R14_FIRQ]) {
651 fprintf(state->state_log, "R14_FIRQ:0x%x\n", state->RegBank[FIQBANK][14]); 668 fprintf(state->state_log, "R14_FIRQ:0x%x\n", state->RegBank[FIQBANK][14]);
652 mirror_register_file[R14_FIRQ] = state->RegBank[FIQBANK][14]; 669 mirror_register_file[R14_FIRQ] = state->RegBank[FIQBANK][14];
653 } 670 }
654 if (state->Spsr[SVCBANK] != mirror_register_file[SPSR_SVC]) { 671 if (state->Spsr[SVCBANK] != mirror_register_file[SPSR_SVC]) {
655 fprintf(state->state_log, "SPSR_SVC:0x%x\n", state->Spsr[SVCBANK]); 672 fprintf(state->state_log, "SPSR_SVC:0x%x\n", state->Spsr[SVCBANK]);
656 mirror_register_file[SPSR_SVC] = state->RegBank[SVCBANK]; 673 mirror_register_file[SPSR_SVC] = state->RegBank[SVCBANK];
657 } 674 }
658 if (state->Spsr[ABORTBANK] != mirror_register_file[SPSR_ABORT]) { 675 if (state->Spsr[ABORTBANK] != mirror_register_file[SPSR_ABORT]) {
659 fprintf(state->state_log, "SPSR_ABORT:0x%x\n", state->Spsr[ABORTBANK]); 676 fprintf(state->state_log, "SPSR_ABORT:0x%x\n", state->Spsr[ABORTBANK]);
660 mirror_register_file[SPSR_ABORT] = state->RegBank[ABORTBANK]; 677 mirror_register_file[SPSR_ABORT] = state->RegBank[ABORTBANK];
661 } 678 }
662 if (state->Spsr[UNDEFBANK] != mirror_register_file[SPSR_UNDEF]) { 679 if (state->Spsr[UNDEFBANK] != mirror_register_file[SPSR_UNDEF]) {
663 fprintf(state->state_log, "SPSR_UNDEF:0x%x\n", state->Spsr[UNDEFBANK]); 680 fprintf(state->state_log, "SPSR_UNDEF:0x%x\n", state->Spsr[UNDEFBANK]);
664 mirror_register_file[SPSR_UNDEF] = state->RegBank[UNDEFBANK]; 681 mirror_register_file[SPSR_UNDEF] = state->RegBank[UNDEFBANK];
665 } 682 }
666 if (state->Spsr[IRQBANK] != mirror_register_file[SPSR_IRQ]) { 683 if (state->Spsr[IRQBANK] != mirror_register_file[SPSR_IRQ]) {
667 fprintf(state->state_log, "SPSR_IRQ:0x%x\n", state->Spsr[IRQBANK]); 684 fprintf(state->state_log, "SPSR_IRQ:0x%x\n", state->Spsr[IRQBANK]);
668 mirror_register_file[SPSR_IRQ] = state->RegBank[IRQBANK]; 685 mirror_register_file[SPSR_IRQ] = state->RegBank[IRQBANK];
669 } 686 }
670 if (state->Spsr[FIQBANK] != mirror_register_file[SPSR_FIRQ]) { 687 if (state->Spsr[FIQBANK] != mirror_register_file[SPSR_FIRQ]) {
671 fprintf(state->state_log, "SPSR_FIRQ:0x%x\n", state->Spsr[FIQBANK]); 688 fprintf(state->state_log, "SPSR_FIRQ:0x%x\n", state->Spsr[FIQBANK]);
672 mirror_register_file[SPSR_FIRQ] = state->RegBank[FIQBANK]; 689 mirror_register_file[SPSR_FIRQ] = state->RegBank[FIQBANK];
673 } 690 }
674#endif 691#endif
675 692
676#if 0 693#if 0
677 uint32_t alex = 0; 694 uint32_t alex = 0;
678 static int flagged = 0; 695 static int flagged = 0;
679 if ((flagged == 0) && (pc == 0xb224)) 696 if ((flagged == 0) && (pc == 0xb224)) {
680 {
681 flagged++; 697 flagged++;
682 } 698 }
683 if ((flagged == 1) && (pc == 0x1a800)) 699 if ((flagged == 1) && (pc == 0x1a800)) {
684 {
685 flagged++; 700 flagged++;
686 } 701 }
687 if (flagged == 3) { 702 if (flagged == 3) {
688 printf("---|%p|--- %x\n", pc, state->NumInstrs); 703 printf("---|%p|--- %x\n", pc, state->NumInstrs);
689 for (alex = 0; alex < 15; alex++) 704 for (alex = 0; alex < 15; alex++) {
690 {
691 printf("R%02d % 8x\n", alex, state->Reg[alex]); 705 printf("R%02d % 8x\n", alex, state->Reg[alex]);
692 } 706 }
693 printf("R%02d % 8x\n", alex, state->Reg[alex] - 8); 707 printf("R%02d % 8x\n", alex, state->Reg[alex] - 8);
694 printf("CPS %x%07x\n", (state->NFlag<<3 | state->ZFlag<<2 | state->CFlag<<1 | state->VFlag), state->Cpsr & 0xfffffff); 708 printf("CPS %x%07x\n", (state->NFlag<<3 | state->ZFlag<<2 | state->CFlag<<1 | state->VFlag), state->Cpsr & 0xfffffff);
695 } else { 709 } else {
696 if (state->NumInstrs < 0x400000) 710 if (state->NumInstrs < 0x400000) {
697 {
698 //exit(-1); 711 //exit(-1);
699 } 712 }
700 } 713 }
701#endif 714#endif
702 715
703 if (state->EventSet) 716 /*if (state->EventSet)
704 ARMul_EnvokeEvent (state); 717 ARMul_EnvokeEvent (state);*/
705 718
706#if 0 719#if 0
707 /* do profiling for code coverage */ 720 /* do profiling for code coverage */
@@ -712,7 +725,7 @@ ARMul_Emulate26 (ARMul_State * state)
712#if 0 725#if 0
713 if (skyeye_config.log.logon >= 1) { 726 if (skyeye_config.log.logon >= 1) {
714 if (state->NumInstrs >= skyeye_config.log.start && 727 if (state->NumInstrs >= skyeye_config.log.start &&
715 state->NumInstrs <= skyeye_config.log.end) { 728 state->NumInstrs <= skyeye_config.log.end) {
716 static int mybegin = 0; 729 static int mybegin = 0;
717 static int myinstrnum = 0; 730 static int myinstrnum = 0;
718 if (mybegin == 0) 731 if (mybegin == 0)
@@ -736,16 +749,16 @@ ARMul_Emulate26 (ARMul_State * state)
736 printf ("***********SKYEYE: numinstr = 67347000, begin log\n"); 749 printf ("***********SKYEYE: numinstr = 67347000, begin log\n");
737 mybegin = 1; 750 mybegin = 1;
738 } 751 }
739 if (pc == 0xc00087b4) { //numinstr=67348714 752 if (pc == 0xc00087b4) { //numinstr=67348714
740 mybegin = 1; 753 mybegin = 1;
741 printf ("************SKYEYE: test irq now numinstr is %llu ****************\n", state->NumInstrs); 754 printf ("************SKYEYE: test irq now numinstr is %llu ****************\n", state->NumInstrs);
742 } 755 }
743 if (pc == 0xc00087b8) { //in start_kernel::sti() 756 if (pc == 0xc00087b8) { //in start_kernel::sti()
744 mybeg4 = 1; 757 mybeg4 = 1;
745 printf ("************SKYEYE: startkerenl: sti now numinstr is %llu ********\n", state->NumInstrs); 758 printf ("************SKYEYE: startkerenl: sti now numinstr is %llu ********\n", state->NumInstrs);
746 } 759 }
747 /*if (pc==0xc001e4f4||pc==0xc001e4f8||pc==0xc001e4fc||pc==0xc001e500||pc==0xffff0004) { //MRA instr */ 760 /*if (pc==0xc001e4f4||pc==0xc001e4f8||pc==0xc001e4fc||pc==0xc001e500||pc==0xffff0004) { //MRA instr */
748 if (pc == 0xc001e500) { //MRA instr 761 if (pc == 0xc001e500) { //MRA instr
749 mybeg5 = 1; 762 mybeg5 = 1;
750 printf ("************SKYEYE: MRA instr now numinstr is %llu ********\n", state->NumInstrs); 763 printf ("************SKYEYE: MRA instr now numinstr is %llu ********\n", state->NumInstrs);
751 } 764 }
@@ -755,7 +768,7 @@ ARMul_Emulate26 (ARMul_State * state)
755 SKYEYE_OUTREGS (stderr); 768 SKYEYE_OUTREGS (stderr);
756 printf ("************************************************************************\n"); 769 printf ("************************************************************************\n");
757 } 770 }
758 //chy 2003-09-01 test after tlb-flush 771 //chy 2003-09-01 test after tlb-flush
759 if (pc == 0xc00261ac) { 772 if (pc == 0xc00261ac) {
760 //sleep(2); 773 //sleep(2);
761 mybeg3 = 1; 774 mybeg3 = 1;
@@ -779,29 +792,29 @@ ARMul_Emulate26 (ARMul_State * state)
779 } 792 }
780 */ 793 */
781 if (skyeye_config.log.logon >= 1) 794 if (skyeye_config.log.logon >= 1)
782 /* 795 /*
783 fprintf (skyeye_logfd, 796 fprintf (skyeye_logfd,
784 "N %llx :p %x,i %x,", 797 "N %llx :p %x,i %x,",
785 state->NumInstrs, pc, 798 state->NumInstrs, pc,
786#ifdef MODET 799 #ifdef MODET
787 TFLAG ? instr & 0xffff : instr 800 TFLAG ? instr & 0xffff : instr
788#else 801 #else
789 instr 802 instr
790#endif 803 #endif
791 ); 804 );
792 */ 805 */
793 fprintf(skyeye_logfd, "pc=0x%x,r3=0x%x\n", pc, state->Reg[3]); 806 fprintf(skyeye_logfd, "pc=0x%x,r3=0x%x\n", pc, state->Reg[3]);
794 if (skyeye_config.log.logon >= 2) 807 if (skyeye_config.log.logon >= 2)
795 SKYEYE_OUTREGS (skyeye_logfd); 808 SKYEYE_OUTREGS (skyeye_logfd);
796 if (skyeye_config.log.logon >= 3) 809 if (skyeye_config.log.logon >= 3)
797 SKYEYE_OUTMOREREGS 810 SKYEYE_OUTMOREREGS
798 (skyeye_logfd); 811 (skyeye_logfd);
799 //fprintf (skyeye_logfd, "\n"); 812 //fprintf (skyeye_logfd, "\n");
800 if (skyeye_config.log.length > 0) { 813 if (skyeye_config.log.length > 0) {
801 myinstrnum++; 814 myinstrnum++;
802 if (myinstrnum >= 815 if (myinstrnum >=
803 skyeye_config.log. 816 skyeye_config.log.
804 length) { 817 length) {
805 myinstrnum = 0; 818 myinstrnum = 0;
806 fflush (skyeye_logfd); 819 fflush (skyeye_logfd);
807 fseek (skyeye_logfd, 820 fseek (skyeye_logfd,
@@ -814,21 +827,21 @@ ARMul_Emulate26 (ARMul_State * state)
814 } 827 }
815 } 828 }
816#endif 829#endif
817#if 0 /* Enable this for a helpful bit of debugging when tracing is needed. */ 830#if 0 /* Enable this for a helpful bit of debugging when tracing is needed. */
818 fprintf (stderr, "pc: %x, instr: %x\n", pc & ~1, instr); 831 fprintf (stderr, "pc: %x, instr: %x\n", pc & ~1, instr);
819 if (instr == 0) 832 if (instr == 0)
820 abort (); 833 abort ();
821#endif 834#endif
822#if 0 /* Enable this code to help track down stack alignment bugs. */ 835#if 0 /* Enable this code to help track down stack alignment bugs. */
823 { 836 {
824 static ARMword old_sp = -1; 837 static ARMword old_sp = -1;
825 838
826 if (old_sp != state->Reg[13]) { 839 if (old_sp != state->Reg[13]) {
827 old_sp = state->Reg[13]; 840 old_sp = state->Reg[13];
828 fprintf (stderr, 841 fprintf (stderr,
829 "pc: %08x: SP set to %08x%s\n", 842 "pc: %08x: SP set to %08x%s\n",
830 pc & ~1, old_sp, 843 pc & ~1, old_sp,
831 (old_sp % 8) ? " [UNALIGNED!]" : ""); 844 (old_sp % 8) ? " [UNALIGNED!]" : "");
832 } 845 }
833 } 846 }
834#endif 847#endif
@@ -840,15 +853,13 @@ ARMul_Emulate26 (ARMul_State * state)
840 //chy 2005-07-28 for standalone 853 //chy 2005-07-28 for standalone
841 //ARMul_do_energy(state,instr,pc); 854 //ARMul_do_energy(state,instr,pc);
842 break; 855 break;
843 } 856 } else if (!state->NfiqSig && !FFLAG) {
844 else if (!state->NfiqSig && !FFLAG) {
845 ARMul_Abort (state, ARMul_FIQV); 857 ARMul_Abort (state, ARMul_FIQV);
846 /*added energy_prof statement by ksh in 2004-11-26 */ 858 /*added energy_prof statement by ksh in 2004-11-26 */
847 //chy 2005-07-28 for standalone 859 //chy 2005-07-28 for standalone
848 //ARMul_do_energy(state,instr,pc); 860 //ARMul_do_energy(state,instr,pc);
849 break; 861 break;
850 } 862 } else if (!state->NirqSig && !IFLAG) {
851 else if (!state->NirqSig && !IFLAG) {
852 ARMul_Abort (state, ARMul_IRQV); 863 ARMul_Abort (state, ARMul_IRQV);
853 /*added energy_prof statement by ksh in 2004-11-26 */ 864 /*added energy_prof statement by ksh in 2004-11-26 */
854 //chy 2005-07-28 for standalone 865 //chy 2005-07-28 for standalone
@@ -860,11 +871,11 @@ ARMul_Emulate26 (ARMul_State * state)
860#if 0 871#if 0
861// if (state->pc == 0xc011a868 || state->pc == 0xc011a86c) { 872// if (state->pc == 0xc011a868 || state->pc == 0xc011a86c) {
862 if (state->NumInstrs == 1671574 || state->NumInstrs == 1671573 || state->NumInstrs == 1671572 873 if (state->NumInstrs == 1671574 || state->NumInstrs == 1671573 || state->NumInstrs == 1671572
863 || state->NumInstrs == 1671575) { 874 || state->NumInstrs == 1671575) {
864 for (reg_index = 0; reg_index < 16; reg_index ++) { 875 for (reg_index = 0; reg_index < 16; reg_index ++) {
865 printf("R%d:%x\t", reg_index, state->Reg[reg_index]); 876 printf("R%d:%x\t", reg_index, state->Reg[reg_index]);
866 } 877 }
867 printf("\n"); 878 printf("\n");
868 } 879 }
869#endif 880#endif
870 if (state->tea_pc) { 881 if (state->tea_pc) {
@@ -874,14 +885,13 @@ ARMul_Emulate26 (ARMul_State * state)
874 fprintf (state->tea_reg_fd, "\n"); 885 fprintf (state->tea_reg_fd, "\n");
875 for (i = 0; i < 15; i++) { 886 for (i = 0; i < 15; i++) {
876 fprintf (state->tea_reg_fd, "%x,", 887 fprintf (state->tea_reg_fd, "%x,",
877 state->Reg[i]); 888 state->Reg[i]);
878 } 889 }
879 fprintf (state->tea_reg_fd, "%x,", pc); 890 fprintf (state->tea_reg_fd, "%x,", pc);
880 state->Cpsr = ARMul_GetCPSR (state); 891 state->Cpsr = ARMul_GetCPSR (state);
881 fprintf (state->tea_reg_fd, "%x\n", 892 fprintf (state->tea_reg_fd, "%x\n",
882 state->Cpsr); 893 state->Cpsr);
883 } 894 } else {
884 else {
885 printf ("\n"); 895 printf ("\n");
886 for (i = 0; i < 15; i++) { 896 for (i = 0; i < 15; i++) {
887 printf ("%x,", state->Reg[i]); 897 printf ("%x,", state->Reg[i]);
@@ -893,30 +903,31 @@ ARMul_Emulate26 (ARMul_State * state)
893 } 903 }
894//AJ2D-------------------------------------------------------------------------- 904//AJ2D--------------------------------------------------------------------------
895 905
896 if (state->CallDebug > 0) { 906 /*if (state->CallDebug > 0) {
897 instr = ARMul_Debug (state, pc, instr); 907 instr = ARMul_Debug (state, pc, instr);
898 if (state->Emulate < ONCE) { 908 if (state->Emulate < ONCE) {
899 state->NextInstr = RESUME; 909 state->NextInstr = RESUME;
900 break; 910 break;
901 } 911 }
902 if (state->Debug) { 912 if (state->Debug) {
903 fprintf (stderr, 913 fprintf (stderr,
904 "sim: At %08lx Instr %08lx Mode %02lx\n", 914 "sim: At %08lx Instr %08lx Mode %02lx\n",
905 pc, instr, state->Mode); 915 pc, instr, state->Mode);
906 (void) fgetc (stdin); 916 (void) fgetc (stdin);
907 } 917 }
908 } 918 }
909 else if (state->Emulate < ONCE) { 919 else*/
920 if (state->Emulate < ONCE) {
910 state->NextInstr = RESUME; 921 state->NextInstr = RESUME;
911 break; 922 break;
912 } 923 }
913 //io_do_cycle (state); 924 //io_do_cycle (state);
914 state->NumInstrs++; 925 state->NumInstrs++;
915 #if 0 926#if 0
916 if (state->NumInstrs % 10000000 == 0) { 927 if (state->NumInstrs % 10000000 == 0) {
917 printf("10 MIPS instr have been executed\n"); 928 printf("10 MIPS instr have been executed\n");
918 } 929 }
919 #endif 930#endif
920 931
921#ifdef MODET 932#ifdef MODET
922 /* Provide Thumb instruction decoding. If the processor is in Thumb 933 /* Provide Thumb instruction decoding. If the processor is in Thumb
@@ -927,23 +938,31 @@ ARMul_Emulate26 (ARMul_State * state)
927 pipelined PC value is used when executing Thumb code, and also for 938 pipelined PC value is used when executing Thumb code, and also for
928 dealing with the BL instruction. */ 939 dealing with the BL instruction. */
929 if (TFLAG) { 940 if (TFLAG) {
930 ARMword new_instr; 941 ARMword armOp = 0;
931
932 /* Check if in Thumb mode. */ 942 /* Check if in Thumb mode. */
933 switch (ARMul_ThumbDecode(state, pc, instr, &new_instr)) { 943 switch (ARMul_ThumbDecode(state, pc, instr, &armOp)) {
934 case t_undefined: 944 case t_undefined:
935 /* This is a Thumb instruction. */ 945 /* This is a Thumb instruction. */
936 ARMul_UndefInstr (state, instr); 946 ARMul_UndefInstr (state, instr);
937 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext; 947 goto donext;
938 948
939 case t_branch: 949 case t_branch:
940 /* Already processed. */ 950 /* Already processed. */
941 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext; 951 //pc = state->Reg[15] - 2;
952 //state->pc = state->Reg[15] - 2; //ichfly why do I need that
953 goto donext;
942 954
943 case t_decoded: 955 case t_decoded:
944 /* ARM instruction available. */ 956 /* ARM instruction available. */
945 //printf("t decode %04lx -> %08lx\n", instr & 0xffff, new); 957 //printf("t decode %04lx -> %08lx\n", instr & 0xffff, armOp);
946 instr = new_instr; 958
959 if (armOp == 0xDEADC0DE)
960 {
961 DEBUG("Failed to decode thumb opcode %04X at %08X\n", instr, pc);
962 }
963
964 instr = armOp;
965
947 /* So continue instruction decoding. */ 966 /* So continue instruction decoding. */
948 break; 967 break;
949 default: 968 default:
@@ -969,11 +988,11 @@ ARMul_Emulate26 (ARMul_State * state)
969 if (state->is_v7) { 988 if (state->is_v7) {
970 if ((instr & 0x0fffff00) == 0x057ff000) { 989 if ((instr & 0x0fffff00) == 0x057ff000) {
971 switch((instr >> 4) & 0xf) { 990 switch((instr >> 4) & 0xf) {
972 case 4: /* dsb */ 991 case 4: /* dsb */
973 case 5: /* dmb */ 992 case 5: /* dmb */
974 case 6: /* isb */ 993 case 6: /* isb */
975 // TODO: do no implemented thes instr 994 // TODO: do no implemented thes instr
976 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext; 995 goto donext;
977 } 996 }
978 } 997 }
979 } 998 }
@@ -982,17 +1001,16 @@ ARMul_Emulate26 (ARMul_State * state)
982 /* clrex do nothing here temporary */ 1001 /* clrex do nothing here temporary */
983 if (instr == 0xf57ff01f) { 1002 if (instr == 0xf57ff01f) {
984 //printf("clrex \n"); 1003 //printf("clrex \n");
985 ERROR_LOG(ARM11, "Instr = 0x%x, pc = 0x%x, clrex instr!!\n", instr, pc);
986#if 0 1004#if 0
987 int i; 1005 int i;
988 for(i = 0; i < 128; i++){ 1006 for(i = 0; i < 128; i++) {
989 state->exclusive_tag_array[i] = 0xffffffff; 1007 state->exclusive_tag_array[i] = 0xffffffff;
990 } 1008 }
991#endif 1009#endif
992 /* shenoubang 2012-3-14 refer the dyncom_interpreter */ 1010 /* shenoubang 2012-3-14 refer the dyncom_interpreter */
993 state->exclusive_tag_array[0] = 0xFFFFFFFF; 1011 state->exclusive_tag_array[0] = 0xFFFFFFFF;
994 state->exclusive_access_state = 0; 1012 state->exclusive_access_state = 0;
995 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext; 1013 goto donext;
996 } 1014 }
997 1015
998 if (BITS(20, 27) == 0x10) { 1016 if (BITS(20, 27) == 0x10) {
@@ -1022,18 +1040,15 @@ ARMul_Emulate26 (ARMul_State * state)
1022 state->Cpsr |= BITS(0, 4); 1040 state->Cpsr |= BITS(0, 4);
1023 printf("skyeye test state->Mode\n"); 1041 printf("skyeye test state->Mode\n");
1024 if (state->Mode != (state->Cpsr & MODEBITS)) { 1042 if (state->Mode != (state->Cpsr & MODEBITS)) {
1025 state->Mode = 1043 state->Mode = ARMul_SwitchMode (state, state->Mode, state->Cpsr & MODEBITS);
1026 ARMul_SwitchMode (state, state->Mode,
1027 state->Cpsr & MODEBITS);
1028
1029 state->NtransSig = (state->Mode & 3) ? HIGH : LOW; 1044 state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
1030 } 1045 }
1031 } 1046 }
1032 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext; 1047 goto donext;
1033 } 1048 }
1034 } 1049 }
1035 if (state->is_v5) { 1050 if (state->is_v5) {
1036 if (BITS (25, 27) == 5) { /* BLX(1) */ 1051 if (BITS (25, 27) == 5) { /* BLX(1) */
1037 ARMword dest; 1052 ARMword dest;
1038 1053
1039 state->Reg[14] = pc + 4; 1054 state->Reg[14] = pc + 4;
@@ -1042,25 +1057,22 @@ ARMul_Emulate26 (ARMul_State * state)
1042 dest = pc + 8 + 1; 1057 dest = pc + 8 + 1;
1043 if (BIT (23)) 1058 if (BIT (23))
1044 dest += (NEGBRANCH + 1059 dest += (NEGBRANCH +
1045 (BIT (24) << 1)); 1060 (BIT (24) << 1));
1046 else 1061 else
1047 dest += POSBRANCH + 1062 dest += POSBRANCH +
1048 (BIT (24) << 1); 1063 (BIT (24) << 1);
1049 1064
1050 WriteR15Branch (state, dest); 1065 WriteR15Branch (state, dest);
1051 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext; 1066 goto donext;
1052 } 1067 } else if ((instr & 0xFC70F000) == 0xF450F000) {
1053 else if ((instr & 0xFC70F000) == 0xF450F000) {
1054 /* The PLD instruction. Ignored. */ 1068 /* The PLD instruction. Ignored. */
1055 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext; 1069 goto donext;
1056 } 1070 } else if (((instr & 0xfe500f00) == 0xfc100100)
1057 else if (((instr & 0xfe500f00) == 0xfc100100) 1071 || ((instr & 0xfe500f00) ==
1058 || ((instr & 0xfe500f00) == 1072 0xfc000100)) {
1059 0xfc000100)) {
1060 /* wldrw and wstrw are unconditional. */ 1073 /* wldrw and wstrw are unconditional. */
1061 goto mainswitch; 1074 goto mainswitch;
1062 } 1075 } else {
1063 else {
1064 /* UNDEFINED in v5, UNPREDICTABLE in v3, v4, non executed in v1, v2. */ 1076 /* UNDEFINED in v5, UNPREDICTABLE in v3, v4, non executed in v1, v2. */
1065 ARMul_UndefInstr (state, instr); 1077 ARMul_UndefInstr (state, instr);
1066 } 1078 }
@@ -1105,206 +1117,20 @@ ARMul_Emulate26 (ARMul_State * state)
1105 break; 1117 break;
1106 case GT: 1118 case GT:
1107 temp = ((!NFLAG && !VFLAG && !ZFLAG) 1119 temp = ((!NFLAG && !VFLAG && !ZFLAG)
1108 || (NFLAG && VFLAG && !ZFLAG)); 1120 || (NFLAG && VFLAG && !ZFLAG));
1109 break; 1121 break;
1110 case LE: 1122 case LE:
1111 temp = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG)) 1123 temp = ((NFLAG && !VFLAG) || (!NFLAG && VFLAG))
1112 || ZFLAG; 1124 || ZFLAG;
1113 break; 1125 break;
1114 } /* cc check */ 1126 } /* cc check */
1115 1127
1116//chy 2003-08-24 now #if 0 .... #endif process cp14, cp15.reg14, I disable it... 1128//chy 2003-08-24 now #if 0 .... #endif process cp14, cp15.reg14, I disable it...
1117#if 0
1118 /* Handle the Clock counter here. */
1119 if (state->is_XScale) {
1120 ARMword cp14r0;
1121 int ok;
1122
1123 ok = state->CPRead[14] (state, 0, &cp14r0);
1124
1125 if (ok && (cp14r0 & ARMul_CP14_R0_ENABLE)) {
1126 unsigned int newcycles, nowtime =
1127 ARMul_Time (state);
1128
1129 newcycles = nowtime - state->LastTime;
1130 state->LastTime = nowtime;
1131
1132 if (cp14r0 & ARMul_CP14_R0_CCD) {
1133 if (state->CP14R0_CCD == -1)
1134 state->CP14R0_CCD = newcycles;
1135 else
1136 state->CP14R0_CCD +=
1137 newcycles;
1138
1139 if (state->CP14R0_CCD >= 64) {
1140 newcycles = 0;
1141
1142 while (state->CP14R0_CCD >=
1143 64)
1144 state->CP14R0_CCD -=
1145 64,
1146 newcycles++;
1147
1148 goto check_PMUintr;
1149 }
1150 }
1151 else {
1152 ARMword cp14r1;
1153 int do_int = 0;
1154
1155 state->CP14R0_CCD = -1;
1156 check_PMUintr:
1157 cp14r0 |= ARMul_CP14_R0_FLAG2;
1158 (void) state->CPWrite[14] (state, 0,
1159 cp14r0);
1160
1161 ok = state->CPRead[14] (state, 1,
1162 &cp14r1);
1163
1164 /* Coded like this for portability. */
1165 while (ok && newcycles) {
1166 if (cp14r1 == 0xffffffff) {
1167 cp14r1 = 0;
1168 do_int = 1;
1169 }
1170 else
1171 cp14r1++;
1172
1173 newcycles--;
1174 }
1175
1176 (void) state->CPWrite[14] (state, 1,
1177 cp14r1);
1178
1179 if (do_int
1180 && (cp14r0 &
1181 ARMul_CP14_R0_INTEN2)) {
1182 ARMword temp;
1183
1184 if (state->
1185 CPRead[13] (state, 8,
1186 &temp)
1187 && (temp &
1188 ARMul_CP13_R8_PMUS))
1189 ARMul_Abort (state,
1190 ARMul_FIQV);
1191 else
1192 ARMul_Abort (state,
1193 ARMul_IRQV);
1194 }
1195 }
1196 }
1197 }
1198
1199 /* Handle hardware instructions breakpoints here. */
1200 if (state->is_XScale) {
1201 if ((pc | 3) == (read_cp15_reg (14, 0, 8) | 2)
1202 || (pc | 3) == (read_cp15_reg (14, 0, 9) | 2)) {
1203 if (XScale_debug_moe
1204 (state, ARMul_CP14_R10_MOE_IB))
1205 ARMul_OSHandleSWI (state,
1206 SWI_Breakpoint);
1207 }
1208 }
1209#endif
1210 1129
1211 /* Actual execution of instructions begins here. */ 1130 /* Actual execution of instructions begins here. */
1212 /* If the condition codes don't match, stop here. */ 1131 /* If the condition codes don't match, stop here. */
1213 if (temp) { 1132 if (temp) {
1214 mainswitch: 1133mainswitch:
1215
1216 if (state->is_XScale) {
1217 if (BIT (20) == 0 && BITS (25, 27) == 0) {
1218 if (BITS (4, 7) == 0xD) {
1219 /* XScale Load Consecutive insn. */
1220 ARMword temp =
1221 GetLS7RHS (state,
1222 instr);
1223 ARMword temp2 =
1224 BIT (23) ? LHS +
1225 temp : LHS - temp;
1226 ARMword addr =
1227 BIT (24) ? temp2 :
1228 LHS;
1229
1230 if (BIT (12))
1231 ARMul_UndefInstr
1232 (state,
1233 instr);
1234 else if (addr & 7)
1235 /* Alignment violation. */
1236 ARMul_Abort (state,
1237 ARMul_DataAbortV);
1238 else {
1239 int wb = BIT (21)
1240 ||
1241 (!BIT (24));
1242
1243 state->Reg[BITS
1244 (12, 15)] =
1245 ARMul_LoadWordN
1246 (state, addr);
1247 state->Reg[BITS
1248 (12,
1249 15) + 1] =
1250 ARMul_LoadWordN
1251 (state,
1252 addr + 4);
1253 if (wb)
1254 LSBase = temp2;
1255 }
1256
1257 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext;
1258 }
1259 else if (BITS (4, 7) == 0xF) {
1260 /* XScale Store Consecutive insn. */
1261 ARMword temp =
1262 GetLS7RHS (state,
1263 instr);
1264 ARMword temp2 =
1265 BIT (23) ? LHS +
1266 temp : LHS - temp;
1267 ARMword addr =
1268 BIT (24) ? temp2 :
1269 LHS;
1270
1271 if (BIT (12))
1272 ARMul_UndefInstr
1273 (state,
1274 instr);
1275 else if (addr & 7)
1276 /* Alignment violation. */
1277 ARMul_Abort (state,
1278 ARMul_DataAbortV);
1279 else {
1280 ARMul_StoreWordN
1281 (state, addr,
1282 state->
1283 Reg[BITS
1284 (12,
1285 15)]);
1286 ARMul_StoreWordN
1287 (state,
1288 addr + 4,
1289 state->
1290 Reg[BITS
1291 (12,
1292 15) +
1293 1]);
1294
1295 if (BIT (21)
1296 || !BIT (24))
1297 LSBase = temp2;
1298 }
1299
1300 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext;
1301 }
1302 }
1303 //chy 2003-09-03 TMRRC(iwmmxt.c) and MRA has the same decoded instr????
1304 //Now, I commit iwmmxt process, may be future, I will change it!!!!
1305 //if (ARMul_HandleIwmmxt (state, instr))
1306 // _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext;
1307 }
1308 1134
1309 /* shenoubang sbfx and ubfx instr 2012-3-16 */ 1135 /* shenoubang sbfx and ubfx instr 2012-3-16 */
1310 if (state->is_v6) { 1136 if (state->is_v6) {
@@ -1319,52 +1145,51 @@ ARMul_Emulate26 (ARMul_State * state)
1319 Rn = (unsigned)BITS(0, 3); 1145 Rn = (unsigned)BITS(0, 3);
1320 if ((Rd == 15) || (Rn == 15)) { 1146 if ((Rd == 15) || (Rn == 15)) {
1321 ARMul_UndefInstr (state, instr); 1147 ARMul_UndefInstr (state, instr);
1322 } 1148 } else if ((m + width) < 32) {
1323 else if ((m + width) < 32) {
1324 data = state->Reg[Rn]; 1149 data = state->Reg[Rn];
1325 state->Reg[Rd] ^= state->Reg[Rd]; 1150 state->Reg[Rd] ^= state->Reg[Rd];
1326 state->Reg[Rd] = 1151 state->Reg[Rd] = ((ARMword)(data << (31 -(m + width))) >> ((31 - (m + width)) + (m)));
1327 ((ARMword)(data << (31 -(m + width))) >> ((31 - (m + width)) + (m)));
1328 //SKYEYE_LOG_IN_CLR(RED, "UBFX: In %s, line = %d, Reg_src[%d] = 0x%x, Reg_d[%d] = 0x%x, m = %d, width = %d, Rd = %d, Rn = %d\n", 1152 //SKYEYE_LOG_IN_CLR(RED, "UBFX: In %s, line = %d, Reg_src[%d] = 0x%x, Reg_d[%d] = 0x%x, m = %d, width = %d, Rd = %d, Rn = %d\n",
1329 // __FUNCTION__, __LINE__, Rn, data, Rd, state->Reg[Rd], m, width + 1, Rd, Rn); 1153 // __FUNCTION__, __LINE__, Rn, data, Rd, state->Reg[Rd], m, width + 1, Rd, Rn);
1330 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext; 1154 goto donext;
1331 } 1155 }
1332 } // ubfx instr 1156 } // ubfx instr
1333 else if ((((int) BITS (21, 27)) == 0x3d) && (((int) BITS (4, 6)) == 0x5)) { 1157 else if ((((int) BITS (21, 27)) == 0x3d) && (((int) BITS (4, 6)) == 0x5)) {
1334 int tmp = 0; 1158 int tmp = 0;
1335 Rd = BITS(12, 15); Rn = BITS(0, 3); 1159 Rd = BITS(12, 15);
1336 lsb = BITS(7, 11); width = BITS(16, 20); 1160 Rn = BITS(0, 3);
1161 lsb = BITS(7, 11);
1162 width = BITS(16, 20);
1337 if ((Rd == 15) || (Rn == 15)) { 1163 if ((Rd == 15) || (Rn == 15)) {
1338 ARMul_UndefInstr (state, instr); 1164 ARMul_UndefInstr (state, instr);
1339 } 1165 } else if ((lsb + width) < 32) {
1340 else if ((lsb + width) < 32) {
1341 state->Reg[Rd] ^= state->Reg[Rd]; 1166 state->Reg[Rd] ^= state->Reg[Rd];
1342 data = state->Reg[Rn]; 1167 data = state->Reg[Rn];
1343 tmp = (data << (32 - (lsb + width + 1))); 1168 tmp = (data << (32 - (lsb + width + 1)));
1344 state->Reg[Rd] = (tmp >> (32 - (lsb + width + 1))); 1169 state->Reg[Rd] = (tmp >> (32 - (lsb + width + 1)));
1345 //SKYEYE_LOG_IN_CLR(RED, "sbfx: In %s, line = %d, pc = 0x%x, instr = 0x%x,Rd = 0x%x, \ 1170 //SKYEYE_LOG_IN_CLR(RED, "sbfx: In %s, line = %d, pc = 0x%x, instr = 0x%x,Rd = 0x%x, Rn = 0x%x, lsb = %d, width = %d, Rs[%d] = 0x%x, Rd[%d] = 0x%x\n",
1346 Rn = 0x%x, lsb = %d, width = %d, Rs[%d] = 0x%x, Rd[%d] = 0x%x\n", 1171 // __func__, __LINE__, pc, instr, Rd, Rn, lsb, width + 1, Rn, state->Reg[Rn], Rd, state->Reg[Rd]);
1347 // __func__, __LINE__, pc, instr, Rd, Rn, lsb, width + 1, Rn, state->Reg[Rn], Rd, state->Reg[Rd]); 1172 goto donext;
1348 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext;
1349 } 1173 }
1350 } // sbfx instr 1174 } // sbfx instr
1351 else if ((((int)BITS(21, 27)) == 0x3e) && ((int)BITS(4, 6) == 0x1)) { 1175 else if ((((int)BITS(21, 27)) == 0x3e) && ((int)BITS(4, 6) == 0x1)) {
1352 //(ARMword)(instr<<(31-(n))) >> ((31-(n))+(m)) 1176 //(ARMword)(instr<<(31-(n))) >> ((31-(n))+(m))
1353 unsigned msb ,tmp_rn, tmp_rd, dst; 1177 unsigned msb ,tmp_rn, tmp_rd, dst;
1354 msb = tmp_rd = tmp_rn = dst = 0; 1178 msb = tmp_rd = tmp_rn = dst = 0;
1355 Rd = BITS(12, 15); Rn = BITS(0, 3); 1179 Rd = BITS(12, 15);
1356 lsb = BITS(7, 11); msb = BITS(16, 20); 1180 Rn = BITS(0, 3);
1181 lsb = BITS(7, 11);
1182 msb = BITS(16, 20); //-V519
1357 if ((Rd == 15)) { 1183 if ((Rd == 15)) {
1358 ARMul_UndefInstr (state, instr); 1184 ARMul_UndefInstr (state, instr);
1359 } 1185 } else if ((Rn == 15)) {
1360 else if ((Rn == 15)) {
1361 data = state->Reg[Rd]; 1186 data = state->Reg[Rd];
1362 tmp_rd = ((ARMword)(data << (31 - lsb)) >> (31 - lsb)); 1187 tmp_rd = ((ARMword)(data << (31 - lsb)) >> (31 - lsb));
1363 dst = ((data >> msb) << (msb - lsb)); 1188 dst = ((data >> msb) << (msb - lsb));
1364 dst = (dst << lsb) | tmp_rd; 1189 dst = (dst << lsb) | tmp_rd;
1365 DEBUG_LOG(ARM11, "BFC instr: msb = %d, lsb = %d, Rd[%d] : 0x%x, dst = 0x%x\n", 1190 /*SKYEYE_DBG("BFC instr: msb = %d, lsb = %d, Rd[%d] : 0x%x, dst = 0x%x\n",
1366 msb, lsb, Rd, state->Reg[Rd], dst); 1191 msb, lsb, Rd, state->Reg[Rd], dst);*/
1367 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext; 1192 goto donext;
1368 } // bfc instr 1193 } // bfc instr
1369 else if (((msb >= lsb) && (msb < 32))) { 1194 else if (((msb >= lsb) && (msb < 32))) {
1370 data = state->Reg[Rn]; 1195 data = state->Reg[Rn];
@@ -1373,17 +1198,17 @@ ARMul_Emulate26 (ARMul_State * state)
1373 tmp_rd = ((ARMword)(data << (31 - lsb)) >> (31 - lsb)); 1198 tmp_rd = ((ARMword)(data << (31 - lsb)) >> (31 - lsb));
1374 dst = ((data >> msb) << (msb - lsb)) | tmp_rn; 1199 dst = ((data >> msb) << (msb - lsb)) | tmp_rn;
1375 dst = (dst << lsb) | tmp_rd; 1200 dst = (dst << lsb) | tmp_rd;
1376 DEBUG_LOG(ARM11, "BFI instr:msb = %d, lsb = %d, Rd[%d] : 0x%x, Rn[%d]: 0x%x, dst = 0x%x\n", 1201 /*SKYEYE_DBG("BFI instr:msb = %d, lsb = %d, Rd[%d] : 0x%x, Rn[%d]: 0x%x, dst = 0x%x\n",
1377 msb, lsb, Rd, state->Reg[Rd], Rn, state->Reg[Rn], dst); 1202 msb, lsb, Rd, state->Reg[Rd], Rn, state->Reg[Rn], dst);*/
1378 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext; 1203 goto donext;
1379 } // bfi instr 1204 } // bfi instr
1380 } 1205 }
1381 } 1206 }
1382 1207
1383 switch ((int) BITS (20, 27)) { 1208 switch ((int) BITS (20, 27)) {
1384 /* Data Processing Register RHS Instructions. */ 1209 /* Data Processing Register RHS Instructions. */
1385 1210
1386 case 0x00: /* AND reg and MUL */ 1211 case 0x00: /* AND reg and MUL */
1387#ifdef MODET 1212#ifdef MODET
1388 if (BITS (4, 11) == 0xB) { 1213 if (BITS (4, 11) == 0xB) {
1389 /* STRH register offset, no write-back, down, post indexed. */ 1214 /* STRH register offset, no write-back, down, post indexed. */
@@ -1403,28 +1228,22 @@ ARMul_Emulate26 (ARMul_State * state)
1403 /* MUL */ 1228 /* MUL */
1404 rhs = state->Reg[MULRHSReg]; 1229 rhs = state->Reg[MULRHSReg];
1405 //if (MULLHSReg == MULDESTReg) { 1230 //if (MULLHSReg == MULDESTReg) {
1406 if(0){ /* For armv6, the restriction is removed */ 1231 if(0) { /* For armv6, the restriction is removed */
1407 UNDEF_MULDestEQOp1; 1232 UNDEF_MULDestEQOp1;
1408 state->Reg[MULDESTReg] = 0; 1233 state->Reg[MULDESTReg] = 0;
1409 } 1234 } else if (MULDESTReg != 15)
1410 else if (MULDESTReg != 15) 1235 state->Reg[MULDESTReg] = state->Reg[MULLHSReg] * rhs;
1411 state->Reg[MULDESTReg] =
1412 state->
1413 Reg[MULLHSReg] * rhs;
1414 else 1236 else
1415 UNDEF_MULPCDest; 1237 UNDEF_MULPCDest;
1416 1238
1417 for (dest = 0, temp = 0; dest < 32; 1239 for (dest = 0, temp = 0; dest < 32;
1418 dest++) 1240 dest++)
1419 if (rhs & (1L << dest)) 1241 if (rhs & (1L << dest))
1420 temp = dest; 1242 temp = dest;
1421 1243
1422 /* Mult takes this many/2 I cycles. */ 1244 /* Mult takes this many/2 I cycles. */
1423 ARMul_Icycles (state, 1245 ARMul_Icycles (state, ARMul_MultTable[temp], 0L);
1424 ARMul_MultTable[temp], 1246 } else {
1425 0L);
1426 }
1427 else {
1428 /* AND reg. */ 1247 /* AND reg. */
1429 rhs = DPRegRHS; 1248 rhs = DPRegRHS;
1430 dest = LHS & rhs; 1249 dest = LHS & rhs;
@@ -1432,7 +1251,7 @@ ARMul_Emulate26 (ARMul_State * state)
1432 } 1251 }
1433 break; 1252 break;
1434 1253
1435 case 0x01: /* ANDS reg and MULS */ 1254 case 0x01: /* ANDS reg and MULS */
1436#ifdef MODET 1255#ifdef MODET
1437 if ((BITS (4, 11) & 0xF9) == 0x9) 1256 if ((BITS (4, 11) & 0xF9) == 0x9)
1438 /* LDR register offset, no write-back, down, post indexed. */ 1257 /* LDR register offset, no write-back, down, post indexed. */
@@ -1444,34 +1263,28 @@ ARMul_Emulate26 (ARMul_State * state)
1444 rhs = state->Reg[MULRHSReg]; 1263 rhs = state->Reg[MULRHSReg];
1445 1264
1446 //if (MULLHSReg == MULDESTReg) { 1265 //if (MULLHSReg == MULDESTReg) {
1447 if(0){ 1266 if(0) {
1448 printf("Something in %d line\n", __LINE__); 1267 printf("Something in %d line\n", __LINE__);
1449 UNDEF_WARNING; 1268 UNDEF_WARNING;
1450 UNDEF_MULDestEQOp1; 1269 UNDEF_MULDestEQOp1;
1451 state->Reg[MULDESTReg] = 0; 1270 state->Reg[MULDESTReg] = 0;
1452 CLEARN; 1271 CLEARN;
1453 SETZ; 1272 SETZ;
1454 } 1273 } else if (MULDESTReg != 15) {
1455 else if (MULDESTReg != 15) { 1274 dest = state->Reg[MULLHSReg] * rhs;
1456 dest = state->Reg[MULLHSReg] *
1457 rhs;
1458 ARMul_NegZero (state, dest); 1275 ARMul_NegZero (state, dest);
1459 state->Reg[MULDESTReg] = dest; 1276 state->Reg[MULDESTReg] = dest;
1460 } 1277 } else
1461 else
1462 UNDEF_MULPCDest; 1278 UNDEF_MULPCDest;
1463 1279
1464 for (dest = 0, temp = 0; dest < 32; 1280 for (dest = 0, temp = 0; dest < 32;
1465 dest++) 1281 dest++)
1466 if (rhs & (1L << dest)) 1282 if (rhs & (1L << dest))
1467 temp = dest; 1283 temp = dest;
1468 1284
1469 /* Mult takes this many/2 I cycles. */ 1285 /* Mult takes this many/2 I cycles. */
1470 ARMul_Icycles (state, 1286 ARMul_Icycles (state, ARMul_MultTable[temp], 0L);
1471 ARMul_MultTable[temp], 1287 } else {
1472 0L);
1473 }
1474 else {
1475 /* ANDS reg. */ 1288 /* ANDS reg. */
1476 rhs = DPSRegRHS; 1289 rhs = DPSRegRHS;
1477 dest = LHS & rhs; 1290 dest = LHS & rhs;
@@ -1479,7 +1292,7 @@ ARMul_Emulate26 (ARMul_State * state)
1479 } 1292 }
1480 break; 1293 break;
1481 1294
1482 case 0x02: /* EOR reg and MLA */ 1295 case 0x02: /* EOR reg and MLA */
1483#ifdef MODET 1296#ifdef MODET
1484 if (BITS (4, 11) == 0xB) { 1297 if (BITS (4, 11) == 0xB) {
1485 /* STRH register offset, write-back, down, post indexed. */ 1298 /* STRH register offset, write-back, down, post indexed. */
@@ -1487,3069 +1300,2603 @@ ARMul_Emulate26 (ARMul_State * state)
1487 break; 1300 break;
1488 } 1301 }
1489#endif 1302#endif
1490 if (BITS (4, 7) == 9) { /* MLA */ 1303 if (BITS (4, 7) == 9) { /* MLA */
1491 rhs = state->Reg[MULRHSReg]; 1304 rhs = state->Reg[MULRHSReg];
1492 #if 0 1305#if 0
1493 if (MULLHSReg == MULDESTReg) { 1306 if (MULLHSReg == MULDESTReg) {
1494 UNDEF_MULDestEQOp1; 1307 UNDEF_MULDestEQOp1;
1495 state->Reg[MULDESTReg] = 1308 state->Reg[MULDESTReg] = state->Reg[MULACCReg];
1496 state->Reg[MULACCReg]; 1309 } else if (MULDESTReg != 15) {
1497 } 1310#endif
1498 else if (MULDESTReg != 15){ 1311 if (MULDESTReg != 15) {
1499 #endif 1312 state->Reg[MULDESTReg] = state->Reg[MULLHSReg] * rhs + state->Reg[MULACCReg];
1500 if (MULDESTReg != 15){ 1313 } else
1501 state->Reg[MULDESTReg] = 1314 UNDEF_MULPCDest;
1502 state-> 1315
1503 Reg[MULLHSReg] * rhs + 1316 for (dest = 0, temp = 0; dest < 32;
1504 state->Reg[MULACCReg]; 1317 dest++)
1318 if (rhs & (1L << dest))
1319 temp = dest;
1320
1321 /* Mult takes this many/2 I cycles. */
1322 ARMul_Icycles (state, ARMul_MultTable[temp], 0L);
1323 } else {
1324 rhs = DPRegRHS;
1325 dest = LHS ^ rhs;
1326 WRITEDEST (dest);
1505 } 1327 }
1506 else 1328 break;
1507 UNDEF_MULPCDest;
1508 1329
1509 for (dest = 0, temp = 0; dest < 32; 1330 case 0x03: /* EORS reg and MLAS */
1510 dest++) 1331#ifdef MODET
1511 if (rhs & (1L << dest)) 1332 if ((BITS (4, 11) & 0xF9) == 0x9)
1512 temp = dest; 1333 /* LDR register offset, write-back, down, post-indexed. */
1334 LHPOSTDOWN ();
1335 /* Fall through to rest of the decoding. */
1336#endif
1337 if (BITS (4, 7) == 9) {
1338 /* MLAS */
1339 rhs = state->Reg[MULRHSReg];
1340 //if (MULLHSReg == MULDESTReg) {
1341 if (0) {
1342 UNDEF_MULDestEQOp1;
1343 dest = state->Reg[MULACCReg];
1344 ARMul_NegZero (state, dest);
1345 state->Reg[MULDESTReg] = dest;
1346 } else if (MULDESTReg != 15) {
1347 dest = state->Reg[MULLHSReg] * rhs + state->Reg[MULACCReg];
1348 ARMul_NegZero (state, dest);
1349 state->Reg[MULDESTReg] = dest;
1350 } else
1351 UNDEF_MULPCDest;
1352
1353 for (dest = 0, temp = 0; dest < 32;
1354 dest++)
1355 if (rhs & (1L << dest))
1356 temp = dest;
1357
1358 /* Mult takes this many/2 I cycles. */
1359 ARMul_Icycles (state, ARMul_MultTable[temp], 0L);
1360 } else {
1361 /* EORS Reg. */
1362 rhs = DPSRegRHS;
1363 dest = LHS ^ rhs;
1364 WRITESDEST (dest);
1365 }
1366 break;
1513 1367
1514 /* Mult takes this many/2 I cycles. */ 1368 case 0x04: /* SUB reg */
1515 ARMul_Icycles (state, 1369#ifdef MODET
1516 ARMul_MultTable[temp], 1370 if (BITS (4, 7) == 0xB) {
1517 0L); 1371 /* STRH immediate offset, no write-back, down, post indexed. */
1518 } 1372 SHDOWNWB ();
1519 else { 1373 break;
1374 }
1375 if (BITS (4, 7) == 0xD) {
1376 Handle_Load_Double (state, instr);
1377 break;
1378 }
1379 if (BITS (4, 7) == 0xF) {
1380 Handle_Store_Double (state, instr);
1381 break;
1382 }
1383#endif
1520 rhs = DPRegRHS; 1384 rhs = DPRegRHS;
1521 dest = LHS ^ rhs; 1385 dest = LHS - rhs;
1522 WRITEDEST (dest); 1386 WRITEDEST (dest);
1523 } 1387 break;
1524 break;
1525 1388
1526 case 0x03: /* EORS reg and MLAS */ 1389 case 0x05: /* SUBS reg */
1527#ifdef MODET 1390#ifdef MODET
1528 if ((BITS (4, 11) & 0xF9) == 0x9) 1391 if ((BITS (4, 7) & 0x9) == 0x9)
1529 /* LDR register offset, write-back, down, post-indexed. */ 1392 /* LDR immediate offset, no write-back, down, post indexed. */
1530 LHPOSTDOWN (); 1393 LHPOSTDOWN ();
1531 /* Fall through to rest of the decoding. */ 1394 /* Fall through to the rest of the instruction decoding. */
1532#endif 1395#endif
1533 if (BITS (4, 7) == 9) { 1396 lhs = LHS;
1534 /* MLAS */ 1397 rhs = DPRegRHS;
1535 rhs = state->Reg[MULRHSReg]; 1398 dest = lhs - rhs;
1536 //if (MULLHSReg == MULDESTReg) {
1537 if (0) {
1538 UNDEF_MULDestEQOp1;
1539 dest = state->Reg[MULACCReg];
1540 ARMul_NegZero (state, dest);
1541 state->Reg[MULDESTReg] = dest;
1542 }
1543 else if (MULDESTReg != 15) {
1544 dest = state->Reg[MULLHSReg] *
1545 rhs +
1546 state->Reg[MULACCReg];
1547 ARMul_NegZero (state, dest);
1548 state->Reg[MULDESTReg] = dest;
1549 }
1550 else
1551 UNDEF_MULPCDest;
1552
1553 for (dest = 0, temp = 0; dest < 32;
1554 dest++)
1555 if (rhs & (1L << dest))
1556 temp = dest;
1557 1399
1558 /* Mult takes this many/2 I cycles. */ 1400 if ((lhs >= rhs) || ((rhs | lhs) >> 31)) {
1559 ARMul_Icycles (state, 1401 ARMul_SubCarry (state, lhs, rhs, dest);
1560 ARMul_MultTable[temp], 1402 ARMul_SubOverflow (state, lhs, rhs, dest);
1561 0L); 1403 } else {
1562 } 1404 CLEARC;
1563 else { 1405 CLEARV;
1564 /* EORS Reg. */ 1406 }
1565 rhs = DPSRegRHS;
1566 dest = LHS ^ rhs;
1567 WRITESDEST (dest); 1407 WRITESDEST (dest);
1568 } 1408 break;
1569 break;
1570 1409
1571 case 0x04: /* SUB reg */ 1410 case 0x06: /* RSB reg */
1572#ifdef MODET 1411#ifdef MODET
1573 if (BITS (4, 7) == 0xB) { 1412 if (BITS (4, 7) == 0xB) {
1574 /* STRH immediate offset, no write-back, down, post indexed. */ 1413 /* STRH immediate offset, write-back, down, post indexed. */
1575 SHDOWNWB (); 1414 SHDOWNWB ();
1576 break; 1415 break;
1577 } 1416 }
1578 if (BITS (4, 7) == 0xD) {
1579 Handle_Load_Double (state, instr);
1580 break;
1581 }
1582 if (BITS (4, 7) == 0xF) {
1583 Handle_Store_Double (state, instr);
1584 break;
1585 }
1586#endif 1417#endif
1587 rhs = DPRegRHS; 1418 rhs = DPRegRHS;
1588 dest = LHS - rhs; 1419 dest = rhs - LHS;
1589 WRITEDEST (dest); 1420 WRITEDEST (dest);
1590 break; 1421 break;
1591 1422
1592 case 0x05: /* SUBS reg */ 1423 case 0x07: /* RSBS reg */
1593#ifdef MODET 1424#ifdef MODET
1594 if ((BITS (4, 7) & 0x9) == 0x9) 1425 if ((BITS (4, 7) & 0x9) == 0x9)
1595 /* LDR immediate offset, no write-back, down, post indexed. */ 1426 /* LDR immediate offset, write-back, down, post indexed. */
1596 LHPOSTDOWN (); 1427 LHPOSTDOWN ();
1597 /* Fall through to the rest of the instruction decoding. */ 1428 /* Fall through to remainder of instruction decoding. */
1598#endif 1429#endif
1599 lhs = LHS; 1430 lhs = LHS;
1600 rhs = DPRegRHS; 1431 rhs = DPRegRHS;
1601 dest = lhs - rhs; 1432 dest = rhs - lhs;
1602
1603 if ((lhs >= rhs) || ((rhs | lhs) >> 31)) {
1604 ARMul_SubCarry (state, lhs, rhs,
1605 dest);
1606 ARMul_SubOverflow (state, lhs, rhs,
1607 dest);
1608 }
1609 else {
1610 CLEARC;
1611 CLEARV;
1612 }
1613 WRITESDEST (dest);
1614 break;
1615 1433
1616 case 0x06: /* RSB reg */ 1434 if ((rhs >= lhs) || ((rhs | lhs) >> 31)) {
1617#ifdef MODET 1435 ARMul_SubCarry (state, rhs, lhs, dest);
1618 if (BITS (4, 7) == 0xB) { 1436 ARMul_SubOverflow (state, rhs, lhs, dest);
1619 /* STRH immediate offset, write-back, down, post indexed. */ 1437 } else {
1620 SHDOWNWB (); 1438 CLEARC;
1439 CLEARV;
1440 }
1441 WRITESDEST (dest);
1621 break; 1442 break;
1622 }
1623#endif
1624 rhs = DPRegRHS;
1625 dest = rhs - LHS;
1626 WRITEDEST (dest);
1627 break;
1628 1443
1629 case 0x07: /* RSBS reg */ 1444 case 0x08: /* ADD reg */
1630#ifdef MODET 1445#ifdef MODET
1631 if ((BITS (4, 7) & 0x9) == 0x9) 1446 if (BITS (4, 11) == 0xB) {
1632 /* LDR immediate offset, write-back, down, post indexed. */ 1447 /* STRH register offset, no write-back, up, post indexed. */
1633 LHPOSTDOWN (); 1448 SHUPWB ();
1634 /* Fall through to remainder of instruction decoding. */ 1449 break;
1450 }
1451 if (BITS (4, 7) == 0xD) {
1452 Handle_Load_Double (state, instr);
1453 break;
1454 }
1455 if (BITS (4, 7) == 0xF) {
1456 Handle_Store_Double (state, instr);
1457 break;
1458 }
1635#endif 1459#endif
1636 lhs = LHS;
1637 rhs = DPRegRHS;
1638 dest = rhs - lhs;
1639
1640 if ((rhs >= lhs) || ((rhs | lhs) >> 31)) {
1641 ARMul_SubCarry (state, rhs, lhs,
1642 dest);
1643 ARMul_SubOverflow (state, rhs, lhs,
1644 dest);
1645 }
1646 else {
1647 CLEARC;
1648 CLEARV;
1649 }
1650 WRITESDEST (dest);
1651 break;
1652
1653 case 0x08: /* ADD reg */
1654#ifdef MODET 1460#ifdef MODET
1655 if (BITS (4, 11) == 0xB) { 1461 if (BITS (4, 7) == 0x9) {
1656 /* STRH register offset, no write-back, up, post indexed. */ 1462 /* MULL */
1657 SHUPWB (); 1463 /* 32x32 = 64 */
1658 break; 1464 ARMul_Icycles (state, Multiply64 (state, instr, LUNSIGNED, LDEFAULT), 0L);
1659 } 1465 break;
1660 if (BITS (4, 7) == 0xD) { 1466 }
1661 Handle_Load_Double (state, instr);
1662 break;
1663 }
1664 if (BITS (4, 7) == 0xF) {
1665 Handle_Store_Double (state, instr);
1666 break;
1667 }
1668#endif 1467#endif
1669#ifdef MODET 1468 rhs = DPRegRHS;
1670 if (BITS (4, 7) == 0x9) { 1469 dest = LHS + rhs;
1671 /* MULL */ 1470 WRITEDEST (dest);
1672 /* 32x32 = 64 */
1673 ARMul_Icycles (state,
1674 Multiply64 (state,
1675 instr,
1676 LUNSIGNED,
1677 LDEFAULT),
1678 0L);
1679 break; 1471 break;
1680 }
1681#endif
1682 rhs = DPRegRHS;
1683 dest = LHS + rhs;
1684 WRITEDEST (dest);
1685 break;
1686 1472
1687 case 0x09: /* ADDS reg */ 1473 case 0x09: /* ADDS reg */
1688#ifdef MODET 1474#ifdef MODET
1689 if ((BITS (4, 11) & 0xF9) == 0x9) 1475 if ((BITS (4, 11) & 0xF9) == 0x9)
1690 /* LDR register offset, no write-back, up, post indexed. */ 1476 /* LDR register offset, no write-back, up, post indexed. */
1691 LHPOSTUP (); 1477 LHPOSTUP ();
1692 /* Fall through to remaining instruction decoding. */ 1478 /* Fall through to remaining instruction decoding. */
1693#endif 1479#endif
1694#ifdef MODET 1480#ifdef MODET
1695 if (BITS (4, 7) == 0x9) { 1481 if (BITS (4, 7) == 0x9) {
1696 /* MULL */ 1482 /* MULL */
1697 /* 32x32=64 */ 1483 /* 32x32=64 */
1698 ARMul_Icycles (state, 1484 ARMul_Icycles (state, Multiply64 (state, instr, LUNSIGNED, LSCC), 0L);
1699 Multiply64 (state, 1485 break;
1700 instr, 1486 }
1701 LUNSIGNED,
1702 LSCC), 0L);
1703 break;
1704 }
1705#endif 1487#endif
1706 lhs = LHS; 1488 lhs = LHS;
1707 rhs = DPRegRHS; 1489 rhs = DPRegRHS;
1708 dest = lhs + rhs; 1490 dest = lhs + rhs;
1709 ASSIGNZ (dest == 0); 1491 ASSIGNZ (dest == 0);
1710 if ((lhs | rhs) >> 30) { 1492 if ((lhs | rhs) >> 30) {
1711 /* Possible C,V,N to set. */ 1493 /* Possible C,V,N to set. */
1712 ASSIGNN (NEG (dest)); 1494 ASSIGNN (NEG (dest));
1713 ARMul_AddCarry (state, lhs, rhs, 1495 ARMul_AddCarry (state, lhs, rhs, dest);
1714 dest); 1496 ARMul_AddOverflow (state, lhs, rhs, dest);
1715 ARMul_AddOverflow (state, lhs, rhs, 1497 } else {
1716 dest); 1498 CLEARN;
1717 } 1499 CLEARC;
1718 else { 1500 CLEARV;
1719 CLEARN; 1501 }
1720 CLEARC; 1502 WRITESDEST (dest);
1721 CLEARV; 1503 break;
1722 }
1723 WRITESDEST (dest);
1724 break;
1725 1504
1726 case 0x0a: /* ADC reg */ 1505 case 0x0a: /* ADC reg */
1727#ifdef MODET 1506#ifdef MODET
1728 if (BITS (4, 11) == 0xB) { 1507 if (BITS (4, 11) == 0xB) {
1729 /* STRH register offset, write-back, up, post-indexed. */ 1508 /* STRH register offset, write-back, up, post-indexed. */
1730 SHUPWB (); 1509 SHUPWB ();
1731 break; 1510 break;
1732 } 1511 }
1733 if (BITS (4, 7) == 0x9) { 1512 if (BITS (4, 7) == 0x9) {
1734 /* MULL */ 1513 /* MULL */
1735 /* 32x32=64 */ 1514 /* 32x32=64 */
1736 ARMul_Icycles (state, 1515 ARMul_Icycles (state, MultiplyAdd64 (state, instr, LUNSIGNED, LDEFAULT), 0L);
1737 MultiplyAdd64 (state, 1516 break;
1738 instr, 1517 }
1739 LUNSIGNED,
1740 LDEFAULT),
1741 0L);
1742 break;
1743 }
1744#endif 1518#endif
1745 rhs = DPRegRHS; 1519 rhs = DPRegRHS;
1746 dest = LHS + rhs + CFLAG; 1520 dest = LHS + rhs + CFLAG;
1747 WRITEDEST (dest); 1521 WRITEDEST (dest);
1748 break; 1522 break;
1749 1523
1750 case 0x0b: /* ADCS reg */ 1524 case 0x0b: /* ADCS reg */
1751#ifdef MODET 1525#ifdef MODET
1752 if ((BITS (4, 11) & 0xF9) == 0x9) 1526 if ((BITS (4, 11) & 0xF9) == 0x9)
1753 /* LDR register offset, write-back, up, post indexed. */ 1527 /* LDR register offset, write-back, up, post indexed. */
1754 LHPOSTUP (); 1528 LHPOSTUP ();
1755 /* Fall through to remaining instruction decoding. */ 1529 /* Fall through to remaining instruction decoding. */
1756 if (BITS (4, 7) == 0x9) { 1530 if (BITS (4, 7) == 0x9) {
1757 /* MULL */ 1531 /* MULL */
1758 /* 32x32=64 */ 1532 /* 32x32=64 */
1759 ARMul_Icycles (state, 1533 ARMul_Icycles (state, MultiplyAdd64 (state, instr, LUNSIGNED, LSCC), 0L);
1760 MultiplyAdd64 (state, 1534 break;
1761 instr, 1535 }
1762 LUNSIGNED,
1763 LSCC),
1764 0L);
1765 break;
1766 }
1767#endif 1536#endif
1768 lhs = LHS; 1537 lhs = LHS;
1769 rhs = DPRegRHS; 1538 rhs = DPRegRHS;
1770 dest = lhs + rhs + CFLAG; 1539 dest = lhs + rhs + CFLAG;
1771 ASSIGNZ (dest == 0); 1540 ASSIGNZ (dest == 0);
1772 if ((lhs | rhs) >> 30) { 1541 if ((lhs | rhs) >> 30) {
1773 /* Possible C,V,N to set. */ 1542 /* Possible C,V,N to set. */
1774 ASSIGNN (NEG (dest)); 1543 ASSIGNN (NEG (dest));
1775 ARMul_AddCarry (state, lhs, rhs, 1544 ARMul_AddCarry (state, lhs, rhs, dest);
1776 dest); 1545 ARMul_AddOverflow (state, lhs, rhs, dest);
1777 ARMul_AddOverflow (state, lhs, rhs, 1546 } else {
1778 dest); 1547 CLEARN;
1779 } 1548 CLEARC;
1780 else { 1549 CLEARV;
1781 CLEARN; 1550 }
1782 CLEARC; 1551 WRITESDEST (dest);
1783 CLEARV; 1552 break;
1784 }
1785 WRITESDEST (dest);
1786 break;
1787 1553
1788 case 0x0c: /* SBC reg */ 1554 case 0x0c: /* SBC reg */
1789#ifdef MODET 1555#ifdef MODET
1790 if (BITS (4, 7) == 0xB) { 1556 if (BITS (4, 7) == 0xB) {
1791 /* STRH immediate offset, no write-back, up post indexed. */ 1557 /* STRH immediate offset, no write-back, up post indexed. */
1792 SHUPWB (); 1558 SHUPWB ();
1793 break; 1559 break;
1794 } 1560 }
1795 if (BITS (4, 7) == 0xD) { 1561 if (BITS (4, 7) == 0xD) {
1796 Handle_Load_Double (state, instr); 1562 Handle_Load_Double (state, instr);
1797 break; 1563 break;
1798 } 1564 }
1799 if (BITS (4, 7) == 0xF) { 1565 if (BITS (4, 7) == 0xF) {
1800 Handle_Store_Double (state, instr); 1566 Handle_Store_Double (state, instr);
1801 break; 1567 break;
1802 } 1568 }
1803 if (BITS (4, 7) == 0x9) { 1569 if (BITS (4, 7) == 0x9) {
1804 /* MULL */ 1570 /* MULL */
1805 /* 32x32=64 */ 1571 /* 32x32=64 */
1806 ARMul_Icycles (state, 1572 ARMul_Icycles (state, Multiply64 (state, instr, LSIGNED, LDEFAULT), 0L);
1807 Multiply64 (state, 1573 break;
1808 instr, 1574 }
1809 LSIGNED,
1810 LDEFAULT),
1811 0L);
1812 break;
1813 }
1814#endif 1575#endif
1815 rhs = DPRegRHS; 1576 rhs = DPRegRHS;
1816 dest = LHS - rhs - !CFLAG; 1577 dest = LHS - rhs - !CFLAG;
1817 WRITEDEST (dest); 1578 WRITEDEST (dest);
1818 break; 1579 break;
1819 1580
1820 case 0x0d: /* SBCS reg */ 1581 case 0x0d: /* SBCS reg */
1821#ifdef MODET 1582#ifdef MODET
1822 if ((BITS (4, 7) & 0x9) == 0x9) 1583 if ((BITS (4, 7) & 0x9) == 0x9)
1823 /* LDR immediate offset, no write-back, up, post indexed. */ 1584 /* LDR immediate offset, no write-back, up, post indexed. */
1824 LHPOSTUP (); 1585 LHPOSTUP ();
1825 1586
1826 if (BITS (4, 7) == 0x9) { 1587 if (BITS (4, 7) == 0x9) {
1827 /* MULL */ 1588 /* MULL */
1828 /* 32x32=64 */ 1589 /* 32x32=64 */
1829 ARMul_Icycles (state, 1590 ARMul_Icycles (state, Multiply64 (state, instr, LSIGNED, LSCC), 0L);
1830 Multiply64 (state, 1591 break;
1831 instr, 1592 }
1832 LSIGNED,
1833 LSCC), 0L);
1834 break;
1835 }
1836#endif 1593#endif
1837 lhs = LHS; 1594 lhs = LHS;
1838 rhs = DPRegRHS; 1595 rhs = DPRegRHS;
1839 dest = lhs - rhs - !CFLAG; 1596 dest = lhs - rhs - !CFLAG;
1840 if ((lhs >= rhs) || ((rhs | lhs) >> 31)) { 1597 if ((lhs >= rhs) || ((rhs | lhs) >> 31)) {
1841 ARMul_SubCarry (state, lhs, rhs, 1598 ARMul_SubCarry (state, lhs, rhs, dest);
1842 dest); 1599 ARMul_SubOverflow (state, lhs, rhs, dest);
1843 ARMul_SubOverflow (state, lhs, rhs, 1600 } else {
1844 dest); 1601 CLEARC;
1845 } 1602 CLEARV;
1846 else { 1603 }
1847 CLEARC; 1604 WRITESDEST (dest);
1848 CLEARV; 1605 break;
1849 }
1850 WRITESDEST (dest);
1851 break;
1852 1606
1853 case 0x0e: /* RSC reg */ 1607 case 0x0e: /* RSC reg */
1854#ifdef MODET 1608#ifdef MODET
1855 if (BITS (4, 7) == 0xB) { 1609 if (BITS (4, 7) == 0xB) {
1856 /* STRH immediate offset, write-back, up, post indexed. */ 1610 /* STRH immediate offset, write-back, up, post indexed. */
1857 SHUPWB (); 1611 SHUPWB ();
1858 break; 1612 break;
1859 } 1613 }
1860 1614
1861 if (BITS (4, 7) == 0x9) { 1615 if (BITS (4, 7) == 0x9) {
1862 /* MULL */ 1616 /* MULL */
1863 /* 32x32=64 */ 1617 /* 32x32=64 */
1864 ARMul_Icycles (state, 1618 ARMul_Icycles (state, MultiplyAdd64 (state, instr, LSIGNED, LDEFAULT), 0L);
1865 MultiplyAdd64 (state, 1619 break;
1866 instr, 1620 }
1867 LSIGNED,
1868 LDEFAULT),
1869 0L);
1870 break;
1871 }
1872#endif 1621#endif
1873 rhs = DPRegRHS; 1622 rhs = DPRegRHS;
1874 dest = rhs - LHS - !CFLAG; 1623 dest = rhs - LHS - !CFLAG;
1875 WRITEDEST (dest); 1624 WRITEDEST (dest);
1876 break; 1625 break;
1877 1626
1878 case 0x0f: /* RSCS reg */ 1627 case 0x0f: /* RSCS reg */
1879#ifdef MODET 1628#ifdef MODET
1880 if ((BITS (4, 7) & 0x9) == 0x9) 1629 if ((BITS (4, 7) & 0x9) == 0x9)
1881 /* LDR immediate offset, write-back, up, post indexed. */ 1630 /* LDR immediate offset, write-back, up, post indexed. */
1882 LHPOSTUP (); 1631 LHPOSTUP ();
1883 /* Fall through to remaining instruction decoding. */ 1632 /* Fall through to remaining instruction decoding. */
1884
1885 if (BITS (4, 7) == 0x9) {
1886 /* MULL */
1887 /* 32x32=64 */
1888 ARMul_Icycles (state,
1889 MultiplyAdd64 (state,
1890 instr,
1891 LSIGNED,
1892 LSCC),
1893 0L);
1894 break;
1895 }
1896#endif
1897 lhs = LHS;
1898 rhs = DPRegRHS;
1899 dest = rhs - lhs - !CFLAG;
1900
1901 if ((rhs >= lhs) || ((rhs | lhs) >> 31)) {
1902 ARMul_SubCarry (state, rhs, lhs,
1903 dest);
1904 ARMul_SubOverflow (state, rhs, lhs,
1905 dest);
1906 }
1907 else {
1908 CLEARC;
1909 CLEARV;
1910 }
1911 WRITESDEST (dest);
1912 break;
1913 1633
1914 case 0x10: /* TST reg and MRS CPSR and SWP word. */ 1634 if (BITS (4, 7) == 0x9) {
1915 if (state->is_v5e) { 1635 /* MULL */
1916 if (BIT (4) == 0 && BIT (7) == 1) { 1636 /* 32x32=64 */
1917 /* ElSegundo SMLAxy insn. */ 1637 ARMul_Icycles (state, MultiplyAdd64 (state, instr, LSIGNED, LSCC), 0L);
1918 ARMword op1 =
1919 state->
1920 Reg[BITS (0, 3)];
1921 ARMword op2 =
1922 state->
1923 Reg[BITS (8, 11)];
1924 ARMword Rn =
1925 state->
1926 Reg[BITS (12, 15)];
1927
1928 if (BIT (5))
1929 op1 >>= 16;
1930 if (BIT (6))
1931 op2 >>= 16;
1932 op1 &= 0xFFFF;
1933 op2 &= 0xFFFF;
1934 if (op1 & 0x8000)
1935 op1 -= 65536;
1936 if (op2 & 0x8000)
1937 op2 -= 65536;
1938 op1 *= op2;
1939 //printf("SMLA_INST:BB,op1=0x%x, op2=0x%x. Rn=0x%x\n", op1, op2, Rn);
1940 if (AddOverflow
1941 (op1, Rn, op1 + Rn))
1942 SETS;
1943 state->Reg[BITS (16, 19)] =
1944 op1 + Rn;
1945 break; 1638 break;
1946 } 1639 }
1640#endif
1641 lhs = LHS;
1642 rhs = DPRegRHS;
1643 dest = rhs - lhs - !CFLAG;
1644
1645 if ((rhs >= lhs) || ((rhs | lhs) >> 31)) {
1646 ARMul_SubCarry (state, rhs, lhs, dest);
1647 ARMul_SubOverflow (state, rhs, lhs, dest);
1648 } else {
1649 CLEARC;
1650 CLEARV;
1651 }
1652 WRITESDEST (dest);
1653 break;
1947 1654
1948 if (BITS (4, 11) == 5) { 1655 case 0x10: /* TST reg and MRS CPSR and SWP word. */
1949 /* ElSegundo QADD insn. */ 1656 if (state->is_v5e) {
1950 ARMword op1 = 1657 if (BIT (4) == 0 && BIT (7) == 1) {
1951 state-> 1658 /* ElSegundo SMLAxy insn. */
1952 Reg[BITS (0, 3)]; 1659 ARMword op1 = state->Reg[BITS (0, 3)];
1953 ARMword op2 = 1660 ARMword op2 = state->Reg[BITS (8, 11)];
1954 state-> 1661 ARMword Rn = state->Reg[BITS (12, 15)];
1955 Reg[BITS (16, 19)]; 1662
1956 ARMword result = op1 + op2; 1663 if (BIT (5))
1957 if (AddOverflow 1664 op1 >>= 16;
1958 (op1, op2, result)) { 1665 if (BIT (6))
1959 result = POS (result) 1666 op2 >>= 16;
1960 ? 0x80000000 : 1667 op1 &= 0xFFFF;
1961 0x7fffffff; 1668 op2 &= 0xFFFF;
1962 SETS; 1669 if (op1 & 0x8000)
1670 op1 -= 65536;
1671 if (op2 & 0x8000)
1672 op2 -= 65536;
1673 op1 *= op2;
1674 //printf("SMLA_INST:BB,op1=0x%x, op2=0x%x. Rn=0x%x\n", op1, op2, Rn);
1675 if (AddOverflow(op1, Rn, op1 + Rn))
1676 SETS;
1677 state->Reg[BITS (16, 19)] = op1 + Rn;
1678 break;
1679 }
1680
1681 if (BITS (4, 11) == 5) {
1682 /* ElSegundo QADD insn. */
1683 ARMword op1 = state->Reg[BITS (0, 3)];
1684 ARMword op2 = state->Reg[BITS (16, 19)];
1685 ARMword result = op1 + op2;
1686 if (AddOverflow(op1, op2, result)) {
1687 result = POS (result) ? 0x80000000 : 0x7fffffff;
1688 SETS;
1689 }
1690 state->Reg[BITS (12, 15)] = result;
1691 break;
1963 } 1692 }
1964 state->Reg[BITS (12, 15)] =
1965 result;
1966 break;
1967 } 1693 }
1968 }
1969#ifdef MODET 1694#ifdef MODET
1970 if (BITS (4, 11) == 0xB) { 1695 if (BITS (4, 11) == 0xB) {
1971 /* STRH register offset, no write-back, down, pre indexed. */ 1696 /* STRH register offset, no write-back, down, pre indexed. */
1972 SHPREDOWN (); 1697 SHPREDOWN ();
1973 break; 1698 break;
1974 } 1699 }
1975 if (BITS (4, 7) == 0xD) { 1700 if (BITS (4, 7) == 0xD) {
1976 Handle_Load_Double (state, instr); 1701 Handle_Load_Double (state, instr);
1977 break; 1702 break;
1978 } 1703 }
1979 if (BITS (4, 7) == 0xF) { 1704 if (BITS (4, 7) == 0xF) {
1980 Handle_Store_Double (state, instr); 1705 Handle_Store_Double (state, instr);
1981 break; 1706 break;
1982 } 1707 }
1983#endif 1708#endif
1984 if (BITS (4, 11) == 9) { 1709 if (BITS (4, 11) == 9) {
1985 /* SWP */ 1710 /* SWP */
1986 UNDEF_SWPPC; 1711 UNDEF_SWPPC;
1987 temp = LHS; 1712 temp = LHS;
1988 BUSUSEDINCPCS; 1713 BUSUSEDINCPCS;
1989#ifndef MODE32 1714#ifndef MODE32
1990 if (VECTORACCESS (temp) 1715 if (VECTORACCESS (temp) || ADDREXCEPT (temp)) {
1991 || ADDREXCEPT (temp)) { 1716 INTERNALABORT (temp);
1992 INTERNALABORT (temp); 1717 (void) ARMul_LoadWordN (state, temp);
1993 (void) ARMul_LoadWordN (state, 1718 (void) ARMul_LoadWordN (state, temp);
1994 temp); 1719 } else
1995 (void) ARMul_LoadWordN (state,
1996 temp);
1997 }
1998 else
1999#endif 1720#endif
2000 dest = ARMul_SwapWord (state, 1721 dest = ARMul_SwapWord (state, temp, state->Reg[RHSReg]);
2001 temp, 1722 if (temp & 3)
2002 state-> 1723 DEST = ARMul_Align (state, temp, dest);
2003 Reg 1724 else
2004 [RHSReg]); 1725 DEST = dest;
2005 if (temp & 3) 1726 if (state->abortSig || state->Aborted)
2006 DEST = ARMul_Align (state, 1727 TAKEABORT;
2007 temp, 1728 } else if ((BITS (0, 11) == 0) && (LHSReg == 15)) { /* MRS CPSR */
2008 dest); 1729 UNDEF_MRSPC;
2009 else 1730 DEST = ECC | EINT | EMODE;
2010 DEST = dest; 1731 } else {
2011 if (state->abortSig || state->Aborted) 1732 UNDEF_Test;
2012 TAKEABORT; 1733 }
2013 } 1734 break;
2014 else if ((BITS (0, 11) == 0) && (LHSReg == 15)) { /* MRS CPSR */
2015 UNDEF_MRSPC;
2016 DEST = ECC | EINT | EMODE;
2017 }
2018 else {
2019 UNDEF_Test;
2020 }
2021 break;
2022 1735
2023 case 0x11: /* TSTP reg */ 1736 case 0x11: /* TSTP reg */
2024#ifdef MODET 1737#ifdef MODET
2025 if ((BITS (4, 11) & 0xF9) == 0x9) 1738 if ((BITS (4, 11) & 0xF9) == 0x9)
2026 /* LDR register offset, no write-back, down, pre indexed. */ 1739 /* LDR register offset, no write-back, down, pre indexed. */
2027 LHPREDOWN (); 1740 LHPREDOWN ();
2028 /* Continue with remaining instruction decode. */ 1741 /* Continue with remaining instruction decode. */
2029#endif 1742#endif
2030 if (DESTReg == 15) { 1743 if (DESTReg == 15) {
2031 /* TSTP reg */ 1744 /* TSTP reg */
2032#ifdef MODE32 1745#ifdef MODE32
2033 //chy 2006-02-15 if in user mode, can not set cpsr 0:23 1746 //chy 2006-02-15 if in user mode, can not set cpsr 0:23
2034 //from p165 of ARMARM book 1747 //from p165 of ARMARM book
2035 state->Cpsr = GETSPSR (state->Bank); 1748 state->Cpsr = GETSPSR (state->Bank);
2036 ARMul_CPSRAltered (state); 1749 //ARMul_CPSRAltered (state);
2037#else 1750#else
2038 rhs = DPRegRHS; 1751 rhs = DPRegRHS;
2039 temp = LHS & rhs; 1752 temp = LHS & rhs;
2040 SETR15PSR (temp); 1753 SETR15PSR (temp);
2041#endif 1754#endif
2042 } 1755 } else {
2043 else { 1756 /* TST reg */
2044 /* TST reg */ 1757 rhs = DPSRegRHS;
2045 rhs = DPSRegRHS; 1758 dest = LHS & rhs;
2046 dest = LHS & rhs; 1759 ARMul_NegZero (state, dest);
2047 ARMul_NegZero (state, dest); 1760 }
2048 } 1761 break;
2049 break;
2050 1762
2051 case 0x12: /* TEQ reg and MSR reg to CPSR (ARM6). */ 1763 case 0x12: /* TEQ reg and MSR reg to CPSR (ARM6). */
2052 1764
2053 if (state->is_v5) { 1765 if (state->is_v5) {
2054 if (BITS (4, 7) == 3) { 1766 if (BITS (4, 7) == 3) {
2055 /* BLX(2) */ 1767 /* BLX(2) */
2056 ARMword temp; 1768 ARMword temp;
2057 1769
2058 if (TFLAG) 1770 if (TFLAG)
2059 temp = (pc + 2) | 1; 1771 temp = (pc + 2) | 1;
2060 else 1772 else
2061 temp = pc + 4; 1773 temp = pc + 4;
2062 1774
2063 WriteR15Branch (state, 1775 WriteR15Branch (state, state->Reg[RHSReg]);
2064 state-> 1776 state->Reg[14] = temp;
2065 Reg[RHSReg]); 1777 break;
2066 state->Reg[14] = temp; 1778 }
2067 break;
2068 } 1779 }
2069 }
2070 1780
2071 if (state->is_v5e) { 1781 if (state->is_v5e) {
2072 if (BIT (4) == 0 && BIT (7) == 1 1782 if (BIT (4) == 0 && BIT (7) == 1 && (BIT (5) == 0 || BITS (12, 15) == 0)) {
2073 && (BIT (5) == 0 1783 /* ElSegundo SMLAWy/SMULWy insn. */
2074 || BITS (12, 15) == 0)) { 1784 unsigned long long op1 = state->Reg[BITS (0, 3)];
2075 /* ElSegundo SMLAWy/SMULWy insn. */ 1785 unsigned long long op2 = state->Reg[BITS (8, 11)];
2076 unsigned long long op1 = 1786 unsigned long long result;
2077 state-> 1787
2078 Reg[BITS (0, 3)]; 1788 if (BIT (6))
2079 unsigned long long op2 = 1789 op2 >>= 16;
2080 state-> 1790 if (op1 & 0x80000000)
2081 Reg[BITS (8, 11)]; 1791 op1 -= 1ULL << 32;
2082 unsigned long long result; 1792 op2 &= 0xFFFF;
2083 1793 if (op2 & 0x8000)
2084 if (BIT (6)) 1794 op2 -= 65536;
2085 op2 >>= 16; 1795 result = (op1 * op2) >> 16;
2086 if (op1 & 0x80000000) 1796
2087 op1 -= 1ULL << 32; 1797 if (BIT (5) == 0) {
2088 op2 &= 0xFFFF; 1798 ARMword Rn = state->Reg[BITS(12, 15)];
2089 if (op2 & 0x8000) 1799
2090 op2 -= 65536; 1800 if (AddOverflow((ARMword)result, Rn, (ARMword)(result + Rn)))
2091 result = (op1 * op2) >> 16; 1801 SETS;
2092 1802 result += Rn;
2093 if (BIT (5) == 0) { 1803 }
2094 ARMword Rn = 1804 state->Reg[BITS (16, 19)] = (ARMword)result;
2095 state-> 1805 break;
2096 Reg[BITS 1806 }
2097 (12, 15)]; 1807
1808 if (BITS (4, 11) == 5) {
1809 /* ElSegundo QSUB insn. */
1810 ARMword op1 = state->Reg[BITS (0, 3)];
1811 ARMword op2 = state->Reg[BITS (16, 19)];
1812 ARMword result = op1 - op2;
2098 1813
2099 if (AddOverflow 1814 if (SubOverflow
2100 (result, Rn, 1815 (op1, op2, result)) {
2101 result + Rn)) 1816 result = POS (result) ? 0x80000000 : 0x7fffffff;
2102 SETS; 1817 SETS;
2103 result += Rn; 1818 }
1819
1820 state->Reg[BITS (12, 15)] = result;
1821 break;
2104 } 1822 }
2105 state->Reg[BITS (16, 19)] = 1823 }
2106 result; 1824#ifdef MODET
1825 if (BITS (4, 11) == 0xB) {
1826 /* STRH register offset, write-back, down, pre indexed. */
1827 SHPREDOWNWB ();
2107 break; 1828 break;
2108 } 1829 }
2109 1830 if (BITS (4, 27) == 0x12FFF1) {
2110 if (BITS (4, 11) == 5) { 1831 /* BX */
2111 /* ElSegundo QSUB insn. */ 1832 WriteR15Branch (state, state->Reg[RHSReg]);
2112 ARMword op1 = 1833 break;
2113 state-> 1834 }
2114 Reg[BITS (0, 3)]; 1835 if (BITS (4, 7) == 0xD) {
2115 ARMword op2 = 1836 Handle_Load_Double (state, instr);
2116 state-> 1837 break;
2117 Reg[BITS (16, 19)]; 1838 }
2118 ARMword result = op1 - op2; 1839 if (BITS (4, 7) == 0xF) {
2119 1840 Handle_Store_Double (state, instr);
2120 if (SubOverflow
2121 (op1, op2, result)) {
2122 result = POS (result)
2123 ? 0x80000000 :
2124 0x7fffffff;
2125 SETS;
2126 }
2127
2128 state->Reg[BITS (12, 15)] =
2129 result;
2130 break; 1841 break;
2131 } 1842 }
2132 }
2133#ifdef MODET
2134 if (BITS (4, 11) == 0xB) {
2135 /* STRH register offset, write-back, down, pre indexed. */
2136 SHPREDOWNWB ();
2137 break;
2138 }
2139 if (BITS (4, 27) == 0x12FFF1) {
2140 /* BX */
2141 WriteR15Branch (state,
2142 state->Reg[RHSReg]);
2143 break;
2144 }
2145 if (BITS (4, 7) == 0xD) {
2146 Handle_Load_Double (state, instr);
2147 break;
2148 }
2149 if (BITS (4, 7) == 0xF) {
2150 Handle_Store_Double (state, instr);
2151 break;
2152 }
2153#endif 1843#endif
2154 if (state->is_v5) { 1844 if (state->is_v5) {
2155 if (BITS (4, 7) == 0x7) { 1845 if (BITS (4, 7) == 0x7) {
2156 ARMword value; 1846 //ARMword value;
2157 extern int 1847 //extern int SWI_vector_installed;
2158 SWI_vector_installed; 1848
2159 1849 /* Hardware is allowed to optionally override this
2160 /* Hardware is allowed to optionally override this 1850 instruction and treat it as a breakpoint. Since
2161 instruction and treat it as a breakpoint. Since 1851 this is a simulator not hardware, we take the position
2162 this is a simulator not hardware, we take the position 1852 that if a SWI vector was not installed, then an Abort
2163 that if a SWI vector was not installed, then an Abort 1853 vector was probably not installed either, and so
2164 vector was probably not installed either, and so 1854 normally this instruction would be ignored, even if an
2165 normally this instruction would be ignored, even if an 1855 Abort is generated. This is a bad thing, since GDB
2166 Abort is generated. This is a bad thing, since GDB 1856 uses this instruction for its breakpoints (at least in
2167 uses this instruction for its breakpoints (at least in 1857 Thumb mode it does). So intercept the instruction here
2168 Thumb mode it does). So intercept the instruction here 1858 and generate a breakpoint SWI instead. */
2169 and generate a breakpoint SWI instead. */ 1859 /* Force the next instruction to be refetched. */
2170 if (!SWI_vector_installed) 1860 state->NextInstr = RESUME;
2171 ARMul_OSHandleSWI 1861 break;
2172 (state,
2173 SWI_Breakpoint);
2174 else {
2175 /* BKPT - normally this will cause an abort, but on the
2176 XScale we must check the DCSR. */
2177 XScale_set_fsr_far
2178 (state,
2179 ARMul_CP15_R5_MMU_EXCPT,
2180 pc);
2181 //if (!XScale_debug_moe
2182 // (state,
2183 // ARMul_CP14_R10_MOE_BT))
2184 // break; // Disabled /bunnei
2185 } 1862 }
2186
2187 /* Force the next instruction to be refetched. */
2188 state->NextInstr = RESUME;
2189 break;
2190 } 1863 }
2191 } 1864 if (DESTReg == 15) {
2192 if (DESTReg == 15) { 1865 /* MSR reg to CPSR. */
2193 /* MSR reg to CPSR. */ 1866 UNDEF_MSRPC;
2194 UNDEF_MSRPC; 1867 temp = DPRegRHS;
2195 temp = DPRegRHS;
2196#ifdef MODET 1868#ifdef MODET
2197 /* Don't allow TBIT to be set by MSR. */ 1869 /* Don't allow TBIT to be set by MSR. */
2198 temp &= ~TBIT; 1870 temp &= ~TBIT;
2199#endif 1871#endif
2200 ARMul_FixCPSR (state, instr, temp); 1872 ARMul_FixCPSR (state, instr, temp);
2201 } 1873 } else
2202 else 1874 UNDEF_Test;
2203 UNDEF_Test;
2204 1875
2205 break; 1876 break;
2206 1877
2207 case 0x13: /* TEQP reg */ 1878 case 0x13: /* TEQP reg */
2208#ifdef MODET 1879#ifdef MODET
2209 if ((BITS (4, 11) & 0xF9) == 0x9) 1880 if ((BITS (4, 11) & 0xF9) == 0x9)
2210 /* LDR register offset, write-back, down, pre indexed. */ 1881 /* LDR register offset, write-back, down, pre indexed. */
2211 LHPREDOWNWB (); 1882 LHPREDOWNWB ();
2212 /* Continue with remaining instruction decode. */ 1883 /* Continue with remaining instruction decode. */
2213#endif 1884#endif
2214 if (DESTReg == 15) { 1885 if (DESTReg == 15) {
2215 /* TEQP reg */ 1886 /* TEQP reg */
2216#ifdef MODE32 1887#ifdef MODE32
2217 state->Cpsr = GETSPSR (state->Bank); 1888 state->Cpsr = GETSPSR (state->Bank);
2218 ARMul_CPSRAltered (state); 1889 //ARMul_CPSRAltered (state);
2219#else 1890#else
2220 rhs = DPRegRHS; 1891 rhs = DPRegRHS;
2221 temp = LHS ^ rhs; 1892 temp = LHS ^ rhs;
2222 SETR15PSR (temp); 1893 SETR15PSR (temp);
2223#endif 1894#endif
2224 } 1895 } else {
2225 else { 1896 /* TEQ Reg. */
2226 /* TEQ Reg. */ 1897 rhs = DPSRegRHS;
2227 rhs = DPSRegRHS; 1898 dest = LHS ^ rhs;
2228 dest = LHS ^ rhs; 1899 ARMul_NegZero (state, dest);
2229 ARMul_NegZero (state, dest);
2230 }
2231 break;
2232
2233 case 0x14: /* CMP reg and MRS SPSR and SWP byte. */
2234 if (state->is_v5e) {
2235 if (BIT (4) == 0 && BIT (7) == 1) {
2236 /* ElSegundo SMLALxy insn. */
2237 unsigned long long op1 =
2238 state->
2239 Reg[BITS (0, 3)];
2240 unsigned long long op2 =
2241 state->
2242 Reg[BITS (8, 11)];
2243 unsigned long long dest;
2244 unsigned long long result;
2245
2246 if (BIT (5))
2247 op1 >>= 16;
2248 if (BIT (6))
2249 op2 >>= 16;
2250 op1 &= 0xFFFF;
2251 if (op1 & 0x8000)
2252 op1 -= 65536;
2253 op2 &= 0xFFFF;
2254 if (op2 & 0x8000)
2255 op2 -= 65536;
2256
2257 dest = (unsigned long long)
2258 state->
2259 Reg[BITS (16, 19)] <<
2260 32;
2261 dest |= state->
2262 Reg[BITS (12, 15)];
2263 dest += op1 * op2;
2264 state->Reg[BITS (12, 15)] =
2265 dest;
2266 state->Reg[BITS (16, 19)] =
2267 dest >> 32;
2268 break;
2269 } 1900 }
1901 break;
2270 1902
2271 if (BITS (4, 11) == 5) { 1903 case 0x14: /* CMP reg and MRS SPSR and SWP byte. */
2272 /* ElSegundo QDADD insn. */ 1904 if (state->is_v5e) {
2273 ARMword op1 = 1905 if (BIT (4) == 0 && BIT (7) == 1) {
2274 state-> 1906 /* ElSegundo SMLALxy insn. */
2275 Reg[BITS (0, 3)]; 1907 unsigned long long op1 = state->Reg[BITS (0, 3)];
2276 ARMword op2 = 1908 unsigned long long op2 = state->Reg[BITS (8, 11)];
2277 state-> 1909 unsigned long long dest;
2278 Reg[BITS (16, 19)]; 1910 //unsigned long long result;
2279 ARMword op2d = op2 + op2; 1911
2280 ARMword result; 1912 if (BIT (5))
2281 1913 op1 >>= 16;
2282 if (AddOverflow 1914 if (BIT (6))
2283 (op2, op2, op2d)) { 1915 op2 >>= 16;
2284 SETS; 1916 op1 &= 0xFFFF;
2285 op2d = POS (op2d) ? 1917 if (op1 & 0x8000)
2286 0x80000000 : 1918 op1 -= 65536;
2287 0x7fffffff; 1919 op2 &= 0xFFFF;
1920 if (op2 & 0x8000)
1921 op2 -= 65536;
1922
1923 dest = (unsigned long long) state->Reg[BITS (16, 19)] << 32;
1924 dest |= state->Reg[BITS (12, 15)];
1925 dest += op1 * op2;
1926 state->Reg[BITS(12, 15)] = (ARMword)dest;
1927 state->Reg[BITS(16, 19)] = (ARMword)(dest >> 32);
1928 break;
2288 } 1929 }
2289 1930
2290 result = op1 + op2d; 1931 if (BITS (4, 11) == 5) {
2291 if (AddOverflow 1932 /* ElSegundo QDADD insn. */
2292 (op1, op2d, result)) { 1933 ARMword op1 = state->Reg[BITS (0, 3)];
2293 SETS; 1934 ARMword op2 = state->Reg[BITS (16, 19)];
2294 result = POS (result) 1935 ARMword op2d = op2 + op2;
2295 ? 0x80000000 : 1936 ARMword result;
2296 0x7fffffff;
2297 }
2298 1937
2299 state->Reg[BITS (12, 15)] = 1938 if (AddOverflow
2300 result; 1939 (op2, op2, op2d)) {
2301 break; 1940 SETS;
1941 op2d = POS (op2d) ? 0x80000000 : 0x7fffffff;
1942 }
1943
1944 result = op1 + op2d;
1945 if (AddOverflow(op1, op2d, result)) {
1946 SETS;
1947 result = POS (result) ? 0x80000000 : 0x7fffffff;
1948 }
1949
1950 state->Reg[BITS (12, 15)] = result;
1951 break;
1952 }
2302 } 1953 }
2303 }
2304#ifdef MODET 1954#ifdef MODET
2305 if (BITS (4, 7) == 0xB) { 1955 if (BITS (4, 7) == 0xB) {
2306 /* STRH immediate offset, no write-back, down, pre indexed. */ 1956 /* STRH immediate offset, no write-back, down, pre indexed. */
2307 SHPREDOWN (); 1957 SHPREDOWN ();
2308 break; 1958 break;
2309 } 1959 }
2310 if (BITS (4, 7) == 0xD) { 1960 if (BITS (4, 7) == 0xD) {
2311 Handle_Load_Double (state, instr); 1961 Handle_Load_Double (state, instr);
2312 break; 1962 break;
2313 } 1963 }
2314 if (BITS (4, 7) == 0xF) { 1964 if (BITS (4, 7) == 0xF) {
2315 Handle_Store_Double (state, instr); 1965 Handle_Store_Double (state, instr);
2316 break; 1966 break;
2317 } 1967 }
2318#endif 1968#endif
2319 if (BITS (4, 11) == 9) { 1969 if (BITS (4, 11) == 9) {
2320 /* SWP */ 1970 /* SWP */
2321 UNDEF_SWPPC; 1971 UNDEF_SWPPC;
2322 temp = LHS; 1972 temp = LHS;
2323 BUSUSEDINCPCS; 1973 BUSUSEDINCPCS;
2324#ifndef MODE32 1974#ifndef MODE32
2325 if (VECTORACCESS (temp) 1975 if (VECTORACCESS (temp) || ADDREXCEPT (temp)) {
2326 || ADDREXCEPT (temp)) { 1976 INTERNALABORT (temp);
2327 INTERNALABORT (temp); 1977 (void) ARMul_LoadByte (state, temp);
2328 (void) ARMul_LoadByte (state, 1978 (void) ARMul_LoadByte (state, temp);
2329 temp); 1979 } else
2330 (void) ARMul_LoadByte (state,
2331 temp);
2332 }
2333 else
2334#endif 1980#endif
2335 DEST = ARMul_SwapByte (state, 1981 DEST = ARMul_SwapByte (state, temp, state->Reg[RHSReg]);
2336 temp, 1982 if (state->abortSig || state->Aborted)
2337 state-> 1983 TAKEABORT;
2338 Reg 1984 } else if ((BITS (0, 11) == 0)
2339 [RHSReg]); 1985 && (LHSReg == 15)) {
2340 if (state->abortSig || state->Aborted) 1986 /* MRS SPSR */
2341 TAKEABORT; 1987 UNDEF_MRSPC;
2342 } 1988 DEST = GETSPSR (state->Bank);
2343 else if ((BITS (0, 11) == 0) 1989 } else
2344 && (LHSReg == 15)) { 1990 UNDEF_Test;
2345 /* MRS SPSR */
2346 UNDEF_MRSPC;
2347 DEST = GETSPSR (state->Bank);
2348 }
2349 else
2350 UNDEF_Test;
2351 1991
2352 break; 1992 break;
2353 1993
2354 case 0x15: /* CMPP reg. */ 1994 case 0x15: /* CMPP reg. */
2355#ifdef MODET 1995#ifdef MODET
2356 if ((BITS (4, 7) & 0x9) == 0x9) 1996 if ((BITS (4, 7) & 0x9) == 0x9)
2357 /* LDR immediate offset, no write-back, down, pre indexed. */ 1997 /* LDR immediate offset, no write-back, down, pre indexed. */
2358 LHPREDOWN (); 1998 LHPREDOWN ();
2359 /* Continue with remaining instruction decode. */ 1999 /* Continue with remaining instruction decode. */
2360#endif 2000#endif
2361 if (DESTReg == 15) { 2001 if (DESTReg == 15) {
2362 /* CMPP reg. */ 2002 /* CMPP reg. */
2363#ifdef MODE32 2003#ifdef MODE32
2364 state->Cpsr = GETSPSR (state->Bank); 2004 state->Cpsr = GETSPSR (state->Bank);
2365 ARMul_CPSRAltered (state); 2005 //ARMul_CPSRAltered (state);
2366#else 2006#else
2367 rhs = DPRegRHS; 2007 rhs = DPRegRHS;
2368 temp = LHS - rhs; 2008 temp = LHS - rhs;
2369 SETR15PSR (temp); 2009 SETR15PSR (temp);
2370#endif 2010#endif
2371 } 2011 } else {
2372 else { 2012 /* CMP reg. */
2373 /* CMP reg. */ 2013 lhs = LHS;
2374 lhs = LHS; 2014 rhs = DPRegRHS;
2375 rhs = DPRegRHS; 2015 dest = lhs - rhs;
2376 dest = lhs - rhs; 2016 ARMul_NegZero (state, dest);
2377 ARMul_NegZero (state, dest); 2017 if ((lhs >= rhs)
2378 if ((lhs >= rhs) 2018 || ((rhs | lhs) >> 31)) {
2379 || ((rhs | lhs) >> 31)) { 2019 ARMul_SubCarry (state, lhs, rhs, dest);
2380 ARMul_SubCarry (state, lhs, 2020 ARMul_SubOverflow (state, lhs, rhs, dest);
2381 rhs, dest); 2021 } else {
2382 ARMul_SubOverflow (state, lhs, 2022 CLEARC;
2383 rhs, dest); 2023 CLEARV;
2384 } 2024 }
2385 else {
2386 CLEARC;
2387 CLEARV;
2388 } 2025 }
2389 } 2026 break;
2390 break;
2391 2027
2392 case 0x16: /* CMN reg and MSR reg to SPSR */ 2028 case 0x16: /* CMN reg and MSR reg to SPSR */
2393 if (state->is_v5e) { 2029 if (state->is_v5e) {
2394 if (BIT (4) == 0 && BIT (7) == 1 2030 if (BIT (4) == 0 && BIT (7) == 1 && BITS (12, 15) == 0) {
2395 && BITS (12, 15) == 0) { 2031 /* ElSegundo SMULxy insn. */
2396 /* ElSegundo SMULxy insn. */ 2032 ARMword op1 = state->Reg[BITS (0, 3)];
2397 ARMword op1 = 2033 ARMword op2 = state->Reg[BITS (8, 11)];
2398 state-> 2034 ARMword Rn = state->Reg[BITS (12, 15)];
2399 Reg[BITS (0, 3)]; 2035
2400 ARMword op2 = 2036 if (BIT (5))
2401 state-> 2037 op1 >>= 16;
2402 Reg[BITS (8, 11)]; 2038 if (BIT (6))
2403 ARMword Rn = 2039 op2 >>= 16;
2404 state-> 2040 op1 &= 0xFFFF;
2405 Reg[BITS (12, 15)]; 2041 op2 &= 0xFFFF;
2406 2042 if (op1 & 0x8000)
2407 if (BIT (5)) 2043 op1 -= 65536;
2408 op1 >>= 16; 2044 if (op2 & 0x8000)
2409 if (BIT (6)) 2045 op2 -= 65536;
2410 op2 >>= 16; 2046
2411 op1 &= 0xFFFF; 2047 state->Reg[BITS (16, 19)] = op1 * op2;
2412 op2 &= 0xFFFF; 2048 break;
2413 if (op1 & 0x8000) 2049 }
2414 op1 -= 65536; 2050
2415 if (op2 & 0x8000) 2051 if (BITS (4, 11) == 5) {
2416 op2 -= 65536; 2052 /* ElSegundo QDSUB insn. */
2417 2053 ARMword op1 = state->Reg[BITS (0, 3)];
2418 state->Reg[BITS (16, 19)] = 2054 ARMword op2 = state->Reg[BITS (16, 19)];
2419 op1 * op2; 2055 ARMword op2d = op2 + op2;
2420 break; 2056 ARMword result;
2421 } 2057
2058 if (AddOverflow(op2, op2, op2d)) {
2059 SETS;
2060 op2d = POS (op2d) ? 0x80000000 : 0x7fffffff;
2061 }
2422 2062
2423 if (BITS (4, 11) == 5) { 2063 result = op1 - op2d;
2424 /* ElSegundo QDSUB insn. */ 2064 if (SubOverflow(op1, op2d, result)) {
2425 ARMword op1 = 2065 SETS;
2426 state-> 2066 result = POS (result) ? 0x80000000 : 0x7fffffff;
2427 Reg[BITS (0, 3)]; 2067 }
2428 ARMword op2 = 2068
2429 state-> 2069 state->Reg[BITS (12, 15)] = result;
2430 Reg[BITS (16, 19)]; 2070 break;
2431 ARMword op2d = op2 + op2;
2432 ARMword result;
2433
2434 if (AddOverflow
2435 (op2, op2, op2d)) {
2436 SETS;
2437 op2d = POS (op2d) ?
2438 0x80000000 :
2439 0x7fffffff;
2440 } 2071 }
2072 }
2441 2073
2442 result = op1 - op2d; 2074 if (state->is_v5) {
2443 if (SubOverflow 2075 if (BITS (4, 11) == 0xF1
2444 (op1, op2d, result)) { 2076 && BITS (16, 19) == 0xF) {
2445 SETS; 2077 /* ARM5 CLZ insn. */
2446 result = POS (result) 2078 ARMword op1 = state->Reg[BITS (0, 3)];
2447 ? 0x80000000 : 2079 int result = 32;
2448 0x7fffffff; 2080
2081 if (op1)
2082 for (result = 0; (op1 & 0x80000000) == 0; op1 <<= 1)
2083 result++;
2084 state->Reg[BITS (12, 15)] = result;
2085 break;
2449 } 2086 }
2087 }
2450 2088
2451 state->Reg[BITS (12, 15)] = 2089#ifdef MODET
2452 result; 2090 if (BITS (4, 7) == 0xB) {
2091 /* STRH immediate offset, write-back, down, pre indexed. */
2092 SHPREDOWNWB ();
2453 break; 2093 break;
2454 } 2094 }
2455 } 2095 if (BITS (4, 7) == 0xD) {
2456 2096 Handle_Load_Double (state, instr);
2457 if (state->is_v5) { 2097 break;
2458 if (BITS (4, 11) == 0xF1 2098 }
2459 && BITS (16, 19) == 0xF) { 2099 if (BITS (4, 7) == 0xF) {
2460 /* ARM5 CLZ insn. */ 2100 Handle_Store_Double (state, instr);
2461 ARMword op1 =
2462 state->
2463 Reg[BITS (0, 3)];
2464 int result = 32;
2465
2466 if (op1)
2467 for (result = 0;
2468 (op1 &
2469 0x80000000) ==
2470 0; op1 <<= 1)
2471 result++;
2472 state->Reg[BITS (12, 15)] =
2473 result;
2474 break; 2101 break;
2475 } 2102 }
2476 }
2477
2478#ifdef MODET
2479 if (BITS (4, 7) == 0xB) {
2480 /* STRH immediate offset, write-back, down, pre indexed. */
2481 SHPREDOWNWB ();
2482 break;
2483 }
2484 if (BITS (4, 7) == 0xD) {
2485 Handle_Load_Double (state, instr);
2486 break;
2487 }
2488 if (BITS (4, 7) == 0xF) {
2489 Handle_Store_Double (state, instr);
2490 break;
2491 }
2492#endif 2103#endif
2493 if (DESTReg == 15) { 2104 if (DESTReg == 15) {
2494 /* MSR */ 2105 /* MSR */
2495 UNDEF_MSRPC; 2106 UNDEF_MSRPC;
2496 ARMul_FixSPSR (state, instr, 2107 /*ARMul_FixSPSR (state, instr,
2497 DPRegRHS); 2108 DPRegRHS);*/
2498 } 2109 } else {
2499 else { 2110 UNDEF_Test;
2500 UNDEF_Test; 2111 }
2501 } 2112 break;
2502 break;
2503 2113
2504 case 0x17: /* CMNP reg */ 2114 case 0x17: /* CMNP reg */
2505#ifdef MODET 2115#ifdef MODET
2506 if ((BITS (4, 7) & 0x9) == 0x9) 2116 if ((BITS (4, 7) & 0x9) == 0x9)
2507 /* LDR immediate offset, write-back, down, pre indexed. */ 2117 /* LDR immediate offset, write-back, down, pre indexed. */
2508 LHPREDOWNWB (); 2118 LHPREDOWNWB ();
2509 /* Continue with remaining instruction decoding. */ 2119 /* Continue with remaining instruction decoding. */
2510#endif 2120#endif
2511 if (DESTReg == 15) { 2121 if (DESTReg == 15) {
2512#ifdef MODE32 2122#ifdef MODE32
2513 state->Cpsr = GETSPSR (state->Bank); 2123 state->Cpsr = GETSPSR (state->Bank);
2514 ARMul_CPSRAltered (state); 2124 //ARMul_CPSRAltered (state);
2515#else 2125#else
2516 rhs = DPRegRHS; 2126 rhs = DPRegRHS;
2517 temp = LHS + rhs; 2127 temp = LHS + rhs;
2518 SETR15PSR (temp); 2128 SETR15PSR (temp);
2519#endif 2129#endif
2520 break; 2130 break;
2521 } 2131 } else {
2522 else { 2132 /* CMN reg. */
2523 /* CMN reg. */ 2133 lhs = LHS;
2524 lhs = LHS; 2134 rhs = DPRegRHS;
2525 rhs = DPRegRHS; 2135 dest = lhs + rhs;
2526 dest = lhs + rhs; 2136 ASSIGNZ (dest == 0);
2527 ASSIGNZ (dest == 0); 2137 if ((lhs | rhs) >> 30) {
2528 if ((lhs | rhs) >> 30) { 2138 /* Possible C,V,N to set. */
2529 /* Possible C,V,N to set. */ 2139 ASSIGNN (NEG (dest));
2530 ASSIGNN (NEG (dest)); 2140 ARMul_AddCarry (state, lhs, rhs, dest);
2531 ARMul_AddCarry (state, lhs, 2141 ARMul_AddOverflow (state, lhs, rhs, dest);
2532 rhs, dest); 2142 } else {
2533 ARMul_AddOverflow (state, lhs, 2143 CLEARN;
2534 rhs, dest); 2144 CLEARC;
2535 } 2145 CLEARV;
2536 else { 2146 }
2537 CLEARN;
2538 CLEARC;
2539 CLEARV;
2540 } 2147 }
2541 } 2148 break;
2542 break;
2543 2149
2544 case 0x18: /* ORR reg */ 2150 case 0x18: /* ORR reg */
2545#ifdef MODET 2151#ifdef MODET
2546 /* dyf add armv6 instr strex 2010.9.17 */ 2152 /* dyf add armv6 instr strex 2010.9.17 */
2547 if (state->is_v6) { 2153 if (state->is_v6) {
2548 if (BITS (4, 7) == 0x9) 2154 if (BITS (4, 7) == 0x9)
2549 if (handle_v6_insn (state, instr)) 2155 if (handle_v6_insn (state, instr))
2550 break; 2156 break;
2551 } 2157 }
2552 2158
2553 if (BITS (4, 11) == 0xB) { 2159 if (BITS (4, 11) == 0xB) {
2554 /* STRH register offset, no write-back, up, pre indexed. */ 2160 /* STRH register offset, no write-back, up, pre indexed. */
2555 SHPREUP (); 2161 SHPREUP ();
2556 break; 2162 break;
2557 } 2163 }
2558 if (BITS (4, 7) == 0xD) { 2164 if (BITS (4, 7) == 0xD) {
2559 Handle_Load_Double (state, instr); 2165 Handle_Load_Double (state, instr);
2560 break; 2166 break;
2561 } 2167 }
2562 if (BITS (4, 7) == 0xF) { 2168 if (BITS (4, 7) == 0xF) {
2563 Handle_Store_Double (state, instr); 2169 Handle_Store_Double (state, instr);
2564 break; 2170 break;
2565 } 2171 }
2566#endif 2172#endif
2567 rhs = DPRegRHS; 2173 rhs = DPRegRHS;
2568 dest = LHS | rhs; 2174 dest = LHS | rhs;
2569 WRITEDEST (dest); 2175 WRITEDEST (dest);
2570 break; 2176 break;
2571 2177
2572 case 0x19: /* ORRS reg */ 2178 case 0x19: /* ORRS reg */
2573#ifdef MODET 2179#ifdef MODET
2574 /* dyf add armv6 instr ldrex */ 2180 /* dyf add armv6 instr ldrex */
2575 if (state->is_v6) { 2181 if (state->is_v6) {
2576 if (BITS (4, 7) == 0x9) { 2182 if (BITS (4, 7) == 0x9) {
2577 if (handle_v6_insn (state, instr)) 2183 if (handle_v6_insn (state, instr))
2578 break; 2184 break;
2185 }
2579 } 2186 }
2580 } 2187 if ((BITS (4, 11) & 0xF9) == 0x9)
2581 if ((BITS (4, 11) & 0xF9) == 0x9) 2188 /* LDR register offset, no write-back, up, pre indexed. */
2582 /* LDR register offset, no write-back, up, pre indexed. */ 2189 LHPREUP ();
2583 LHPREUP (); 2190 /* Continue with remaining instruction decoding. */
2584 /* Continue with remaining instruction decoding. */
2585#endif 2191#endif
2586 rhs = DPSRegRHS; 2192 rhs = DPSRegRHS;
2587 dest = LHS | rhs; 2193 dest = LHS | rhs;
2588 WRITESDEST (dest); 2194 WRITESDEST (dest);
2589 break; 2195 break;
2590 2196
2591 case 0x1a: /* MOV reg */ 2197 case 0x1a: /* MOV reg */
2592#ifdef MODET 2198#ifdef MODET
2593 if (BITS (4, 11) == 0xB) { 2199 if (BITS (4, 11) == 0xB) {
2594 /* STRH register offset, write-back, up, pre indexed. */ 2200 /* STRH register offset, write-back, up, pre indexed. */
2595 SHPREUPWB (); 2201 SHPREUPWB ();
2596 break; 2202 break;
2597 } 2203 }
2598 if (BITS (4, 7) == 0xD) { 2204 if (BITS (4, 7) == 0xD) {
2599 Handle_Load_Double (state, instr); 2205 Handle_Load_Double (state, instr);
2600 break; 2206 break;
2601 } 2207 }
2602 if (BITS (4, 7) == 0xF) { 2208 if (BITS (4, 7) == 0xF) {
2603 Handle_Store_Double (state, instr); 2209 Handle_Store_Double (state, instr);
2604 break; 2210 break;
2605 } 2211 }
2606#endif 2212#endif
2607 dest = DPRegRHS; 2213 dest = DPRegRHS;
2608 WRITEDEST (dest); 2214 WRITEDEST (dest);
2609 break; 2215 break;
2610 2216
2611 case 0x1b: /* MOVS reg */ 2217 case 0x1b: /* MOVS reg */
2612#ifdef MODET 2218#ifdef MODET
2613 if ((BITS (4, 11) & 0xF9) == 0x9) 2219 if ((BITS (4, 11) & 0xF9) == 0x9)
2614 /* LDR register offset, write-back, up, pre indexed. */ 2220 /* LDR register offset, write-back, up, pre indexed. */
2615 LHPREUPWB (); 2221 LHPREUPWB ();
2616 /* Continue with remaining instruction decoding. */ 2222 /* Continue with remaining instruction decoding. */
2617#endif 2223#endif
2618 dest = DPSRegRHS; 2224 dest = DPSRegRHS;
2619 WRITESDEST (dest); 2225 WRITESDEST (dest);
2620 break; 2226 break;
2621 2227
2622 case 0x1c: /* BIC reg */ 2228 case 0x1c: /* BIC reg */
2623#ifdef MODET 2229#ifdef MODET
2624 /* dyf add for STREXB */ 2230 /* dyf add for STREXB */
2625 if (state->is_v6) { 2231 if (state->is_v6) {
2626 if (BITS (4, 7) == 0x9) { 2232 if (BITS (4, 7) == 0x9) {
2627 if (handle_v6_insn (state, instr)) 2233 if (handle_v6_insn (state, instr))
2628 break; 2234 break;
2235 }
2236 }
2237 if (BITS (4, 7) == 0xB) {
2238 /* STRH immediate offset, no write-back, up, pre indexed. */
2239 SHPREUP ();
2240 break;
2241 }
2242 if (BITS (4, 7) == 0xD) {
2243 Handle_Load_Double (state, instr);
2244 break;
2245 } else if (BITS (4, 7) == 0xF) {
2246 Handle_Store_Double (state, instr);
2247 break;
2629 } 2248 }
2630 }
2631 if (BITS (4, 7) == 0xB) {
2632 /* STRH immediate offset, no write-back, up, pre indexed. */
2633 SHPREUP ();
2634 break;
2635 }
2636 if (BITS (4, 7) == 0xD) {
2637 Handle_Load_Double (state, instr);
2638 break;
2639 }
2640 else if (BITS (4, 7) == 0xF) {
2641 Handle_Store_Double (state, instr);
2642 break;
2643 }
2644#endif 2249#endif
2645 rhs = DPRegRHS; 2250 rhs = DPRegRHS;
2646 dest = LHS & ~rhs; 2251 dest = LHS & ~rhs;
2647 WRITEDEST (dest); 2252 WRITEDEST (dest);
2648 break;
2649
2650 case 0x1d: /* BICS reg */
2651#ifdef MODET
2652 /* ladsh P=1 U=1 W=0 L=1 S=1 H=1 */
2653 if (BITS(4, 7) == 0xF) {
2654 temp = LHS + GetLS7RHS (state, instr);
2655 LoadHalfWord (state, instr, temp, LSIGNED);
2656 break; 2253 break;
2657 2254
2658 } 2255 case 0x1d: /* BICS reg */
2659 if (BITS (4, 7) == 0xb) { 2256#ifdef MODET
2660 /* LDRH immediate offset, no write-back, up, pre indexed. */ 2257 /* ladsh P=1 U=1 W=0 L=1 S=1 H=1 */
2661 temp = LHS + GetLS7RHS (state, instr); 2258 if (BITS(4, 7) == 0xF) {
2662 LoadHalfWord (state, instr, temp, LUNSIGNED); 2259 temp = LHS + GetLS7RHS (state, instr);
2663 break; 2260 LoadHalfWord (state, instr, temp, LSIGNED);
2664 } 2261 break;
2665 if (BITS (4, 7) == 0xd) {
2666 // alex-ykl fix: 2011-07-20 missing ldrsb instruction
2667 temp = LHS + GetLS7RHS (state, instr);
2668 LoadByte (state, instr, temp, LSIGNED);
2669 break;
2670 }
2671 2262
2672 /* Continue with instruction decoding. */
2673 /*if ((BITS (4, 7) & 0x9) == 0x9) */
2674 if ((BITS (4, 7)) == 0x9) {
2675 /* ldrexb */
2676 if (state->is_v6) {
2677 if (handle_v6_insn (state, instr))
2678 break;
2679 } 2263 }
2680 /* LDR immediate offset, no write-back, up, pre indexed. */ 2264 if (BITS (4, 7) == 0xb) {
2681 LHPREUP (); 2265 /* LDRH immediate offset, no write-back, up, pre indexed. */
2266 temp = LHS + GetLS7RHS (state, instr);
2267 LoadHalfWord (state, instr, temp, LUNSIGNED);
2268 break;
2269 }
2270 if (BITS (4, 7) == 0xd) {
2271 // alex-ykl fix: 2011-07-20 missing ldrsb instruction
2272 temp = LHS + GetLS7RHS (state, instr);
2273 LoadByte (state, instr, temp, LSIGNED);
2274 break;
2275 }
2682 2276
2683 } 2277 /* Continue with instruction decoding. */
2278 /*if ((BITS (4, 7) & 0x9) == 0x9) */
2279 if ((BITS (4, 7)) == 0x9) {
2280 /* ldrexb */
2281 if (state->is_v6) {
2282 if (handle_v6_insn (state, instr))
2283 break;
2284 }
2285 /* LDR immediate offset, no write-back, up, pre indexed. */
2286 LHPREUP ();
2287
2288 }
2684 2289
2685#endif 2290#endif
2686 rhs = DPSRegRHS; 2291 rhs = DPSRegRHS;
2687 dest = LHS & ~rhs; 2292 dest = LHS & ~rhs;
2688 WRITESDEST (dest); 2293 WRITESDEST (dest);
2689 break; 2294 break;
2690 2295
2691 case 0x1e: /* MVN reg */ 2296 case 0x1e: /* MVN reg */
2692#ifdef MODET 2297#ifdef MODET
2693 if (BITS (4, 7) == 0xB) { 2298 if ((instr & 0x00000FF0) == 0x00000F90) { //if ((instr & 0x0FF00FF0) == 0x01e00f90) { //todo make that better ichfly
2694 /* STRH immediate offset, write-back, up, pre indexed. */ 2299 /* strexh ichfly */
2695 SHPREUPWB (); 2300 u32 l = LHSReg;
2696 break; 2301 u32 r = RHSReg;
2697 } 2302 lhs = LHS;
2698 if (BITS (4, 7) == 0xD) { 2303
2699 Handle_Load_Double (state, instr); 2304 bool enter = false;
2700 break; 2305
2701 } 2306 if (state->currentexval == (u32)ARMul_LoadHalfWord(state, state->currentexaddr))enter = true;
2702 if (BITS (4, 7) == 0xF) { 2307
2703 Handle_Store_Double (state, instr); 2308
2704 break; 2309 ARMul_StoreHalfWord(state, lhs, RHS);
2705 } 2310 //StoreWord(state, lhs, RHS)
2311 if (state->Aborted) {
2312 TAKEABORT;
2313 }
2314 if (enter)
2315 {
2316 state->Reg[DESTReg] = 0;
2317 }
2318 else
2319 {
2320 state->Reg[DESTReg] = 1;
2321 }
2322 break;
2323 }
2324 if (BITS (4, 7) == 0xB) {
2325 /* STRH immediate offset, write-back, up, pre indexed. */
2326 SHPREUPWB ();
2327 break;
2328 }
2329 if (BITS (4, 7) == 0xD) {
2330 Handle_Load_Double (state, instr);
2331 break;
2332 }
2333 if (BITS (4, 7) == 0xF) {
2334 Handle_Store_Double (state, instr);
2335 break;
2336 }
2706#endif 2337#endif
2707 dest = ~DPRegRHS; 2338 dest = ~DPRegRHS;
2708 WRITEDEST (dest); 2339 WRITEDEST (dest);
2709 break; 2340 break;
2710 2341
2711 case 0x1f: /* MVNS reg */ 2342 case 0x1f: /* MVNS reg */
2712#ifdef MODET 2343#ifdef MODET
2713 if ((BITS (4, 7) & 0x9) == 0x9) 2344
2714 /* LDR immediate offset, write-back, up, pre indexed. */ 2345 if ((instr & 0x00000FF0) == 0x00000F90) { //(instr & 0x0FF00FF0) == 0x01f00f90)//if ((instr & 0x0FF00FF0) == 0x01f00f90) {
2715 LHPREUPWB (); 2346 /* ldrexh ichfly */
2716 /* Continue instruction decoding. */ 2347 lhs = LHS;
2348
2349 state->currentexaddr = lhs;
2350 state->currentexval = (u32)ARMul_LoadHalfWord(state, lhs);
2351
2352 LoadHalfWord(state, instr, lhs,0);
2353 break;
2354 }
2355
2356 if ((BITS (4, 7) & 0x9) == 0x9)
2357 /* LDR immediate offset, write-back, up, pre indexed. */
2358 LHPREUPWB ();
2359 /* Continue instruction decoding. */
2717#endif 2360#endif
2718 dest = ~DPSRegRHS; 2361 dest = ~DPSRegRHS;
2719 WRITESDEST (dest); 2362 WRITESDEST (dest);
2720 break; 2363 break;
2721 2364
2722 2365
2723 /* Data Processing Immediate RHS Instructions. */ 2366 /* Data Processing Immediate RHS Instructions. */
2724 2367
2725 case 0x20: /* AND immed */ 2368 case 0x20: /* AND immed */
2726 dest = LHS & DPImmRHS; 2369 dest = LHS & DPImmRHS;
2727 WRITEDEST (dest); 2370 WRITEDEST (dest);
2728 break; 2371 break;
2729 2372
2730 case 0x21: /* ANDS immed */ 2373 case 0x21: /* ANDS immed */
2731 DPSImmRHS; 2374 DPSImmRHS;
2732 dest = LHS & rhs; 2375 dest = LHS & rhs;
2733 WRITESDEST (dest); 2376 WRITESDEST (dest);
2734 break; 2377 break;
2735 2378
2736 case 0x22: /* EOR immed */ 2379 case 0x22: /* EOR immed */
2737 dest = LHS ^ DPImmRHS; 2380 dest = LHS ^ DPImmRHS;
2738 WRITEDEST (dest); 2381 WRITEDEST (dest);
2739 break; 2382 break;
2740 2383
2741 case 0x23: /* EORS immed */ 2384 case 0x23: /* EORS immed */
2742 DPSImmRHS; 2385 DPSImmRHS;
2743 dest = LHS ^ rhs; 2386 dest = LHS ^ rhs;
2744 WRITESDEST (dest); 2387 WRITESDEST (dest);
2745 break; 2388 break;
2746 2389
2747 case 0x24: /* SUB immed */ 2390 case 0x24: /* SUB immed */
2748 dest = LHS - DPImmRHS; 2391 dest = LHS - DPImmRHS;
2749 WRITEDEST (dest); 2392 WRITEDEST (dest);
2750 break; 2393 break;
2751 2394
2752 case 0x25: /* SUBS immed */ 2395 case 0x25: /* SUBS immed */
2753 lhs = LHS; 2396 lhs = LHS;
2754 rhs = DPImmRHS; 2397 rhs = DPImmRHS;
2755 dest = lhs - rhs; 2398 dest = lhs - rhs;
2756
2757 if ((lhs >= rhs) || ((rhs | lhs) >> 31)) {
2758 ARMul_SubCarry (state, lhs, rhs,
2759 dest);
2760 ARMul_SubOverflow (state, lhs, rhs,
2761 dest);
2762 }
2763 else {
2764 CLEARC;
2765 CLEARV;
2766 }
2767 WRITESDEST (dest);
2768 break;
2769 2399
2770 case 0x26: /* RSB immed */ 2400 if ((lhs >= rhs) || ((rhs | lhs) >> 31)) {
2771 dest = DPImmRHS - LHS; 2401 ARMul_SubCarry (state, lhs, rhs, dest);
2772 WRITEDEST (dest); 2402 ARMul_SubOverflow (state, lhs, rhs, dest);
2773 break; 2403 } else {
2404 CLEARC;
2405 CLEARV;
2406 }
2407 WRITESDEST (dest);
2408 break;
2774 2409
2775 case 0x27: /* RSBS immed */ 2410 case 0x26: /* RSB immed */
2776 lhs = LHS; 2411 dest = DPImmRHS - LHS;
2777 rhs = DPImmRHS; 2412 WRITEDEST (dest);
2778 dest = rhs - lhs; 2413 break;
2779
2780 if ((rhs >= lhs) || ((rhs | lhs) >> 31)) {
2781 ARMul_SubCarry (state, rhs, lhs,
2782 dest);
2783 ARMul_SubOverflow (state, rhs, lhs,
2784 dest);
2785 }
2786 else {
2787 CLEARC;
2788 CLEARV;
2789 }
2790 WRITESDEST (dest);
2791 break;
2792 2414
2793 case 0x28: /* ADD immed */ 2415 case 0x27: /* RSBS immed */
2794 dest = LHS + DPImmRHS; 2416 lhs = LHS;
2795 WRITEDEST (dest); 2417 rhs = DPImmRHS;
2796 break; 2418 dest = rhs - lhs;
2797 2419
2798 case 0x29: /* ADDS immed */ 2420 if ((rhs >= lhs) || ((rhs | lhs) >> 31)) {
2799 lhs = LHS; 2421 ARMul_SubCarry (state, rhs, lhs, dest);
2800 rhs = DPImmRHS; 2422 ARMul_SubOverflow (state, rhs, lhs, dest);
2801 dest = lhs + rhs; 2423 } else {
2802 ASSIGNZ (dest == 0); 2424 CLEARC;
2803 2425 CLEARV;
2804 if ((lhs | rhs) >> 30) { 2426 }
2805 /* Possible C,V,N to set. */ 2427 WRITESDEST (dest);
2806 ASSIGNN (NEG (dest)); 2428 break;
2807 ARMul_AddCarry (state, lhs, rhs,
2808 dest);
2809 ARMul_AddOverflow (state, lhs, rhs,
2810 dest);
2811 }
2812 else {
2813 CLEARN;
2814 CLEARC;
2815 CLEARV;
2816 }
2817 WRITESDEST (dest);
2818 break;
2819 2429
2820 case 0x2a: /* ADC immed */ 2430 case 0x28: /* ADD immed */
2821 dest = LHS + DPImmRHS + CFLAG; 2431 dest = LHS + DPImmRHS;
2822 WRITEDEST (dest); 2432 WRITEDEST (dest);
2823 break; 2433 break;
2824 2434
2825 case 0x2b: /* ADCS immed */ 2435 case 0x29: /* ADDS immed */
2826 lhs = LHS; 2436 lhs = LHS;
2827 rhs = DPImmRHS; 2437 rhs = DPImmRHS;
2828 dest = lhs + rhs + CFLAG; 2438 dest = lhs + rhs;
2829 ASSIGNZ (dest == 0); 2439 ASSIGNZ (dest == 0);
2830 if ((lhs | rhs) >> 30) {
2831 /* Possible C,V,N to set. */
2832 ASSIGNN (NEG (dest));
2833 ARMul_AddCarry (state, lhs, rhs,
2834 dest);
2835 ARMul_AddOverflow (state, lhs, rhs,
2836 dest);
2837 }
2838 else {
2839 CLEARN;
2840 CLEARC;
2841 CLEARV;
2842 }
2843 WRITESDEST (dest);
2844 break;
2845 2440
2846 case 0x2c: /* SBC immed */ 2441 if ((lhs | rhs) >> 30) {
2847 dest = LHS - DPImmRHS - !CFLAG; 2442 /* Possible C,V,N to set. */
2848 WRITEDEST (dest); 2443 ASSIGNN (NEG (dest));
2849 break; 2444 ARMul_AddCarry (state, lhs, rhs, dest);
2445 ARMul_AddOverflow (state, lhs, rhs, dest);
2446 } else {
2447 CLEARN;
2448 CLEARC;
2449 CLEARV;
2450 }
2451 WRITESDEST (dest);
2452 break;
2850 2453
2851 case 0x2d: /* SBCS immed */ 2454 case 0x2a: /* ADC immed */
2852 lhs = LHS; 2455 dest = LHS + DPImmRHS + CFLAG;
2853 rhs = DPImmRHS; 2456 WRITEDEST (dest);
2854 dest = lhs - rhs - !CFLAG; 2457 break;
2855 if ((lhs >= rhs) || ((rhs | lhs) >> 31)) {
2856 ARMul_SubCarry (state, lhs, rhs,
2857 dest);
2858 ARMul_SubOverflow (state, lhs, rhs,
2859 dest);
2860 }
2861 else {
2862 CLEARC;
2863 CLEARV;
2864 }
2865 WRITESDEST (dest);
2866 break;
2867 2458
2868 case 0x2e: /* RSC immed */ 2459 case 0x2b: /* ADCS immed */
2869 dest = DPImmRHS - LHS - !CFLAG; 2460 lhs = LHS;
2870 WRITEDEST (dest); 2461 rhs = DPImmRHS;
2871 break; 2462 dest = lhs + rhs + CFLAG;
2463 ASSIGNZ (dest == 0);
2464 if ((lhs | rhs) >> 30) {
2465 /* Possible C,V,N to set. */
2466 ASSIGNN (NEG (dest));
2467 ARMul_AddCarry (state, lhs, rhs, dest);
2468 ARMul_AddOverflow (state, lhs, rhs, dest);
2469 } else {
2470 CLEARN;
2471 CLEARC;
2472 CLEARV;
2473 }
2474 WRITESDEST (dest);
2475 break;
2872 2476
2873 case 0x2f: /* RSCS immed */ 2477 case 0x2c: /* SBC immed */
2874 lhs = LHS; 2478 dest = LHS - DPImmRHS - !CFLAG;
2875 rhs = DPImmRHS; 2479 WRITEDEST (dest);
2876 dest = rhs - lhs - !CFLAG; 2480 break;
2877 if ((rhs >= lhs) || ((rhs | lhs) >> 31)) {
2878 ARMul_SubCarry (state, rhs, lhs,
2879 dest);
2880 ARMul_SubOverflow (state, rhs, lhs,
2881 dest);
2882 }
2883 else {
2884 CLEARC;
2885 CLEARV;
2886 }
2887 WRITESDEST (dest);
2888 break;
2889 2481
2890 case 0x30: /* TST immed */ 2482 case 0x2d: /* SBCS immed */
2891 /* shenoubang 2012-3-14*/ 2483 lhs = LHS;
2892 if (state->is_v6) { /* movw, ARMV6, ARMv7 */ 2484 rhs = DPImmRHS;
2893 dest ^= dest; 2485 dest = lhs - rhs - !CFLAG;
2894 dest = BITS(16, 19); 2486 if ((lhs >= rhs) || ((rhs | lhs) >> 31)) {
2895 dest = ((dest<<12) | BITS(0, 11)); 2487 ARMul_SubCarry (state, lhs, rhs, dest);
2896 WRITEDEST(dest); 2488 ARMul_SubOverflow (state, lhs, rhs, dest);
2897 //SKYEYE_DBG("In %s, line = %d, pc = 0x%x, instr = 0x%x, R[0:11]: 0x%x, R[16:19]: 0x%x, R[%d]:0x%x\n", 2489 } else {
2898 // __func__, __LINE__, pc, instr, BITS(0, 11), BITS(16, 19), DESTReg, state->Reg[DESTReg]); 2490 CLEARC;
2491 CLEARV;
2492 }
2493 WRITESDEST (dest);
2899 break; 2494 break;
2900 } 2495
2901 else { 2496 case 0x2e: /* RSC immed */
2902 UNDEF_Test; 2497 dest = DPImmRHS - LHS - !CFLAG;
2498 WRITEDEST (dest);
2499 break;
2500
2501 case 0x2f: /* RSCS immed */
2502 lhs = LHS;
2503 rhs = DPImmRHS;
2504 dest = rhs - lhs - !CFLAG;
2505 if ((rhs >= lhs) || ((rhs | lhs) >> 31)) {
2506 ARMul_SubCarry (state, rhs, lhs, dest);
2507 ARMul_SubOverflow (state, rhs, lhs, dest);
2508 } else {
2509 CLEARC;
2510 CLEARV;
2511 }
2512 WRITESDEST (dest);
2903 break; 2513 break;
2904 }
2905 2514
2906 case 0x31: /* TSTP immed */ 2515 case 0x30: /* TST immed */
2907 if (DESTReg == 15) { 2516 /* shenoubang 2012-3-14*/
2908 /* TSTP immed. */ 2517 if (state->is_v6) { /* movw, ARMV6, ARMv7 */
2518 dest ^= dest;
2519 dest = BITS(16, 19);
2520 dest = ((dest<<12) | BITS(0, 11));
2521 WRITEDEST(dest);
2522 //SKYEYE_DBG("In %s, line = %d, pc = 0x%x, instr = 0x%x, R[0:11]: 0x%x, R[16:19]: 0x%x, R[%d]:0x%x\n",
2523 // __func__, __LINE__, pc, instr, BITS(0, 11), BITS(16, 19), DESTReg, state->Reg[DESTReg]);
2524 break;
2525 } else {
2526 UNDEF_Test;
2527 break;
2528 }
2529
2530 case 0x31: /* TSTP immed */
2531 if (DESTReg == 15) {
2532 /* TSTP immed. */
2909#ifdef MODE32 2533#ifdef MODE32
2910 state->Cpsr = GETSPSR (state->Bank); 2534 state->Cpsr = GETSPSR (state->Bank);
2911 ARMul_CPSRAltered (state); 2535 //ARMul_CPSRAltered (state);
2912#else 2536#else
2913 temp = LHS & DPImmRHS; 2537 temp = LHS & DPImmRHS;
2914 SETR15PSR (temp); 2538 SETR15PSR (temp);
2915#endif 2539#endif
2916 } 2540 } else {
2917 else { 2541 /* TST immed. */
2918 /* TST immed. */ 2542 DPSImmRHS;
2919 DPSImmRHS; 2543 dest = LHS & rhs;
2920 dest = LHS & rhs; 2544 ARMul_NegZero (state, dest);
2921 ARMul_NegZero (state, dest); 2545 }
2922 } 2546 break;
2923 break;
2924 2547
2925 case 0x32: /* TEQ immed and MSR immed to CPSR */ 2548 case 0x32: /* TEQ immed and MSR immed to CPSR */
2926 if (DESTReg == 15) 2549 if (DESTReg == 15)
2927 /* MSR immed to CPSR. */ 2550 /* MSR immed to CPSR. */
2928 ARMul_FixCPSR (state, instr, 2551 ARMul_FixCPSR (state, instr,
2929 DPImmRHS); 2552 DPImmRHS);
2930 else 2553 else
2931 UNDEF_Test; 2554 UNDEF_Test;
2932 break; 2555 break;
2933 2556
2934 case 0x33: /* TEQP immed */ 2557 case 0x33: /* TEQP immed */
2935 if (DESTReg == 15) { 2558 if (DESTReg == 15) {
2936 /* TEQP immed. */ 2559 /* TEQP immed. */
2937#ifdef MODE32 2560#ifdef MODE32
2938 state->Cpsr = GETSPSR (state->Bank); 2561 state->Cpsr = GETSPSR (state->Bank);
2939 ARMul_CPSRAltered (state); 2562 //ARMul_CPSRAltered (state);
2940#else 2563#else
2941 temp = LHS ^ DPImmRHS; 2564 temp = LHS ^ DPImmRHS;
2942 SETR15PSR (temp); 2565 SETR15PSR (temp);
2943#endif 2566#endif
2944 } 2567 } else {
2945 else { 2568 DPSImmRHS; /* TEQ immed */
2946 DPSImmRHS; /* TEQ immed */ 2569 dest = LHS ^ rhs;
2947 dest = LHS ^ rhs; 2570 ARMul_NegZero (state, dest);
2948 ARMul_NegZero (state, dest); 2571 }
2949 } 2572 break;
2950 break;
2951 2573
2952 case 0x34: /* CMP immed */ 2574 case 0x34: /* CMP immed */
2953 UNDEF_Test; 2575 UNDEF_Test;
2954 break; 2576 break;
2955 2577
2956 case 0x35: /* CMPP immed */ 2578 case 0x35: /* CMPP immed */
2957 if (DESTReg == 15) { 2579 if (DESTReg == 15) {
2958 /* CMPP immed. */ 2580 /* CMPP immed. */
2959#ifdef MODE32 2581#ifdef MODE32
2960 state->Cpsr = GETSPSR (state->Bank); 2582 state->Cpsr = GETSPSR (state->Bank);
2961 ARMul_CPSRAltered (state); 2583 //ARMul_CPSRAltered (state);
2962#else 2584#else
2963 temp = LHS - DPImmRHS; 2585 temp = LHS - DPImmRHS;
2964 SETR15PSR (temp); 2586 SETR15PSR (temp);
2965#endif 2587#endif
2966 break; 2588 break;
2967 } 2589 } else {
2968 else { 2590 /* CMP immed. */
2969 /* CMP immed. */ 2591 lhs = LHS;
2970 lhs = LHS; 2592 rhs = DPImmRHS;
2971 rhs = DPImmRHS; 2593 dest = lhs - rhs;
2972 dest = lhs - rhs; 2594 ARMul_NegZero (state, dest);
2973 ARMul_NegZero (state, dest);
2974 2595
2975 if ((lhs >= rhs) 2596 if ((lhs >= rhs) || ((rhs | lhs) >> 31)) {
2976 || ((rhs | lhs) >> 31)) { 2597 ARMul_SubCarry (state, lhs, rhs, dest);
2977 ARMul_SubCarry (state, lhs, 2598 ARMul_SubOverflow (state, lhs, rhs, dest);
2978 rhs, dest); 2599 } else {
2979 ARMul_SubOverflow (state, lhs, 2600 CLEARC;
2980 rhs, dest); 2601 CLEARV;
2981 } 2602 }
2982 else {
2983 CLEARC;
2984 CLEARV;
2985 } 2603 }
2986 } 2604 break;
2987 break;
2988 2605
2989 case 0x36: /* CMN immed and MSR immed to SPSR */ 2606 case 0x36: /* CMN immed and MSR immed to SPSR */
2990 if (DESTReg == 15) 2607 //if (DESTReg == 15)
2991 ARMul_FixSPSR (state, instr, 2608 /*ARMul0_FixSPSR (state, instr,
2992 DPImmRHS); 2609 DPImmRHS);*/
2993 else 2610 //else
2994 UNDEF_Test; 2611 UNDEF_Test;
2995 break; 2612 break;
2996 2613
2997 case 0x37: /* CMNP immed. */ 2614 case 0x37: /* CMNP immed. */
2998 if (DESTReg == 15) { 2615 if (DESTReg == 15) {
2999 /* CMNP immed. */ 2616 /* CMNP immed. */
3000#ifdef MODE32 2617#ifdef MODE32
3001 state->Cpsr = GETSPSR (state->Bank); 2618 state->Cpsr = GETSPSR (state->Bank);
3002 ARMul_CPSRAltered (state); 2619 //ARMul_CPSRAltered (state);
3003#else 2620#else
3004 temp = LHS + DPImmRHS; 2621 temp = LHS + DPImmRHS;
3005 SETR15PSR (temp); 2622 SETR15PSR (temp);
3006#endif 2623#endif
3007 break; 2624 break;
3008 } 2625 } else {
3009 else { 2626 /* CMN immed. */
3010 /* CMN immed. */ 2627 lhs = LHS;
3011 lhs = LHS; 2628 rhs = DPImmRHS;
3012 rhs = DPImmRHS; 2629 dest = lhs + rhs;
3013 dest = lhs + rhs; 2630 ASSIGNZ (dest == 0);
3014 ASSIGNZ (dest == 0); 2631 if ((lhs | rhs) >> 30) {
3015 if ((lhs | rhs) >> 30) { 2632 /* Possible C,V,N to set. */
3016 /* Possible C,V,N to set. */ 2633 ASSIGNN (NEG (dest));
3017 ASSIGNN (NEG (dest)); 2634 ARMul_AddCarry (state, lhs, rhs, dest);
3018 ARMul_AddCarry (state, lhs, 2635 ARMul_AddOverflow (state, lhs, rhs, dest);
3019 rhs, dest); 2636 } else {
3020 ARMul_AddOverflow (state, lhs, 2637 CLEARN;
3021 rhs, dest); 2638 CLEARC;
3022 } 2639 CLEARV;
3023 else { 2640 }
3024 CLEARN;
3025 CLEARC;
3026 CLEARV;
3027 } 2641 }
3028 } 2642 break;
3029 break;
3030 2643
3031 case 0x38: /* ORR immed. */ 2644 case 0x38: /* ORR immed. */
3032 dest = LHS | DPImmRHS; 2645 dest = LHS | DPImmRHS;
3033 WRITEDEST (dest); 2646 WRITEDEST (dest);
3034 break; 2647 break;
3035 2648
3036 case 0x39: /* ORRS immed. */ 2649 case 0x39: /* ORRS immed. */
3037 DPSImmRHS; 2650 DPSImmRHS;
3038 dest = LHS | rhs; 2651 dest = LHS | rhs;
3039 WRITESDEST (dest); 2652 WRITESDEST (dest);
3040 break; 2653 break;
3041 2654
3042 case 0x3a: /* MOV immed. */ 2655 case 0x3a: /* MOV immed. */
3043 dest = DPImmRHS; 2656 dest = DPImmRHS;
3044 WRITEDEST (dest); 2657 WRITEDEST (dest);
3045 break; 2658 break;
3046 2659
3047 case 0x3b: /* MOVS immed. */ 2660 case 0x3b: /* MOVS immed. */
3048 DPSImmRHS; 2661 DPSImmRHS;
3049 WRITESDEST (rhs); 2662 WRITESDEST (rhs);
3050 break; 2663 break;
3051 2664
3052 case 0x3c: /* BIC immed. */ 2665 case 0x3c: /* BIC immed. */
3053 dest = LHS & ~DPImmRHS; 2666 dest = LHS & ~DPImmRHS;
3054 WRITEDEST (dest); 2667 WRITEDEST (dest);
3055 break; 2668 break;
3056 2669
3057 case 0x3d: /* BICS immed. */ 2670 case 0x3d: /* BICS immed. */
3058 DPSImmRHS; 2671 DPSImmRHS;
3059 dest = LHS & ~rhs; 2672 dest = LHS & ~rhs;
3060 WRITESDEST (dest); 2673 WRITESDEST (dest);
3061 break; 2674 break;
3062 2675
3063 case 0x3e: /* MVN immed. */ 2676 case 0x3e: /* MVN immed. */
3064 dest = ~DPImmRHS; 2677 dest = ~DPImmRHS;
3065 WRITEDEST (dest); 2678 WRITEDEST (dest);
3066 break; 2679 break;
3067 2680
3068 case 0x3f: /* MVNS immed. */ 2681 case 0x3f: /* MVNS immed. */
3069 DPSImmRHS; 2682 DPSImmRHS;
3070 WRITESDEST (~rhs); 2683 WRITESDEST (~rhs);
3071 break; 2684 break;
3072 2685
3073 2686
3074 /* Single Data Transfer Immediate RHS Instructions. */ 2687 /* Single Data Transfer Immediate RHS Instructions. */
3075 2688
3076 case 0x40: /* Store Word, No WriteBack, Post Dec, Immed. */ 2689 case 0x40: /* Store Word, No WriteBack, Post Dec, Immed. */
3077 lhs = LHS; 2690 lhs = LHS;
3078 if (StoreWord (state, instr, lhs)) 2691 if (StoreWord (state, instr, lhs))
3079 LSBase = lhs - LSImmRHS; 2692 LSBase = lhs - LSImmRHS;
3080 break; 2693 break;
3081 2694
3082 case 0x41: /* Load Word, No WriteBack, Post Dec, Immed. */ 2695 case 0x41: /* Load Word, No WriteBack, Post Dec, Immed. */
3083 lhs = LHS; 2696 lhs = LHS;
3084 if (LoadWord (state, instr, lhs)) 2697 if (LoadWord (state, instr, lhs))
3085 LSBase = lhs - LSImmRHS; 2698 LSBase = lhs - LSImmRHS;
3086 break; 2699 break;
3087 2700
3088 case 0x42: /* Store Word, WriteBack, Post Dec, Immed. */ 2701 case 0x42: /* Store Word, WriteBack, Post Dec, Immed. */
3089 UNDEF_LSRBaseEQDestWb; 2702 UNDEF_LSRBaseEQDestWb;
3090 UNDEF_LSRPCBaseWb; 2703 UNDEF_LSRPCBaseWb;
3091 lhs = LHS; 2704 lhs = LHS;
3092 temp = lhs - LSImmRHS; 2705 temp = lhs - LSImmRHS;
3093 state->NtransSig = LOW; 2706 state->NtransSig = LOW;
3094 if (StoreWord (state, instr, lhs)) 2707 if (StoreWord (state, instr, lhs))
3095 LSBase = temp; 2708 LSBase = temp;
3096 state->NtransSig = 2709 state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
3097 (state->Mode & 3) ? HIGH : LOW; 2710 break;
3098 break;
3099 2711
3100 case 0x43: /* Load Word, WriteBack, Post Dec, Immed. */ 2712 case 0x43: /* Load Word, WriteBack, Post Dec, Immed. */
3101 UNDEF_LSRBaseEQDestWb; 2713 UNDEF_LSRBaseEQDestWb;
3102 UNDEF_LSRPCBaseWb; 2714 UNDEF_LSRPCBaseWb;
3103 lhs = LHS; 2715 lhs = LHS;
3104 state->NtransSig = LOW; 2716 state->NtransSig = LOW;
3105 if (LoadWord (state, instr, lhs)) 2717 if (LoadWord (state, instr, lhs))
3106 LSBase = lhs - LSImmRHS; 2718 LSBase = lhs - LSImmRHS;
3107 state->NtransSig = 2719 state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
3108 (state->Mode & 3) ? HIGH : LOW; 2720 break;
3109 break;
3110 2721
3111 case 0x44: /* Store Byte, No WriteBack, Post Dec, Immed. */ 2722 case 0x44: /* Store Byte, No WriteBack, Post Dec, Immed. */
3112 lhs = LHS; 2723 lhs = LHS;
3113 if (StoreByte (state, instr, lhs)) 2724 if (StoreByte (state, instr, lhs))
3114 LSBase = lhs - LSImmRHS; 2725 LSBase = lhs - LSImmRHS;
3115 break; 2726 break;
3116 2727
3117 case 0x45: /* Load Byte, No WriteBack, Post Dec, Immed. */ 2728 case 0x45: /* Load Byte, No WriteBack, Post Dec, Immed. */
3118 lhs = LHS; 2729 lhs = LHS;
3119 if (LoadByte (state, instr, lhs, LUNSIGNED)) 2730 if (LoadByte (state, instr, lhs, LUNSIGNED))
3120 LSBase = lhs - LSImmRHS; 2731 LSBase = lhs - LSImmRHS;
3121 break; 2732 break;
3122 2733
3123 case 0x46: /* Store Byte, WriteBack, Post Dec, Immed. */ 2734 case 0x46: /* Store Byte, WriteBack, Post Dec, Immed. */
3124 UNDEF_LSRBaseEQDestWb; 2735 UNDEF_LSRBaseEQDestWb;
3125 UNDEF_LSRPCBaseWb; 2736 UNDEF_LSRPCBaseWb;
3126 lhs = LHS; 2737 lhs = LHS;
3127 state->NtransSig = LOW; 2738 state->NtransSig = LOW;
3128 if (StoreByte (state, instr, lhs)) 2739 if (StoreByte (state, instr, lhs))
3129 LSBase = lhs - LSImmRHS; 2740 LSBase = lhs - LSImmRHS;
3130 state->NtransSig = 2741 state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
3131 (state->Mode & 3) ? HIGH : LOW; 2742 break;
3132 break;
3133 2743
3134 case 0x47: /* Load Byte, WriteBack, Post Dec, Immed. */ 2744 case 0x47: /* Load Byte, WriteBack, Post Dec, Immed. */
3135 UNDEF_LSRBaseEQDestWb; 2745 UNDEF_LSRBaseEQDestWb;
3136 UNDEF_LSRPCBaseWb; 2746 UNDEF_LSRPCBaseWb;
3137 lhs = LHS; 2747 lhs = LHS;
3138 state->NtransSig = LOW; 2748 state->NtransSig = LOW;
3139 if (LoadByte (state, instr, lhs, LUNSIGNED)) 2749 if (LoadByte (state, instr, lhs, LUNSIGNED))
3140 LSBase = lhs - LSImmRHS; 2750 LSBase = lhs - LSImmRHS;
3141 state->NtransSig = 2751 state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
3142 (state->Mode & 3) ? HIGH : LOW; 2752 break;
3143 break;
3144 2753
3145 case 0x48: /* Store Word, No WriteBack, Post Inc, Immed. */ 2754 case 0x48: /* Store Word, No WriteBack, Post Inc, Immed. */
3146 lhs = LHS; 2755 lhs = LHS;
3147 if (StoreWord (state, instr, lhs)) 2756 if (StoreWord (state, instr, lhs))
3148 LSBase = lhs + LSImmRHS; 2757 LSBase = lhs + LSImmRHS;
3149 break; 2758 break;
3150 2759
3151 case 0x49: /* Load Word, No WriteBack, Post Inc, Immed. */ 2760 case 0x49: /* Load Word, No WriteBack, Post Inc, Immed. */
3152 lhs = LHS; 2761 lhs = LHS;
3153 if (LoadWord (state, instr, lhs)) 2762 if (LoadWord (state, instr, lhs))
3154 LSBase = lhs + LSImmRHS; 2763 LSBase = lhs + LSImmRHS;
3155 break; 2764 break;
3156 2765
3157 case 0x4a: /* Store Word, WriteBack, Post Inc, Immed. */ 2766 case 0x4a: /* Store Word, WriteBack, Post Inc, Immed. */
3158 UNDEF_LSRBaseEQDestWb; 2767 UNDEF_LSRBaseEQDestWb;
3159 UNDEF_LSRPCBaseWb; 2768 UNDEF_LSRPCBaseWb;
3160 lhs = LHS; 2769 lhs = LHS;
3161 state->NtransSig = LOW; 2770 state->NtransSig = LOW;
3162 if (StoreWord (state, instr, lhs)) 2771 if (StoreWord (state, instr, lhs))
3163 LSBase = lhs + LSImmRHS; 2772 LSBase = lhs + LSImmRHS;
3164 state->NtransSig = 2773 state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
3165 (state->Mode & 3) ? HIGH : LOW; 2774 break;
3166 break;
3167 2775
3168 case 0x4b: /* Load Word, WriteBack, Post Inc, Immed. */ 2776 case 0x4b: /* Load Word, WriteBack, Post Inc, Immed. */
3169 UNDEF_LSRBaseEQDestWb; 2777 UNDEF_LSRBaseEQDestWb;
3170 UNDEF_LSRPCBaseWb; 2778 UNDEF_LSRPCBaseWb;
3171 lhs = LHS; 2779 lhs = LHS;
3172 state->NtransSig = LOW; 2780 state->NtransSig = LOW;
3173 if (LoadWord (state, instr, lhs)) 2781 if (LoadWord (state, instr, lhs))
3174 LSBase = lhs + LSImmRHS; 2782 LSBase = lhs + LSImmRHS;
3175 state->NtransSig = 2783 state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
3176 (state->Mode & 3) ? HIGH : LOW; 2784 break;
3177 break;
3178 2785
3179 case 0x4c: /* Store Byte, No WriteBack, Post Inc, Immed. */ 2786 case 0x4c: /* Store Byte, No WriteBack, Post Inc, Immed. */
3180 lhs = LHS; 2787 lhs = LHS;
3181 if (StoreByte (state, instr, lhs)) 2788 if (StoreByte (state, instr, lhs))
3182 LSBase = lhs + LSImmRHS; 2789 LSBase = lhs + LSImmRHS;
3183 break; 2790 break;
3184 2791
3185 case 0x4d: /* Load Byte, No WriteBack, Post Inc, Immed. */ 2792 case 0x4d: /* Load Byte, No WriteBack, Post Inc, Immed. */
3186 lhs = LHS; 2793 lhs = LHS;
3187 if (LoadByte (state, instr, lhs, LUNSIGNED)) 2794 if (LoadByte (state, instr, lhs, LUNSIGNED))
3188 LSBase = lhs + LSImmRHS; 2795 LSBase = lhs + LSImmRHS;
3189 break; 2796 break;
3190 2797
3191 case 0x4e: /* Store Byte, WriteBack, Post Inc, Immed. */ 2798 case 0x4e: /* Store Byte, WriteBack, Post Inc, Immed. */
3192 UNDEF_LSRBaseEQDestWb; 2799 UNDEF_LSRBaseEQDestWb;
3193 UNDEF_LSRPCBaseWb; 2800 UNDEF_LSRPCBaseWb;
3194 lhs = LHS; 2801 lhs = LHS;
3195 state->NtransSig = LOW; 2802 state->NtransSig = LOW;
3196 if (StoreByte (state, instr, lhs)) 2803 if (StoreByte (state, instr, lhs))
3197 LSBase = lhs + LSImmRHS; 2804 LSBase = lhs + LSImmRHS;
3198 state->NtransSig = 2805 state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
3199 (state->Mode & 3) ? HIGH : LOW; 2806 break;
3200 break;
3201 2807
3202 case 0x4f: /* Load Byte, WriteBack, Post Inc, Immed. */ 2808 case 0x4f: /* Load Byte, WriteBack, Post Inc, Immed. */
3203 UNDEF_LSRBaseEQDestWb; 2809 UNDEF_LSRBaseEQDestWb;
3204 UNDEF_LSRPCBaseWb; 2810 UNDEF_LSRPCBaseWb;
3205 lhs = LHS; 2811 lhs = LHS;
3206 state->NtransSig = LOW; 2812 state->NtransSig = LOW;
3207 if (LoadByte (state, instr, lhs, LUNSIGNED)) 2813 if (LoadByte (state, instr, lhs, LUNSIGNED))
3208 LSBase = lhs + LSImmRHS; 2814 LSBase = lhs + LSImmRHS;
3209 state->NtransSig = 2815 state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
3210 (state->Mode & 3) ? HIGH : LOW; 2816 break;
3211 break;
3212 2817
3213 2818
3214 case 0x50: /* Store Word, No WriteBack, Pre Dec, Immed. */ 2819 case 0x50: /* Store Word, No WriteBack, Pre Dec, Immed. */
3215 (void) StoreWord (state, instr, 2820 (void) StoreWord (state, instr, LHS - LSImmRHS);
3216 LHS - LSImmRHS); 2821 break;
3217 break;
3218 2822
3219 case 0x51: /* Load Word, No WriteBack, Pre Dec, Immed. */ 2823 case 0x51: /* Load Word, No WriteBack, Pre Dec, Immed. */
3220 (void) LoadWord (state, instr, 2824 (void) LoadWord (state, instr, LHS - LSImmRHS);
3221 LHS - LSImmRHS); 2825 break;
3222 break;
3223 2826
3224 case 0x52: /* Store Word, WriteBack, Pre Dec, Immed. */ 2827 case 0x52: /* Store Word, WriteBack, Pre Dec, Immed. */
3225 UNDEF_LSRBaseEQDestWb; 2828 UNDEF_LSRBaseEQDestWb;
3226 UNDEF_LSRPCBaseWb; 2829 UNDEF_LSRPCBaseWb;
3227 temp = LHS - LSImmRHS; 2830 temp = LHS - LSImmRHS;
3228 if (StoreWord (state, instr, temp)) 2831 if (StoreWord (state, instr, temp))
3229 LSBase = temp; 2832 LSBase = temp;
3230 break; 2833 break;
3231 2834
3232 case 0x53: /* Load Word, WriteBack, Pre Dec, Immed. */ 2835 case 0x53: /* Load Word, WriteBack, Pre Dec, Immed. */
3233 UNDEF_LSRBaseEQDestWb; 2836 UNDEF_LSRBaseEQDestWb;
3234 UNDEF_LSRPCBaseWb; 2837 UNDEF_LSRPCBaseWb;
3235 temp = LHS - LSImmRHS; 2838 temp = LHS - LSImmRHS;
3236 if (LoadWord (state, instr, temp)) 2839 if (LoadWord (state, instr, temp))
3237 LSBase = temp; 2840 LSBase = temp;
3238 break; 2841 break;
3239 2842
3240 case 0x54: /* Store Byte, No WriteBack, Pre Dec, Immed. */ 2843 case 0x54: /* Store Byte, No WriteBack, Pre Dec, Immed. */
3241 (void) StoreByte (state, instr, 2844 (void) StoreByte (state, instr, LHS - LSImmRHS);
3242 LHS - LSImmRHS); 2845 break;
3243 break;
3244 2846
3245 case 0x55: /* Load Byte, No WriteBack, Pre Dec, Immed. */ 2847 case 0x55: /* Load Byte, No WriteBack, Pre Dec, Immed. */
3246 (void) LoadByte (state, instr, LHS - LSImmRHS, 2848 (void) LoadByte (state, instr, LHS - LSImmRHS, LUNSIGNED);
3247 LUNSIGNED); 2849 break;
3248 break;
3249 2850
3250 case 0x56: /* Store Byte, WriteBack, Pre Dec, Immed. */ 2851 case 0x56: /* Store Byte, WriteBack, Pre Dec, Immed. */
3251 UNDEF_LSRBaseEQDestWb; 2852 UNDEF_LSRBaseEQDestWb;
3252 UNDEF_LSRPCBaseWb; 2853 UNDEF_LSRPCBaseWb;
3253 temp = LHS - LSImmRHS; 2854 temp = LHS - LSImmRHS;
3254 if (StoreByte (state, instr, temp)) 2855 if (StoreByte (state, instr, temp))
3255 LSBase = temp; 2856 LSBase = temp;
3256 break; 2857 break;
3257 2858
3258 case 0x57: /* Load Byte, WriteBack, Pre Dec, Immed. */ 2859 case 0x57: /* Load Byte, WriteBack, Pre Dec, Immed. */
3259 UNDEF_LSRBaseEQDestWb; 2860 UNDEF_LSRBaseEQDestWb;
3260 UNDEF_LSRPCBaseWb; 2861 UNDEF_LSRPCBaseWb;
3261 temp = LHS - LSImmRHS; 2862 temp = LHS - LSImmRHS;
3262 if (LoadByte (state, instr, temp, LUNSIGNED)) 2863 if (LoadByte (state, instr, temp, LUNSIGNED))
3263 LSBase = temp; 2864 LSBase = temp;
3264 break; 2865 break;
3265 2866
3266 case 0x58: /* Store Word, No WriteBack, Pre Inc, Immed. */ 2867 case 0x58: /* Store Word, No WriteBack, Pre Inc, Immed. */
3267 (void) StoreWord (state, instr, 2868 (void) StoreWord (state, instr, LHS + LSImmRHS);
3268 LHS + LSImmRHS); 2869 break;
3269 break;
3270 2870
3271 case 0x59: /* Load Word, No WriteBack, Pre Inc, Immed. */ 2871 case 0x59: /* Load Word, No WriteBack, Pre Inc, Immed. */
3272 (void) LoadWord (state, instr, 2872 (void) LoadWord (state, instr, LHS + LSImmRHS);
3273 LHS + LSImmRHS); 2873 break;
3274 break;
3275 2874
3276 case 0x5a: /* Store Word, WriteBack, Pre Inc, Immed. */ 2875 case 0x5a: /* Store Word, WriteBack, Pre Inc, Immed. */
3277 UNDEF_LSRBaseEQDestWb; 2876 UNDEF_LSRBaseEQDestWb;
3278 UNDEF_LSRPCBaseWb; 2877 UNDEF_LSRPCBaseWb;
3279 temp = LHS + LSImmRHS; 2878 temp = LHS + LSImmRHS;
3280 if (StoreWord (state, instr, temp)) 2879 if (StoreWord (state, instr, temp))
3281 LSBase = temp; 2880 LSBase = temp;
3282 break; 2881 break;
3283 2882
3284 case 0x5b: /* Load Word, WriteBack, Pre Inc, Immed. */ 2883 case 0x5b: /* Load Word, WriteBack, Pre Inc, Immed. */
3285 UNDEF_LSRBaseEQDestWb; 2884 UNDEF_LSRBaseEQDestWb;
3286 UNDEF_LSRPCBaseWb; 2885 UNDEF_LSRPCBaseWb;
3287 temp = LHS + LSImmRHS; 2886 temp = LHS + LSImmRHS;
3288 if (LoadWord (state, instr, temp)) 2887 if (LoadWord (state, instr, temp))
3289 LSBase = temp; 2888 LSBase = temp;
3290 break; 2889 break;
3291 2890
3292 case 0x5c: /* Store Byte, No WriteBack, Pre Inc, Immed. */ 2891 case 0x5c: /* Store Byte, No WriteBack, Pre Inc, Immed. */
3293 (void) StoreByte (state, instr, 2892 (void) StoreByte (state, instr, LHS + LSImmRHS);
3294 LHS + LSImmRHS); 2893 break;
3295 break;
3296 2894
3297 case 0x5d: /* Load Byte, No WriteBack, Pre Inc, Immed. */ 2895 case 0x5d: /* Load Byte, No WriteBack, Pre Inc, Immed. */
3298 (void) LoadByte (state, instr, LHS + LSImmRHS, 2896 (void) LoadByte (state, instr, LHS + LSImmRHS, LUNSIGNED);
3299 LUNSIGNED); 2897 break;
3300 break;
3301 2898
3302 case 0x5e: /* Store Byte, WriteBack, Pre Inc, Immed. */ 2899 case 0x5e: /* Store Byte, WriteBack, Pre Inc, Immed. */
3303 UNDEF_LSRBaseEQDestWb; 2900 UNDEF_LSRBaseEQDestWb;
3304 UNDEF_LSRPCBaseWb; 2901 UNDEF_LSRPCBaseWb;
3305 temp = LHS + LSImmRHS; 2902 temp = LHS + LSImmRHS;
3306 if (StoreByte (state, instr, temp)) 2903 if (StoreByte (state, instr, temp))
3307 LSBase = temp; 2904 LSBase = temp;
3308 break; 2905 break;
3309 2906
3310 case 0x5f: /* Load Byte, WriteBack, Pre Inc, Immed. */ 2907 case 0x5f: /* Load Byte, WriteBack, Pre Inc, Immed. */
3311 UNDEF_LSRBaseEQDestWb; 2908 UNDEF_LSRBaseEQDestWb;
3312 UNDEF_LSRPCBaseWb; 2909 UNDEF_LSRPCBaseWb;
3313 temp = LHS + LSImmRHS; 2910 temp = LHS + LSImmRHS;
3314 if (LoadByte (state, instr, temp, LUNSIGNED)) 2911 if (LoadByte (state, instr, temp, LUNSIGNED))
3315 LSBase = temp; 2912 LSBase = temp;
3316 break; 2913 break;
3317 2914
3318 2915
3319 /* Single Data Transfer Register RHS Instructions. */ 2916 /* Single Data Transfer Register RHS Instructions. */
3320 2917
3321 case 0x60: /* Store Word, No WriteBack, Post Dec, Reg. */ 2918 case 0x60: /* Store Word, No WriteBack, Post Dec, Reg. */
3322 if (BIT (4)) { 2919 if (BIT (4)) {
3323 ARMul_UndefInstr (state, instr); 2920 ARMul_UndefInstr (state, instr);
2921 break;
2922 }
2923 UNDEF_LSRBaseEQOffWb;
2924 UNDEF_LSRBaseEQDestWb;
2925 UNDEF_LSRPCBaseWb;
2926 UNDEF_LSRPCOffWb;
2927 lhs = LHS;
2928 if (StoreWord (state, instr, lhs))
2929 LSBase = lhs - LSRegRHS;
3324 break; 2930 break;
3325 }
3326 UNDEF_LSRBaseEQOffWb;
3327 UNDEF_LSRBaseEQDestWb;
3328 UNDEF_LSRPCBaseWb;
3329 UNDEF_LSRPCOffWb;
3330 lhs = LHS;
3331 if (StoreWord (state, instr, lhs))
3332 LSBase = lhs - LSRegRHS;
3333 break;
3334 2931
3335 case 0x61: /* Load Word, No WriteBack, Post Dec, Reg. */ 2932 case 0x61: /* Load Word, No WriteBack, Post Dec, Reg. */
3336 if (BIT (4)) { 2933 if (BIT (4)) {
3337#ifdef MODE32 2934#ifdef MODE32
3338 if (state->is_v6 2935 if (state->is_v6 && handle_v6_insn (state, instr))
3339 && handle_v6_insn (state, instr)) 2936 break;
3340 break;
3341#endif 2937#endif
3342 2938 ARMul_UndefInstr (state, instr);
3343 ARMul_UndefInstr (state, instr); 2939 break;
2940 }
2941 UNDEF_LSRBaseEQOffWb;
2942 UNDEF_LSRBaseEQDestWb;
2943 UNDEF_LSRPCBaseWb;
2944 UNDEF_LSRPCOffWb;
2945 lhs = LHS;
2946 temp = lhs - LSRegRHS;
2947 if (LoadWord (state, instr, lhs))
2948 LSBase = temp;
3344 break; 2949 break;
3345 }
3346 UNDEF_LSRBaseEQOffWb;
3347 UNDEF_LSRBaseEQDestWb;
3348 UNDEF_LSRPCBaseWb;
3349 UNDEF_LSRPCOffWb;
3350 lhs = LHS;
3351 temp = lhs - LSRegRHS;
3352 if (LoadWord (state, instr, lhs))
3353 LSBase = temp;
3354 break;
3355 2950
3356 case 0x62: /* Store Word, WriteBack, Post Dec, Reg. */ 2951 case 0x62: /* Store Word, WriteBack, Post Dec, Reg. */
3357 if (BIT (4)) { 2952 if (BIT (4)) {
3358#ifdef MODE32 2953#ifdef MODE32
3359 if (state->is_v6 2954 if (state->is_v6 && handle_v6_insn (state, instr))
3360 && handle_v6_insn (state, instr)) 2955 break;
3361 break;
3362#endif 2956#endif
3363 2957 ARMul_UndefInstr (state, instr);
3364 ARMul_UndefInstr (state, instr); 2958 break;
2959 }
2960 UNDEF_LSRBaseEQOffWb;
2961 UNDEF_LSRBaseEQDestWb;
2962 UNDEF_LSRPCBaseWb;
2963 UNDEF_LSRPCOffWb;
2964 lhs = LHS;
2965 state->NtransSig = LOW;
2966 if (StoreWord (state, instr, lhs))
2967 LSBase = lhs - LSRegRHS;
2968 state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
3365 break; 2969 break;
3366 }
3367 UNDEF_LSRBaseEQOffWb;
3368 UNDEF_LSRBaseEQDestWb;
3369 UNDEF_LSRPCBaseWb;
3370 UNDEF_LSRPCOffWb;
3371 lhs = LHS;
3372 state->NtransSig = LOW;
3373 if (StoreWord (state, instr, lhs))
3374 LSBase = lhs - LSRegRHS;
3375 state->NtransSig =
3376 (state->Mode & 3) ? HIGH : LOW;
3377 break;
3378 2970
3379 case 0x63: /* Load Word, WriteBack, Post Dec, Reg. */ 2971 case 0x63: /* Load Word, WriteBack, Post Dec, Reg. */
3380 if (BIT (4)) { 2972 if (BIT (4)) {
3381#ifdef MODE32 2973#ifdef MODE32
3382 if (state->is_v6 2974 if (state->is_v6 && handle_v6_insn (state, instr))
3383 && handle_v6_insn (state, instr)) 2975 break;
3384 break;
3385#endif 2976#endif
3386 2977 ARMul_UndefInstr (state, instr);
3387 ARMul_UndefInstr (state, instr); 2978 break;
2979 }
2980 UNDEF_LSRBaseEQOffWb;
2981 UNDEF_LSRBaseEQDestWb;
2982 UNDEF_LSRPCBaseWb;
2983 UNDEF_LSRPCOffWb;
2984 lhs = LHS;
2985 temp = lhs - LSRegRHS;
2986 state->NtransSig = LOW;
2987 if (LoadWord (state, instr, lhs))
2988 LSBase = temp;
2989 state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
3388 break; 2990 break;
3389 }
3390 UNDEF_LSRBaseEQOffWb;
3391 UNDEF_LSRBaseEQDestWb;
3392 UNDEF_LSRPCBaseWb;
3393 UNDEF_LSRPCOffWb;
3394 lhs = LHS;
3395 temp = lhs - LSRegRHS;
3396 state->NtransSig = LOW;
3397 if (LoadWord (state, instr, lhs))
3398 LSBase = temp;
3399 state->NtransSig =
3400 (state->Mode & 3) ? HIGH : LOW;
3401 break;
3402 2991
3403 case 0x64: /* Store Byte, No WriteBack, Post Dec, Reg. */ 2992 case 0x64: /* Store Byte, No WriteBack, Post Dec, Reg. */
3404 if (BIT (4)) { 2993 if (BIT (4)) {
3405 ARMul_UndefInstr (state, instr); 2994 ARMul_UndefInstr (state, instr);
2995 break;
2996 }
2997 UNDEF_LSRBaseEQOffWb;
2998 UNDEF_LSRBaseEQDestWb;
2999 UNDEF_LSRPCBaseWb;
3000 UNDEF_LSRPCOffWb;
3001 lhs = LHS;
3002 if (StoreByte (state, instr, lhs))
3003 LSBase = lhs - LSRegRHS;
3406 break; 3004 break;
3407 }
3408 UNDEF_LSRBaseEQOffWb;
3409 UNDEF_LSRBaseEQDestWb;
3410 UNDEF_LSRPCBaseWb;
3411 UNDEF_LSRPCOffWb;
3412 lhs = LHS;
3413 if (StoreByte (state, instr, lhs))
3414 LSBase = lhs - LSRegRHS;
3415 break;
3416 3005
3417 case 0x65: /* Load Byte, No WriteBack, Post Dec, Reg. */ 3006 case 0x65: /* Load Byte, No WriteBack, Post Dec, Reg. */
3418 if (BIT (4)) { 3007 if (BIT (4)) {
3419#ifdef MODE32 3008#ifdef MODE32
3420 if (state->is_v6 3009 if (state->is_v6 && handle_v6_insn (state, instr))
3421 && handle_v6_insn (state, instr)) 3010 break;
3422 break;
3423#endif 3011#endif
3424 3012 ARMul_UndefInstr (state, instr);
3425 ARMul_UndefInstr (state, instr); 3013 break;
3014 }
3015 UNDEF_LSRBaseEQOffWb;
3016 UNDEF_LSRBaseEQDestWb;
3017 UNDEF_LSRPCBaseWb;
3018 UNDEF_LSRPCOffWb;
3019 lhs = LHS;
3020 temp = lhs - LSRegRHS;
3021 if (LoadByte (state, instr, lhs, LUNSIGNED))
3022 LSBase = temp;
3426 break; 3023 break;
3427 }
3428 UNDEF_LSRBaseEQOffWb;
3429 UNDEF_LSRBaseEQDestWb;
3430 UNDEF_LSRPCBaseWb;
3431 UNDEF_LSRPCOffWb;
3432 lhs = LHS;
3433 temp = lhs - LSRegRHS;
3434 if (LoadByte (state, instr, lhs, LUNSIGNED))
3435 LSBase = temp;
3436 break;
3437 3024
3438 case 0x66: /* Store Byte, WriteBack, Post Dec, Reg. */ 3025 case 0x66: /* Store Byte, WriteBack, Post Dec, Reg. */
3439 if (BIT (4)) { 3026 if (BIT (4)) {
3440#ifdef MODE32 3027#ifdef MODE32
3441 if (state->is_v6 3028 if (state->is_v6 && handle_v6_insn (state, instr))
3442 && handle_v6_insn (state, instr)) 3029 break;
3443 break;
3444#endif 3030#endif
3445 3031 ARMul_UndefInstr (state, instr);
3446 ARMul_UndefInstr (state, instr); 3032 break;
3033 }
3034 UNDEF_LSRBaseEQOffWb;
3035 UNDEF_LSRBaseEQDestWb;
3036 UNDEF_LSRPCBaseWb;
3037 UNDEF_LSRPCOffWb;
3038 lhs = LHS;
3039 state->NtransSig = LOW;
3040 if (StoreByte (state, instr, lhs))
3041 LSBase = lhs - LSRegRHS;
3042 state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
3447 break; 3043 break;
3448 }
3449 UNDEF_LSRBaseEQOffWb;
3450 UNDEF_LSRBaseEQDestWb;
3451 UNDEF_LSRPCBaseWb;
3452 UNDEF_LSRPCOffWb;
3453 lhs = LHS;
3454 state->NtransSig = LOW;
3455 if (StoreByte (state, instr, lhs))
3456 LSBase = lhs - LSRegRHS;
3457 state->NtransSig =
3458 (state->Mode & 3) ? HIGH : LOW;
3459 break;
3460 3044
3461 case 0x67: /* Load Byte, WriteBack, Post Dec, Reg. */ 3045 case 0x67: /* Load Byte, WriteBack, Post Dec, Reg. */
3462 if (BIT (4)) { 3046 if (BIT (4)) {
3463#ifdef MODE32 3047#ifdef MODE32
3464 if (state->is_v6 3048 if (state->is_v6
3465 && handle_v6_insn (state, instr)) 3049 && handle_v6_insn (state, instr))
3466 break; 3050 break;
3467#endif 3051#endif
3468 3052
3469 ARMul_UndefInstr (state, instr); 3053 ARMul_UndefInstr (state, instr);
3054 break;
3055 }
3056 UNDEF_LSRBaseEQOffWb;
3057 UNDEF_LSRBaseEQDestWb;
3058 UNDEF_LSRPCBaseWb;
3059 UNDEF_LSRPCOffWb;
3060 lhs = LHS;
3061 temp = lhs - LSRegRHS;
3062 state->NtransSig = LOW;
3063 if (LoadByte (state, instr, lhs, LUNSIGNED))
3064 LSBase = temp;
3065 state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
3470 break; 3066 break;
3471 }
3472 UNDEF_LSRBaseEQOffWb;
3473 UNDEF_LSRBaseEQDestWb;
3474 UNDEF_LSRPCBaseWb;
3475 UNDEF_LSRPCOffWb;
3476 lhs = LHS;
3477 temp = lhs - LSRegRHS;
3478 state->NtransSig = LOW;
3479 if (LoadByte (state, instr, lhs, LUNSIGNED))
3480 LSBase = temp;
3481 state->NtransSig =
3482 (state->Mode & 3) ? HIGH : LOW;
3483 break;
3484 3067
3485 case 0x68: /* Store Word, No WriteBack, Post Inc, Reg. */ 3068 case 0x68: /* Store Word, No WriteBack, Post Inc, Reg. */
3486 if (BIT (4)) { 3069 if (BIT (4)) {
3487#ifdef MODE32 3070#ifdef MODE32
3488 if (state->is_v6 3071 if (state->is_v6
3489 && handle_v6_insn (state, instr)) 3072 && handle_v6_insn (state, instr))
3490 break; 3073 break;
3491#endif 3074#endif
3492 3075
3493 ARMul_UndefInstr (state, instr); 3076 ARMul_UndefInstr (state, instr);
3077 break;
3078 }
3079 UNDEF_LSRBaseEQOffWb;
3080 UNDEF_LSRBaseEQDestWb;
3081 UNDEF_LSRPCBaseWb;
3082 UNDEF_LSRPCOffWb;
3083 lhs = LHS;
3084 if (StoreWord (state, instr, lhs))
3085 LSBase = lhs + LSRegRHS;
3494 break; 3086 break;
3495 }
3496 UNDEF_LSRBaseEQOffWb;
3497 UNDEF_LSRBaseEQDestWb;
3498 UNDEF_LSRPCBaseWb;
3499 UNDEF_LSRPCOffWb;
3500 lhs = LHS;
3501 if (StoreWord (state, instr, lhs))
3502 LSBase = lhs + LSRegRHS;
3503 break;
3504 3087
3505 case 0x69: /* Load Word, No WriteBack, Post Inc, Reg. */ 3088 case 0x69: /* Load Word, No WriteBack, Post Inc, Reg. */
3506 if (BIT (4)) { 3089 if (BIT (4)) {
3507 ARMul_UndefInstr (state, instr); 3090 ARMul_UndefInstr (state, instr);
3091 break;
3092 }
3093 UNDEF_LSRBaseEQOffWb;
3094 UNDEF_LSRBaseEQDestWb;
3095 UNDEF_LSRPCBaseWb;
3096 UNDEF_LSRPCOffWb;
3097 lhs = LHS;
3098 temp = lhs + LSRegRHS;
3099 if (LoadWord (state, instr, lhs))
3100 LSBase = temp;
3508 break; 3101 break;
3509 }
3510 UNDEF_LSRBaseEQOffWb;
3511 UNDEF_LSRBaseEQDestWb;
3512 UNDEF_LSRPCBaseWb;
3513 UNDEF_LSRPCOffWb;
3514 lhs = LHS;
3515 temp = lhs + LSRegRHS;
3516 if (LoadWord (state, instr, lhs))
3517 LSBase = temp;
3518 break;
3519 3102
3520 case 0x6a: /* Store Word, WriteBack, Post Inc, Reg. */ 3103 case 0x6a: /* Store Word, WriteBack, Post Inc, Reg. */
3521 if (BIT (4)) { 3104 if (BIT (4)) {
3522#ifdef MODE32 3105#ifdef MODE32
3523 if (state->is_v6 3106 if (state->is_v6
3524 && handle_v6_insn (state, instr)) 3107 && handle_v6_insn (state, instr))
3525 break; 3108 break;
3526#endif 3109#endif
3527 3110
3528 ARMul_UndefInstr (state, instr); 3111 ARMul_UndefInstr (state, instr);
3112 break;
3113 }
3114 UNDEF_LSRBaseEQOffWb;
3115 UNDEF_LSRBaseEQDestWb;
3116 UNDEF_LSRPCBaseWb;
3117 UNDEF_LSRPCOffWb;
3118 lhs = LHS;
3119 state->NtransSig = LOW;
3120 if (StoreWord (state, instr, lhs))
3121 LSBase = lhs + LSRegRHS;
3122 state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
3529 break; 3123 break;
3530 }
3531 UNDEF_LSRBaseEQOffWb;
3532 UNDEF_LSRBaseEQDestWb;
3533 UNDEF_LSRPCBaseWb;
3534 UNDEF_LSRPCOffWb;
3535 lhs = LHS;
3536 state->NtransSig = LOW;
3537 if (StoreWord (state, instr, lhs))
3538 LSBase = lhs + LSRegRHS;
3539 state->NtransSig =
3540 (state->Mode & 3) ? HIGH : LOW;
3541 break;
3542 3124
3543 case 0x6b: /* Load Word, WriteBack, Post Inc, Reg. */ 3125 case 0x6b: /* Load Word, WriteBack, Post Inc, Reg. */
3544 if (BIT (4)) { 3126 if (BIT (4)) {
3545#ifdef MODE32 3127#ifdef MODE32
3546 if (state->is_v6 3128 if (state->is_v6
3547 && handle_v6_insn (state, instr)) 3129 && handle_v6_insn (state, instr))
3548 break; 3130 break;
3549#endif 3131#endif
3550 3132
3551 ARMul_UndefInstr (state, instr); 3133 ARMul_UndefInstr (state, instr);
3134 break;
3135 }
3136 UNDEF_LSRBaseEQOffWb;
3137 UNDEF_LSRBaseEQDestWb;
3138 UNDEF_LSRPCBaseWb;
3139 UNDEF_LSRPCOffWb;
3140 lhs = LHS;
3141 temp = lhs + LSRegRHS;
3142 state->NtransSig = LOW;
3143 if (LoadWord (state, instr, lhs))
3144 LSBase = temp;
3145 state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
3552 break; 3146 break;
3553 }
3554 UNDEF_LSRBaseEQOffWb;
3555 UNDEF_LSRBaseEQDestWb;
3556 UNDEF_LSRPCBaseWb;
3557 UNDEF_LSRPCOffWb;
3558 lhs = LHS;
3559 temp = lhs + LSRegRHS;
3560 state->NtransSig = LOW;
3561 if (LoadWord (state, instr, lhs))
3562 LSBase = temp;
3563 state->NtransSig =
3564 (state->Mode & 3) ? HIGH : LOW;
3565 break;
3566 3147
3567 case 0x6c: /* Store Byte, No WriteBack, Post Inc, Reg. */ 3148 case 0x6c: /* Store Byte, No WriteBack, Post Inc, Reg. */
3568 if (BIT (4)) { 3149 if (BIT (4)) {
3569#ifdef MODE32 3150#ifdef MODE32
3570 if (state->is_v6 3151 if (state->is_v6
3571 && handle_v6_insn (state, instr)) 3152 && handle_v6_insn (state, instr))
3572 break; 3153 break;
3573#endif 3154#endif
3574 3155
3575 ARMul_UndefInstr (state, instr); 3156 ARMul_UndefInstr (state, instr);
3157 break;
3158 }
3159 UNDEF_LSRBaseEQOffWb;
3160 UNDEF_LSRBaseEQDestWb;
3161 UNDEF_LSRPCBaseWb;
3162 UNDEF_LSRPCOffWb;
3163 lhs = LHS;
3164 if (StoreByte (state, instr, lhs))
3165 LSBase = lhs + LSRegRHS;
3576 break; 3166 break;
3577 }
3578 UNDEF_LSRBaseEQOffWb;
3579 UNDEF_LSRBaseEQDestWb;
3580 UNDEF_LSRPCBaseWb;
3581 UNDEF_LSRPCOffWb;
3582 lhs = LHS;
3583 if (StoreByte (state, instr, lhs))
3584 LSBase = lhs + LSRegRHS;
3585 break;
3586 3167
3587 case 0x6d: /* Load Byte, No WriteBack, Post Inc, Reg. */ 3168 case 0x6d: /* Load Byte, No WriteBack, Post Inc, Reg. */
3588 if (BIT (4)) { 3169 if (BIT (4)) {
3589 ARMul_UndefInstr (state, instr); 3170 ARMul_UndefInstr (state, instr);
3171 break;
3172 }
3173 UNDEF_LSRBaseEQOffWb;
3174 UNDEF_LSRBaseEQDestWb;
3175 UNDEF_LSRPCBaseWb;
3176 UNDEF_LSRPCOffWb;
3177 lhs = LHS;
3178 temp = lhs + LSRegRHS;
3179 if (LoadByte (state, instr, lhs, LUNSIGNED))
3180 LSBase = temp;
3590 break; 3181 break;
3591 }
3592 UNDEF_LSRBaseEQOffWb;
3593 UNDEF_LSRBaseEQDestWb;
3594 UNDEF_LSRPCBaseWb;
3595 UNDEF_LSRPCOffWb;
3596 lhs = LHS;
3597 temp = lhs + LSRegRHS;
3598 if (LoadByte (state, instr, lhs, LUNSIGNED))
3599 LSBase = temp;
3600 break;
3601 3182
3602 case 0x6e: /* Store Byte, WriteBack, Post Inc, Reg. */ 3183 case 0x6e: /* Store Byte, WriteBack, Post Inc, Reg. */
3603#if 0 3184#if 0
3604 if (state->is_v6) { 3185 if (state->is_v6) {
3605 int Rm = 0; 3186 int Rm = 0;
3606 /* utxb */ 3187 /* utxb */
3607 if (BITS(15, 19) == 0xf && BITS(4, 7) == 0x7) { 3188 if (BITS(15, 19) == 0xf && BITS(4, 7) == 0x7) {
3608 3189
3609 Rm = (RHS >> (8 * BITS(10, 11))) & 0xff; 3190 Rm = (RHS >> (8 * BITS(10, 11))) & 0xff;
3610 DEST = Rm; 3191 DEST = Rm;
3611 } 3192 }
3612 3193
3613 } 3194 }
3614#endif 3195#endif
3615 if (BIT (4)) { 3196 if (BIT (4)) {
3616#ifdef MODE32 3197#ifdef MODE32
3617 if (state->is_v6 3198 if (state->is_v6
3618 && handle_v6_insn (state, instr)) 3199 && handle_v6_insn (state, instr))
3619 break; 3200 break;
3620#endif 3201#endif
3621 3202
3622 ARMul_UndefInstr (state, instr); 3203 ARMul_UndefInstr (state, instr);
3204 break;
3205 }
3206 UNDEF_LSRBaseEQOffWb;
3207 UNDEF_LSRBaseEQDestWb;
3208 UNDEF_LSRPCBaseWb;
3209 UNDEF_LSRPCOffWb;
3210 lhs = LHS;
3211 state->NtransSig = LOW;
3212 if (StoreByte (state, instr, lhs))
3213 LSBase = lhs + LSRegRHS;
3214 state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
3623 break; 3215 break;
3624 }
3625 UNDEF_LSRBaseEQOffWb;
3626 UNDEF_LSRBaseEQDestWb;
3627 UNDEF_LSRPCBaseWb;
3628 UNDEF_LSRPCOffWb;
3629 lhs = LHS;
3630 state->NtransSig = LOW;
3631 if (StoreByte (state, instr, lhs))
3632 LSBase = lhs + LSRegRHS;
3633 state->NtransSig =
3634 (state->Mode & 3) ? HIGH : LOW;
3635 break;
3636 3216
3637 case 0x6f: /* Load Byte, WriteBack, Post Inc, Reg. */ 3217 case 0x6f: /* Load Byte, WriteBack, Post Inc, Reg. */
3638 if (BIT (4)) { 3218 if (BIT (4)) {
3639#ifdef MODE32 3219#ifdef MODE32
3640 if (state->is_v6 3220 if (state->is_v6
3641 && handle_v6_insn (state, instr)) 3221 && handle_v6_insn (state, instr))
3642 break; 3222 break;
3643#endif 3223#endif
3644 3224
3645 ARMul_UndefInstr (state, instr); 3225 ARMul_UndefInstr (state, instr);
3226 break;
3227 }
3228 UNDEF_LSRBaseEQOffWb;
3229 UNDEF_LSRBaseEQDestWb;
3230 UNDEF_LSRPCBaseWb;
3231 UNDEF_LSRPCOffWb;
3232 lhs = LHS;
3233 temp = lhs + LSRegRHS;
3234 state->NtransSig = LOW;
3235 if (LoadByte (state, instr, lhs, LUNSIGNED))
3236 LSBase = temp;
3237 state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
3646 break; 3238 break;
3647 }
3648 UNDEF_LSRBaseEQOffWb;
3649 UNDEF_LSRBaseEQDestWb;
3650 UNDEF_LSRPCBaseWb;
3651 UNDEF_LSRPCOffWb;
3652 lhs = LHS;
3653 temp = lhs + LSRegRHS;
3654 state->NtransSig = LOW;
3655 if (LoadByte (state, instr, lhs, LUNSIGNED))
3656 LSBase = temp;
3657 state->NtransSig =
3658 (state->Mode & 3) ? HIGH : LOW;
3659 break;
3660 3239
3661 3240
3662 case 0x70: /* Store Word, No WriteBack, Pre Dec, Reg. */ 3241 case 0x70: /* Store Word, No WriteBack, Pre Dec, Reg. */
3663 if (BIT (4)) { 3242 if (BIT (4)) {
3664#ifdef MODE32 3243#ifdef MODE32
3665 if (state->is_v6 3244 if (state->is_v6 && handle_v6_insn (state, instr))
3666 && handle_v6_insn (state, instr)) 3245 break;
3667 break;
3668#endif 3246#endif
3669 3247 ARMul_UndefInstr (state, instr);
3670 ARMul_UndefInstr (state, instr); 3248 break;
3249 }
3250 (void) StoreWord (state, instr, LHS - LSRegRHS);
3671 break; 3251 break;
3672 }
3673 (void) StoreWord (state, instr,
3674 LHS - LSRegRHS);
3675 break;
3676 3252
3677 case 0x71: /* Load Word, No WriteBack, Pre Dec, Reg. */ 3253 case 0x71: /* Load Word, No WriteBack, Pre Dec, Reg. */
3678 if (BIT (4)) { 3254 if (BIT (4)) {
3679 ARMul_UndefInstr (state, instr); 3255 ARMul_UndefInstr (state, instr);
3256 break;
3257 }
3258 (void) LoadWord (state, instr, LHS - LSRegRHS);
3680 break; 3259 break;
3681 }
3682 (void) LoadWord (state, instr,
3683 LHS - LSRegRHS);
3684 break;
3685 3260
3686 case 0x72: /* Store Word, WriteBack, Pre Dec, Reg. */ 3261 case 0x72: /* Store Word, WriteBack, Pre Dec, Reg. */
3687 if (BIT (4)) { 3262 if (BIT (4)) {
3688 ARMul_UndefInstr (state, instr); 3263 ARMul_UndefInstr (state, instr);
3264 break;
3265 }
3266 UNDEF_LSRBaseEQOffWb;
3267 UNDEF_LSRBaseEQDestWb;
3268 UNDEF_LSRPCBaseWb;
3269 UNDEF_LSRPCOffWb;
3270 temp = LHS - LSRegRHS;
3271 if (StoreWord (state, instr, temp))
3272 LSBase = temp;
3689 break; 3273 break;
3690 }
3691 UNDEF_LSRBaseEQOffWb;
3692 UNDEF_LSRBaseEQDestWb;
3693 UNDEF_LSRPCBaseWb;
3694 UNDEF_LSRPCOffWb;
3695 temp = LHS - LSRegRHS;
3696 if (StoreWord (state, instr, temp))
3697 LSBase = temp;
3698 break;
3699 3274
3700 case 0x73: /* Load Word, WriteBack, Pre Dec, Reg. */ 3275 case 0x73: /* Load Word, WriteBack, Pre Dec, Reg. */
3701 if (BIT (4)) { 3276 if (BIT (4)) {
3702 ARMul_UndefInstr (state, instr); 3277 ARMul_UndefInstr (state, instr);
3278 break;
3279 }
3280 UNDEF_LSRBaseEQOffWb;
3281 UNDEF_LSRBaseEQDestWb;
3282 UNDEF_LSRPCBaseWb;
3283 UNDEF_LSRPCOffWb;
3284 temp = LHS - LSRegRHS;
3285 if (LoadWord (state, instr, temp))
3286 LSBase = temp;
3703 break; 3287 break;
3704 }
3705 UNDEF_LSRBaseEQOffWb;
3706 UNDEF_LSRBaseEQDestWb;
3707 UNDEF_LSRPCBaseWb;
3708 UNDEF_LSRPCOffWb;
3709 temp = LHS - LSRegRHS;
3710 if (LoadWord (state, instr, temp))
3711 LSBase = temp;
3712 break;
3713 3288
3714 case 0x74: /* Store Byte, No WriteBack, Pre Dec, Reg. */ 3289 case 0x74: /* Store Byte, No WriteBack, Pre Dec, Reg. */
3715 if (BIT (4)) { 3290 if (BIT (4)) {
3716#ifdef MODE32 3291#ifdef MODE32
3717 if (state->is_v6 3292 if (state->is_v6 && handle_v6_insn (state, instr))
3718 && handle_v6_insn (state, instr)) 3293 break;
3719 break;
3720#endif 3294#endif
3721 3295 ARMul_UndefInstr (state, instr);
3722 ARMul_UndefInstr (state, instr); 3296 break;
3297 }
3298 (void) StoreByte (state, instr, LHS - LSRegRHS);
3723 break; 3299 break;
3724 }
3725 (void) StoreByte (state, instr,
3726 LHS - LSRegRHS);
3727 break;
3728 3300
3729 case 0x75: /* Load Byte, No WriteBack, Pre Dec, Reg. */ 3301 case 0x75: /* Load Byte, No WriteBack, Pre Dec, Reg. */
3730 if (BIT (4)) { 3302 if (BIT (4)) {
3731#ifdef MODE32 3303#ifdef MODE32
3732 if (state->is_v6 3304 if (state->is_v6 && handle_v6_insn (state, instr))
3733 && handle_v6_insn (state, instr)) 3305 break;
3734 break;
3735#endif 3306#endif
3736 3307 ARMul_UndefInstr (state, instr);
3737 ARMul_UndefInstr (state, instr); 3308 break;
3309 }
3310 (void) LoadByte (state, instr, LHS - LSRegRHS, LUNSIGNED);
3738 break; 3311 break;
3739 }
3740 (void) LoadByte (state, instr, LHS - LSRegRHS,
3741 LUNSIGNED);
3742 break;
3743 3312
3744 case 0x76: /* Store Byte, WriteBack, Pre Dec, Reg. */ 3313 case 0x76: /* Store Byte, WriteBack, Pre Dec, Reg. */
3745 if (BIT (4)) { 3314 if (BIT (4)) {
3746 ARMul_UndefInstr (state, instr); 3315 ARMul_UndefInstr (state, instr);
3316 break;
3317 }
3318 UNDEF_LSRBaseEQOffWb;
3319 UNDEF_LSRBaseEQDestWb;
3320 UNDEF_LSRPCBaseWb;
3321 UNDEF_LSRPCOffWb;
3322 temp = LHS - LSRegRHS;
3323 if (StoreByte (state, instr, temp))
3324 LSBase = temp;
3747 break; 3325 break;
3748 }
3749 UNDEF_LSRBaseEQOffWb;
3750 UNDEF_LSRBaseEQDestWb;
3751 UNDEF_LSRPCBaseWb;
3752 UNDEF_LSRPCOffWb;
3753 temp = LHS - LSRegRHS;
3754 if (StoreByte (state, instr, temp))
3755 LSBase = temp;
3756 break;
3757 3326
3758 case 0x77: /* Load Byte, WriteBack, Pre Dec, Reg. */ 3327 case 0x77: /* Load Byte, WriteBack, Pre Dec, Reg. */
3759 if (BIT (4)) { 3328 if (BIT (4)) {
3760 ARMul_UndefInstr (state, instr); 3329 ARMul_UndefInstr (state, instr);
3330 break;
3331 }
3332 UNDEF_LSRBaseEQOffWb;
3333 UNDEF_LSRBaseEQDestWb;
3334 UNDEF_LSRPCBaseWb;
3335 UNDEF_LSRPCOffWb;
3336 temp = LHS - LSRegRHS;
3337 if (LoadByte (state, instr, temp, LUNSIGNED))
3338 LSBase = temp;
3761 break; 3339 break;
3762 }
3763 UNDEF_LSRBaseEQOffWb;
3764 UNDEF_LSRBaseEQDestWb;
3765 UNDEF_LSRPCBaseWb;
3766 UNDEF_LSRPCOffWb;
3767 temp = LHS - LSRegRHS;
3768 if (LoadByte (state, instr, temp, LUNSIGNED))
3769 LSBase = temp;
3770 break;
3771 3340
3772 case 0x78: /* Store Word, No WriteBack, Pre Inc, Reg. */ 3341 case 0x78: /* Store Word, No WriteBack, Pre Inc, Reg. */
3773 if (BIT (4)) { 3342 if (BIT (4)) {
3774#ifdef MODE32 3343#ifdef MODE32
3775 if (state->is_v6 3344 if (state->is_v6 && handle_v6_insn (state, instr))
3776 && handle_v6_insn (state, instr)) 3345 break;
3777 break;
3778#endif 3346#endif
3779 3347
3780 ARMul_UndefInstr (state, instr); 3348 ARMul_UndefInstr (state, instr);
3349 break;
3350 }
3351 (void) StoreWord (state, instr, LHS + LSRegRHS);
3781 break; 3352 break;
3782 }
3783 (void) StoreWord (state, instr,
3784 LHS + LSRegRHS);
3785 break;
3786 3353
3787 case 0x79: /* Load Word, No WriteBack, Pre Inc, Reg. */ 3354 case 0x79: /* Load Word, No WriteBack, Pre Inc, Reg. */
3788 if (BIT (4)) { 3355 if (BIT (4)) {
3789 ARMul_UndefInstr (state, instr); 3356 ARMul_UndefInstr (state, instr);
3357 break;
3358 }
3359 (void) LoadWord (state, instr, LHS + LSRegRHS);
3790 break; 3360 break;
3791 }
3792 (void) LoadWord (state, instr,
3793 LHS + LSRegRHS);
3794 break;
3795 3361
3796 case 0x7a: /* Store Word, WriteBack, Pre Inc, Reg. */ 3362 case 0x7a: /* Store Word, WriteBack, Pre Inc, Reg. */
3797 if (BIT (4)) { 3363 if (BIT (4)) {
3798#ifdef MODE32 3364#ifdef MODE32
3799 if (state->is_v6 3365 if (state->is_v6 && handle_v6_insn (state, instr))
3800 && handle_v6_insn (state, instr)) 3366 break;
3801 break;
3802#endif 3367#endif
3803 3368
3804 ARMul_UndefInstr (state, instr); 3369 ARMul_UndefInstr (state, instr);
3370 break;
3371 }
3372 UNDEF_LSRBaseEQOffWb;
3373 UNDEF_LSRBaseEQDestWb;
3374 UNDEF_LSRPCBaseWb;
3375 UNDEF_LSRPCOffWb;
3376 temp = LHS + LSRegRHS;
3377 if (StoreWord (state, instr, temp))
3378 LSBase = temp;
3805 break; 3379 break;
3806 }
3807 UNDEF_LSRBaseEQOffWb;
3808 UNDEF_LSRBaseEQDestWb;
3809 UNDEF_LSRPCBaseWb;
3810 UNDEF_LSRPCOffWb;
3811 temp = LHS + LSRegRHS;
3812 if (StoreWord (state, instr, temp))
3813 LSBase = temp;
3814 break;
3815 3380
3816 case 0x7b: /* Load Word, WriteBack, Pre Inc, Reg. */ 3381 case 0x7b: /* Load Word, WriteBack, Pre Inc, Reg. */
3817 if (BIT (4)) { 3382 if (BIT (4)) {
3818 ARMul_UndefInstr (state, instr); 3383 ARMul_UndefInstr (state, instr);
3384 break;
3385 }
3386 UNDEF_LSRBaseEQOffWb;
3387 UNDEF_LSRBaseEQDestWb;
3388 UNDEF_LSRPCBaseWb;
3389 UNDEF_LSRPCOffWb;
3390 temp = LHS + LSRegRHS;
3391 if (LoadWord (state, instr, temp))
3392 LSBase = temp;
3819 break; 3393 break;
3820 }
3821 UNDEF_LSRBaseEQOffWb;
3822 UNDEF_LSRBaseEQDestWb;
3823 UNDEF_LSRPCBaseWb;
3824 UNDEF_LSRPCOffWb;
3825 temp = LHS + LSRegRHS;
3826 if (LoadWord (state, instr, temp))
3827 LSBase = temp;
3828 break;
3829 3394
3830 case 0x7c: /* Store Byte, No WriteBack, Pre Inc, Reg. */ 3395 case 0x7c: /* Store Byte, No WriteBack, Pre Inc, Reg. */
3831 if (BIT (4)) { 3396 if (BIT (4)) {
3832#ifdef MODE32 3397#ifdef MODE32
3833 if (state->is_v6 3398 if (state->is_v6 && handle_v6_insn (state, instr))
3834 && handle_v6_insn (state, instr)) 3399 break;
3835 break;
3836#endif 3400#endif
3837 3401
3838 ARMul_UndefInstr (state, instr); 3402 ARMul_UndefInstr (state, instr);
3403 break;
3404 }
3405 (void) StoreByte (state, instr, LHS + LSRegRHS);
3839 break; 3406 break;
3840 }
3841 (void) StoreByte (state, instr,
3842 LHS + LSRegRHS);
3843 break;
3844 3407
3845 case 0x7d: /* Load Byte, No WriteBack, Pre Inc, Reg. */ 3408 case 0x7d: /* Load Byte, No WriteBack, Pre Inc, Reg. */
3846 if (BIT (4)) { 3409 if (BIT (4)) {
3847 ARMul_UndefInstr (state, instr); 3410 ARMul_UndefInstr (state, instr);
3411 break;
3412 }
3413 (void) LoadByte (state, instr, LHS + LSRegRHS, LUNSIGNED);
3848 break; 3414 break;
3849 }
3850 (void) LoadByte (state, instr, LHS + LSRegRHS,
3851 LUNSIGNED);
3852 break;
3853 3415
3854 case 0x7e: /* Store Byte, WriteBack, Pre Inc, Reg. */ 3416 case 0x7e: /* Store Byte, WriteBack, Pre Inc, Reg. */
3855 if (BIT (4)) { 3417 if (BIT (4)) {
3856 ARMul_UndefInstr (state, instr); 3418 ARMul_UndefInstr (state, instr);
3419 break;
3420 }
3421 UNDEF_LSRBaseEQOffWb;
3422 UNDEF_LSRBaseEQDestWb;
3423 UNDEF_LSRPCBaseWb;
3424 UNDEF_LSRPCOffWb;
3425 temp = LHS + LSRegRHS;
3426 if (StoreByte (state, instr, temp))
3427 LSBase = temp;
3857 break; 3428 break;
3858 }
3859 UNDEF_LSRBaseEQOffWb;
3860 UNDEF_LSRBaseEQDestWb;
3861 UNDEF_LSRPCBaseWb;
3862 UNDEF_LSRPCOffWb;
3863 temp = LHS + LSRegRHS;
3864 if (StoreByte (state, instr, temp))
3865 LSBase = temp;
3866 break;
3867 3429
3868 case 0x7f: /* Load Byte, WriteBack, Pre Inc, Reg. */ 3430 case 0x7f: /* Load Byte, WriteBack, Pre Inc, Reg. */
3869 if (BIT (4)) { 3431 if (BIT (4)) {
3870 /* Check for the special breakpoint opcode. 3432 DEBUG("got unhandled special breakpoint\n");
3871 This value should correspond to the value defined 3433 return 1;
3872 as ARM_BE_BREAKPOINT in gdb/arm/tm-arm.h. */
3873 if (BITS (0, 19) == 0xfdefe) {
3874 if (!ARMul_OSHandleSWI
3875 (state, SWI_Breakpoint))
3876 ARMul_Abort (state,
3877 ARMul_SWIV);
3878 } 3434 }
3879 else 3435 UNDEF_LSRBaseEQOffWb;
3880 ARMul_UndefInstr (state, 3436 UNDEF_LSRBaseEQDestWb;
3881 instr); 3437 UNDEF_LSRPCBaseWb;
3438 UNDEF_LSRPCOffWb;
3439 temp = LHS + LSRegRHS;
3440 if (LoadByte (state, instr, temp, LUNSIGNED))
3441 LSBase = temp;
3882 break; 3442 break;
3883 }
3884 UNDEF_LSRBaseEQOffWb;
3885 UNDEF_LSRBaseEQDestWb;
3886 UNDEF_LSRPCBaseWb;
3887 UNDEF_LSRPCOffWb;
3888 temp = LHS + LSRegRHS;
3889 if (LoadByte (state, instr, temp, LUNSIGNED))
3890 LSBase = temp;
3891 break;
3892 3443
3893 3444
3894 /* Multiple Data Transfer Instructions. */ 3445 /* Multiple Data Transfer Instructions. */
3895 3446
3896 case 0x80: /* Store, No WriteBack, Post Dec. */ 3447 case 0x80: /* Store, No WriteBack, Post Dec. */
3897 STOREMULT (instr, LSBase - LSMNumRegs + 4L, 3448 STOREMULT (instr, LSBase - LSMNumRegs + 4L, 0L);
3898 0L); 3449 break;
3899 break;
3900 3450
3901 case 0x81: /* Load, No WriteBack, Post Dec. */ 3451 case 0x81: /* Load, No WriteBack, Post Dec. */
3902 LOADMULT (instr, LSBase - LSMNumRegs + 4L, 3452 LOADMULT (instr, LSBase - LSMNumRegs + 4L, 0L);
3903 0L); 3453 break;
3904 break;
3905 3454
3906 case 0x82: /* Store, WriteBack, Post Dec. */ 3455 case 0x82: /* Store, WriteBack, Post Dec. */
3907 temp = LSBase - LSMNumRegs; 3456 temp = LSBase - LSMNumRegs;
3908 STOREMULT (instr, temp + 4L, temp); 3457 STOREMULT (instr, temp + 4L, temp);
3909 break; 3458 break;
3910 3459
3911 case 0x83: /* Load, WriteBack, Post Dec. */ 3460 case 0x83: /* Load, WriteBack, Post Dec. */
3912 temp = LSBase - LSMNumRegs; 3461 temp = LSBase - LSMNumRegs;
3913 LOADMULT (instr, temp + 4L, temp); 3462 LOADMULT (instr, temp + 4L, temp);
3914 break; 3463 break;
3915 3464
3916 case 0x84: /* Store, Flags, No WriteBack, Post Dec. */ 3465 case 0x84: /* Store, Flags, No WriteBack, Post Dec. */
3917 STORESMULT (instr, LSBase - LSMNumRegs + 4L, 3466 STORESMULT (instr, LSBase - LSMNumRegs + 4L, 0L);
3918 0L); 3467 break;
3919 break;
3920 3468
3921 case 0x85: /* Load, Flags, No WriteBack, Post Dec. */ 3469 case 0x85: /* Load, Flags, No WriteBack, Post Dec. */
3922 LOADSMULT (instr, LSBase - LSMNumRegs + 4L, 3470 LOADSMULT (instr, LSBase - LSMNumRegs + 4L, 0L);
3923 0L); 3471 break;
3924 break;
3925 3472
3926 case 0x86: /* Store, Flags, WriteBack, Post Dec. */ 3473 case 0x86: /* Store, Flags, WriteBack, Post Dec. */
3927 temp = LSBase - LSMNumRegs; 3474 temp = LSBase - LSMNumRegs;
3928 STORESMULT (instr, temp + 4L, temp); 3475 STORESMULT (instr, temp + 4L, temp);
3929 break; 3476 break;
3930 3477
3931 case 0x87: /* Load, Flags, WriteBack, Post Dec. */ 3478 case 0x87: /* Load, Flags, WriteBack, Post Dec. */
3932 temp = LSBase - LSMNumRegs; 3479 temp = LSBase - LSMNumRegs;
3933 LOADSMULT (instr, temp + 4L, temp); 3480 LOADSMULT (instr, temp + 4L, temp);
3934 break; 3481 break;
3935 3482
3936 case 0x88: /* Store, No WriteBack, Post Inc. */ 3483 case 0x88: /* Store, No WriteBack, Post Inc. */
3937 STOREMULT (instr, LSBase, 0L); 3484 STOREMULT (instr, LSBase, 0L);
3938 break; 3485 break;
3939 3486
3940 case 0x89: /* Load, No WriteBack, Post Inc. */ 3487 case 0x89: /* Load, No WriteBack, Post Inc. */
3941 LOADMULT (instr, LSBase, 0L); 3488 LOADMULT (instr, LSBase, 0L);
3942 break; 3489 break;
3943 3490
3944 case 0x8a: /* Store, WriteBack, Post Inc. */ 3491 case 0x8a: /* Store, WriteBack, Post Inc. */
3945 temp = LSBase; 3492 temp = LSBase;
3946 STOREMULT (instr, temp, temp + LSMNumRegs); 3493 STOREMULT (instr, temp, temp + LSMNumRegs);
3947 break; 3494 break;
3948 3495
3949 case 0x8b: /* Load, WriteBack, Post Inc. */ 3496 case 0x8b: /* Load, WriteBack, Post Inc. */
3950 temp = LSBase; 3497 temp = LSBase;
3951 LOADMULT (instr, temp, temp + LSMNumRegs); 3498 LOADMULT (instr, temp, temp + LSMNumRegs);
3952 break; 3499 break;
3953 3500
3954 case 0x8c: /* Store, Flags, No WriteBack, Post Inc. */ 3501 case 0x8c: /* Store, Flags, No WriteBack, Post Inc. */
3955 STORESMULT (instr, LSBase, 0L); 3502 STORESMULT (instr, LSBase, 0L);
3956 break; 3503 break;
3957 3504
3958 case 0x8d: /* Load, Flags, No WriteBack, Post Inc. */ 3505 case 0x8d: /* Load, Flags, No WriteBack, Post Inc. */
3959 LOADSMULT (instr, LSBase, 0L); 3506 LOADSMULT (instr, LSBase, 0L);
3960 break; 3507 break;
3961 3508
3962 case 0x8e: /* Store, Flags, WriteBack, Post Inc. */ 3509 case 0x8e: /* Store, Flags, WriteBack, Post Inc. */
3963 temp = LSBase; 3510 temp = LSBase;
3964 STORESMULT (instr, temp, temp + LSMNumRegs); 3511 STORESMULT (instr, temp, temp + LSMNumRegs);
3965 break; 3512 break;
3966 3513
3967 case 0x8f: /* Load, Flags, WriteBack, Post Inc. */ 3514 case 0x8f: /* Load, Flags, WriteBack, Post Inc. */
3968 temp = LSBase; 3515 temp = LSBase;
3969 LOADSMULT (instr, temp, temp + LSMNumRegs); 3516 LOADSMULT (instr, temp, temp + LSMNumRegs);
3970 break; 3517 break;
3971 3518
3972 case 0x90: /* Store, No WriteBack, Pre Dec. */ 3519 case 0x90: /* Store, No WriteBack, Pre Dec. */
3973 STOREMULT (instr, LSBase - LSMNumRegs, 0L); 3520 STOREMULT (instr, LSBase - LSMNumRegs, 0L);
3974 break; 3521 break;
3975 3522
3976 case 0x91: /* Load, No WriteBack, Pre Dec. */ 3523 case 0x91: /* Load, No WriteBack, Pre Dec. */
3977 LOADMULT (instr, LSBase - LSMNumRegs, 0L); 3524 LOADMULT (instr, LSBase - LSMNumRegs, 0L);
3978 break; 3525 break;
3979 3526
3980 case 0x92: /* Store, WriteBack, Pre Dec. */ 3527 case 0x92: /* Store, WriteBack, Pre Dec. */
3981 temp = LSBase - LSMNumRegs; 3528 temp = LSBase - LSMNumRegs;
3982 STOREMULT (instr, temp, temp); 3529 STOREMULT (instr, temp, temp);
3983 break; 3530 break;
3984 3531
3985 case 0x93: /* Load, WriteBack, Pre Dec. */ 3532 case 0x93: /* Load, WriteBack, Pre Dec. */
3986 temp = LSBase - LSMNumRegs; 3533 temp = LSBase - LSMNumRegs;
3987 LOADMULT (instr, temp, temp); 3534 LOADMULT (instr, temp, temp);
3988 break; 3535 break;
3989 3536
3990 case 0x94: /* Store, Flags, No WriteBack, Pre Dec. */ 3537 case 0x94: /* Store, Flags, No WriteBack, Pre Dec. */
3991 STORESMULT (instr, LSBase - LSMNumRegs, 0L); 3538 STORESMULT (instr, LSBase - LSMNumRegs, 0L);
3992 break; 3539 break;
3993 3540
3994 case 0x95: /* Load, Flags, No WriteBack, Pre Dec. */ 3541 case 0x95: /* Load, Flags, No WriteBack, Pre Dec. */
3995 LOADSMULT (instr, LSBase - LSMNumRegs, 0L); 3542 LOADSMULT (instr, LSBase - LSMNumRegs, 0L);
3996 break; 3543 break;
3997 3544
3998 case 0x96: /* Store, Flags, WriteBack, Pre Dec. */ 3545 case 0x96: /* Store, Flags, WriteBack, Pre Dec. */
3999 temp = LSBase - LSMNumRegs; 3546 temp = LSBase - LSMNumRegs;
4000 STORESMULT (instr, temp, temp); 3547 STORESMULT (instr, temp, temp);
4001 break; 3548 break;
4002 3549
4003 case 0x97: /* Load, Flags, WriteBack, Pre Dec. */ 3550 case 0x97: /* Load, Flags, WriteBack, Pre Dec. */
4004 temp = LSBase - LSMNumRegs; 3551 temp = LSBase - LSMNumRegs;
4005 LOADSMULT (instr, temp, temp); 3552 LOADSMULT (instr, temp, temp);
4006 break; 3553 break;
4007 3554
4008 case 0x98: /* Store, No WriteBack, Pre Inc. */ 3555 case 0x98: /* Store, No WriteBack, Pre Inc. */
4009 STOREMULT (instr, LSBase + 4L, 0L); 3556 STOREMULT (instr, LSBase + 4L, 0L);
4010 break; 3557 break;
4011 3558
4012 case 0x99: /* Load, No WriteBack, Pre Inc. */ 3559 case 0x99: /* Load, No WriteBack, Pre Inc. */
4013 LOADMULT (instr, LSBase + 4L, 0L); 3560 LOADMULT (instr, LSBase + 4L, 0L);
4014 break; 3561 break;
4015 3562
4016 case 0x9a: /* Store, WriteBack, Pre Inc. */ 3563 case 0x9a: /* Store, WriteBack, Pre Inc. */
4017 temp = LSBase; 3564 temp = LSBase;
4018 STOREMULT (instr, temp + 4L, 3565 STOREMULT (instr, temp + 4L, temp + LSMNumRegs);
4019 temp + LSMNumRegs); 3566 break;
4020 break;
4021 3567
4022 case 0x9b: /* Load, WriteBack, Pre Inc. */ 3568 case 0x9b: /* Load, WriteBack, Pre Inc. */
4023 temp = LSBase; 3569 temp = LSBase;
4024 LOADMULT (instr, temp + 4L, 3570 LOADMULT (instr, temp + 4L, temp + LSMNumRegs);
4025 temp + LSMNumRegs); 3571 break;
4026 break;
4027 3572
4028 case 0x9c: /* Store, Flags, No WriteBack, Pre Inc. */ 3573 case 0x9c: /* Store, Flags, No WriteBack, Pre Inc. */
4029 STORESMULT (instr, LSBase + 4L, 0L); 3574 STORESMULT (instr, LSBase + 4L, 0L);
4030 break; 3575 break;
4031 3576
4032 case 0x9d: /* Load, Flags, No WriteBack, Pre Inc. */ 3577 case 0x9d: /* Load, Flags, No WriteBack, Pre Inc. */
4033 LOADSMULT (instr, LSBase + 4L, 0L); 3578 LOADSMULT (instr, LSBase + 4L, 0L);
4034 break; 3579 break;
4035 3580
4036 case 0x9e: /* Store, Flags, WriteBack, Pre Inc. */ 3581 case 0x9e: /* Store, Flags, WriteBack, Pre Inc. */
4037 temp = LSBase; 3582 temp = LSBase;
4038 STORESMULT (instr, temp + 4L, 3583 STORESMULT (instr, temp + 4L, temp + LSMNumRegs);
4039 temp + LSMNumRegs); 3584 break;
4040 break;
4041 3585
4042 case 0x9f: /* Load, Flags, WriteBack, Pre Inc. */ 3586 case 0x9f: /* Load, Flags, WriteBack, Pre Inc. */
4043 temp = LSBase; 3587 temp = LSBase;
4044 LOADSMULT (instr, temp + 4L, 3588 LOADSMULT (instr, temp + 4L, temp + LSMNumRegs);
4045 temp + LSMNumRegs); 3589 break;
4046 break;
4047 3590
4048 3591
4049 /* Branch forward. */ 3592 /* Branch forward. */
4050 case 0xa0: 3593 case 0xa0:
4051 case 0xa1: 3594 case 0xa1:
4052 case 0xa2: 3595 case 0xa2:
4053 case 0xa3: 3596 case 0xa3:
4054 case 0xa4: 3597 case 0xa4:
4055 case 0xa5: 3598 case 0xa5:
4056 case 0xa6: 3599 case 0xa6:
4057 case 0xa7: 3600 case 0xa7:
4058 state->Reg[15] = pc + 8 + POSBRANCH; 3601 state->Reg[15] = pc + 8 + POSBRANCH;
4059 FLUSHPIPE; 3602 FLUSHPIPE;
4060 break; 3603 break;
4061 3604
4062 3605
4063 /* Branch backward. */ 3606 /* Branch backward. */
4064 case 0xa8: 3607 case 0xa8:
4065 case 0xa9: 3608 case 0xa9:
4066 case 0xaa: 3609 case 0xaa:
4067 case 0xab: 3610 case 0xab:
4068 case 0xac: 3611 case 0xac:
4069 case 0xad: 3612 case 0xad:
4070 case 0xae: 3613 case 0xae:
4071 case 0xaf: 3614 case 0xaf:
4072 state->Reg[15] = pc + 8 + NEGBRANCH; 3615 state->Reg[15] = pc + 8 + NEGBRANCH;
4073 FLUSHPIPE; 3616 FLUSHPIPE;
4074 break; 3617 break;
4075 3618
4076 3619
4077 /* Branch and Link forward. */ 3620 /* Branch and Link forward. */
4078 case 0xb0: 3621 case 0xb0:
4079 case 0xb1: 3622 case 0xb1:
4080 case 0xb2: 3623 case 0xb2:
4081 case 0xb3: 3624 case 0xb3:
4082 case 0xb4: 3625 case 0xb4:
4083 case 0xb5: 3626 case 0xb5:
4084 case 0xb6: 3627 case 0xb6:
4085 case 0xb7: 3628 case 0xb7:
4086 /* Put PC into Link. */ 3629
3630 /* Put PC into Link. */
4087#ifdef MODE32 3631#ifdef MODE32
4088 state->Reg[14] = pc + 4; 3632 state->Reg[14] = pc + 4;
4089#else 3633#else
4090 state->Reg[14] = 3634 state->Reg[14] = (pc + 4) | ECC | ER15INT | EMODE;
4091 (pc + 4) | ECC | ER15INT | EMODE;
4092#endif 3635#endif
4093 state->Reg[15] = pc + 8 + POSBRANCH; 3636 state->Reg[15] = pc + 8 + POSBRANCH;
4094 FLUSHPIPE; 3637 FLUSHPIPE;
4095 break; 3638
3639#ifdef callstacker
3640 memset(a, 0, 256);
3641 aufloeser(a, state->Reg[15]);
3642 printf("call %08X %08X %s(%08X %08X %08X %08X %08X %08X %08X)\n", state->Reg[14], state->Reg[15], a, state->Reg[0], state->Reg[1], state->Reg[2], state->Reg[3], mem_Read32(state->Reg[13]), mem_Read32(state->Reg[13] - 4),mem_Read32(state->Reg[13] - 8));
3643#endif
3644
3645
3646 break;
4096 3647
4097 3648
4098 /* Branch and Link backward. */ 3649 /* Branch and Link backward. */
4099 case 0xb8: 3650 case 0xb8:
4100 case 0xb9: 3651 case 0xb9:
4101 case 0xba: 3652 case 0xba:
4102 case 0xbb: 3653 case 0xbb:
4103 case 0xbc: 3654 case 0xbc:
4104 case 0xbd: 3655 case 0xbd:
4105 case 0xbe: 3656 case 0xbe:
4106 case 0xbf: 3657 case 0xbf:
4107 /* Put PC into Link. */ 3658 /* Put PC into Link. */
4108#ifdef MODE32 3659#ifdef MODE32
4109 state->Reg[14] = pc + 4; 3660 state->Reg[14] = pc + 4;
4110#else 3661#else
4111 state->Reg[14] = 3662 state->Reg[14] = (pc + 4) | ECC | ER15INT | EMODE;
4112 (pc + 4) | ECC | ER15INT | EMODE;
4113#endif 3663#endif
4114 state->Reg[15] = pc + 8 + NEGBRANCH; 3664 state->Reg[15] = pc + 8 + NEGBRANCH;
4115 FLUSHPIPE; 3665 FLUSHPIPE;
4116 break; 3666
3667
3668#ifdef callstacker
3669 memset(a, 0, 256);
3670 aufloeser(a, state->Reg[15]);
3671 printf("call %08X %08X %s(%08X %08X %08X %08X %08X %08X %08X)\n", state->Reg[14], state->Reg[15], a, state->Reg[0], state->Reg[1], state->Reg[2], state->Reg[3], mem_Read32(state->Reg[13]), mem_Read32(state->Reg[13] - 4),mem_Read32(state->Reg[13] - 8));
3672#endif
3673
3674
3675
3676 break;
4117 3677
4118 3678
4119 /* Co-Processor Data Transfers. */ 3679 /* Co-Processor Data Transfers. */
4120 case 0xc4: 3680 case 0xc4:
4121 if (state->is_v5) { 3681 if (state->is_v5) {
4122 /* Reading from R15 is UNPREDICTABLE. */ 3682 /* Reading from R15 is UNPREDICTABLE. */
4123 if (BITS (12, 15) == 15 3683 if (BITS (12, 15) == 15 || BITS (16, 19) == 15)
4124 || BITS (16, 19) == 15) 3684 ARMul_UndefInstr (state, instr);
4125 ARMul_UndefInstr (state, 3685 /* Is access to coprocessor 0 allowed ? */
4126 instr); 3686 else if (!CP_ACCESS_ALLOWED(state, CPNum))
4127 /* Is access to coprocessor 0 allowed ? */ 3687 ARMul_UndefInstr (state, instr);
4128 else if (!CP_ACCESS_ALLOWED
4129 (state, CPNum))
4130 ARMul_UndefInstr (state,
4131 instr);
4132 /* Special treatment for XScale coprocessors. */
4133 else if (state->is_XScale) {
4134 /* Only opcode 0 is supported. */
4135 if (BITS (4, 7) != 0x00)
4136 ARMul_UndefInstr
4137 (state,
4138 instr);
4139 /* Only coporcessor 0 is supported. */
4140 else if (CPNum != 0x00)
4141 ARMul_UndefInstr
4142 (state,
4143 instr);
4144 /* Only accumulator 0 is supported. */
4145 else if (BITS (0, 3) != 0x00)
4146 ARMul_UndefInstr
4147 (state,
4148 instr);
4149 else { 3688 else {
4150 /* XScale MAR insn. Move two registers into accumulator. */ 3689 /* MCRR, ARMv5TE and up */
4151 state->Accumulator = 3690 ARMul_MCRR (state, instr, DEST, state->Reg[LHSReg]);
4152 state-> 3691 break;
4153 Reg[BITS
4154 (12, 15)];
4155 state->Accumulator +=
4156 (ARMdword)
4157 state->
4158 Reg[BITS
4159 (16,
4160 19)] <<
4161 32;
4162 } 3692 }
4163 } 3693 }
4164 else
4165 {
4166 /* MCRR, ARMv5TE and up */
4167 ARMul_MCRR (state, instr, DEST, state->Reg[LHSReg]);
4168 break;
4169 }
4170 }
4171 /* Drop through. */ 3694 /* Drop through. */
4172 3695
4173 case 0xc0: /* Store , No WriteBack , Post Dec. */ 3696 case 0xc0: /* Store , No WriteBack , Post Dec. */
4174 ARMul_STC (state, instr, LHS); 3697 ARMul_STC (state, instr, LHS);
4175 break; 3698 break;
4176 3699
4177 case 0xc5: 3700 case 0xc5:
4178 if (state->is_v5) { 3701 if (state->is_v5) {
4179 /* Writes to R15 are UNPREDICATABLE. */ 3702 /* Writes to R15 are UNPREDICATABLE. */
4180 if (DESTReg == 15 || LHSReg == 15) 3703 if (DESTReg == 15 || LHSReg == 15)
4181 ARMul_UndefInstr (state, 3704 ARMul_UndefInstr (state, instr);
4182 instr); 3705 /* Is access to the coprocessor allowed ? */
4183 /* Is access to the coprocessor allowed ? */ 3706 else if (!CP_ACCESS_ALLOWED(state, CPNum))
4184 else if (!CP_ACCESS_ALLOWED 3707 ARMul_UndefInstr (state, instr);
4185 (state, CPNum))
4186 ARMul_UndefInstr (state,
4187 instr);
4188 /* Special handling for XScale coprcoessors. */
4189 else if (state->is_XScale) {
4190 /* Only opcode 0 is supported. */
4191 if (BITS (4, 7) != 0x00)
4192 ARMul_UndefInstr
4193 (state,
4194 instr);
4195 /* Only coprocessor 0 is supported. */
4196 else if (CPNum != 0x00)
4197 ARMul_UndefInstr
4198 (state,
4199 instr);
4200 /* Only accumulator 0 is supported. */
4201 else if (BITS (0, 3) != 0x00)
4202 ARMul_UndefInstr
4203 (state,
4204 instr);
4205 else { 3708 else {
4206 /* XScale MRA insn. Move accumulator into two registers. */ 3709 /* MRRC, ARMv5TE and up */
4207 ARMword t1 = 3710 ARMul_MRRC (state, instr, &DEST, &(state->Reg[LHSReg]));
4208 (state->
4209 Accumulator
4210 >> 32) & 255;
4211
4212 if (t1 & 128)
4213 t1 -= 256;
4214
4215 state->Reg[BITS
4216 (12, 15)] =
4217 state->
4218 Accumulator;
4219 state->Reg[BITS
4220 (16, 19)] =
4221 t1;
4222 break; 3711 break;
4223 } 3712 }
4224 } 3713 }
4225 else
4226 {
4227 /* MRRC, ARMv5TE and up */
4228 ARMul_MRRC (state, instr, &DEST, &(state->Reg[LHSReg]));
4229 break;
4230 }
4231 }
4232 /* Drop through. */ 3714 /* Drop through. */
4233 3715
4234 case 0xc1: /* Load , No WriteBack , Post Dec. */ 3716 case 0xc1: /* Load , No WriteBack , Post Dec. */
4235 ARMul_LDC (state, instr, LHS); 3717 ARMul_LDC (state, instr, LHS);
4236 break; 3718 break;
4237 3719
4238 case 0xc2: 3720 case 0xc2:
4239 case 0xc6: /* Store , WriteBack , Post Dec. */ 3721 case 0xc6: /* Store , WriteBack , Post Dec. */
4240 lhs = LHS; 3722 lhs = LHS;
4241 state->Base = lhs - LSCOff; 3723 state->Base = lhs - LSCOff;
4242 ARMul_STC (state, instr, lhs); 3724 ARMul_STC (state, instr, lhs);
4243 break; 3725 break;
4244 3726
4245 case 0xc3: 3727 case 0xc3:
4246 case 0xc7: /* Load , WriteBack , Post Dec. */ 3728 case 0xc7: /* Load , WriteBack , Post Dec. */
4247 lhs = LHS; 3729 lhs = LHS;
4248 state->Base = lhs - LSCOff; 3730 state->Base = lhs - LSCOff;
4249 ARMul_LDC (state, instr, lhs); 3731 ARMul_LDC (state, instr, lhs);
4250 break; 3732 break;
4251 3733
4252 case 0xc8: 3734 case 0xc8:
4253 case 0xcc: /* Store , No WriteBack , Post Inc. */ 3735 case 0xcc: /* Store , No WriteBack , Post Inc. */
4254 ARMul_STC (state, instr, LHS); 3736 ARMul_STC (state, instr, LHS);
4255 break; 3737 break;
4256 3738
4257 case 0xc9: 3739 case 0xc9:
4258 case 0xcd: /* Load , No WriteBack , Post Inc. */ 3740 case 0xcd: /* Load , No WriteBack , Post Inc. */
4259 ARMul_LDC (state, instr, LHS); 3741 ARMul_LDC (state, instr, LHS);
4260 break; 3742 break;
4261 3743
4262 case 0xca: 3744 case 0xca:
4263 case 0xce: /* Store , WriteBack , Post Inc. */ 3745 case 0xce: /* Store , WriteBack , Post Inc. */
4264 lhs = LHS; 3746 lhs = LHS;
4265 state->Base = lhs + LSCOff; 3747 state->Base = lhs + LSCOff;
4266 ARMul_STC (state, instr, LHS); 3748 ARMul_STC (state, instr, LHS);
4267 break; 3749 break;
4268 3750
4269 case 0xcb: 3751 case 0xcb:
4270 case 0xcf: /* Load , WriteBack , Post Inc. */ 3752 case 0xcf: /* Load , WriteBack , Post Inc. */
4271 lhs = LHS; 3753 lhs = LHS;
4272 state->Base = lhs + LSCOff; 3754 state->Base = lhs + LSCOff;
4273 ARMul_LDC (state, instr, LHS); 3755 ARMul_LDC (state, instr, LHS);
4274 break; 3756 break;
4275 3757
4276 case 0xd0: 3758 case 0xd0:
4277 case 0xd4: /* Store , No WriteBack , Pre Dec. */ 3759 case 0xd4: /* Store , No WriteBack , Pre Dec. */
4278 ARMul_STC (state, instr, LHS - LSCOff); 3760 ARMul_STC (state, instr, LHS - LSCOff);
4279 break; 3761 break;
4280 3762
4281 case 0xd1: 3763 case 0xd1:
4282 case 0xd5: /* Load , No WriteBack , Pre Dec. */ 3764 case 0xd5: /* Load , No WriteBack , Pre Dec. */
4283 ARMul_LDC (state, instr, LHS - LSCOff); 3765 ARMul_LDC (state, instr, LHS - LSCOff);
4284 break; 3766 break;
4285 3767
4286 case 0xd2: 3768 case 0xd2:
4287 case 0xd6: /* Store , WriteBack , Pre Dec. */ 3769 case 0xd6: /* Store , WriteBack , Pre Dec. */
4288 lhs = LHS - LSCOff; 3770 lhs = LHS - LSCOff;
4289 state->Base = lhs; 3771 state->Base = lhs;
4290 ARMul_STC (state, instr, lhs); 3772 ARMul_STC (state, instr, lhs);
4291 break; 3773 break;
4292 3774
4293 case 0xd3: 3775 case 0xd3:
4294 case 0xd7: /* Load , WriteBack , Pre Dec. */ 3776 case 0xd7: /* Load , WriteBack , Pre Dec. */
4295 lhs = LHS - LSCOff; 3777 lhs = LHS - LSCOff;
4296 state->Base = lhs; 3778 state->Base = lhs;
4297 ARMul_LDC (state, instr, lhs); 3779 ARMul_LDC (state, instr, lhs);
4298 break; 3780 break;
4299 3781
4300 case 0xd8: 3782 case 0xd8:
4301 case 0xdc: /* Store , No WriteBack , Pre Inc. */ 3783 case 0xdc: /* Store , No WriteBack , Pre Inc. */
4302 ARMul_STC (state, instr, LHS + LSCOff); 3784 ARMul_STC (state, instr, LHS + LSCOff);
4303 break; 3785 break;
4304 3786
4305 case 0xd9: 3787 case 0xd9:
4306 case 0xdd: /* Load , No WriteBack , Pre Inc. */ 3788 case 0xdd: /* Load , No WriteBack , Pre Inc. */
4307 ARMul_LDC (state, instr, LHS + LSCOff); 3789 ARMul_LDC (state, instr, LHS + LSCOff);
4308 break; 3790 break;
4309 3791
4310 case 0xda: 3792 case 0xda:
4311 case 0xde: /* Store , WriteBack , Pre Inc. */ 3793 case 0xde: /* Store , WriteBack , Pre Inc. */
4312 lhs = LHS + LSCOff; 3794 lhs = LHS + LSCOff;
4313 state->Base = lhs; 3795 state->Base = lhs;
4314 ARMul_STC (state, instr, lhs); 3796 ARMul_STC (state, instr, lhs);
4315 break; 3797 break;
4316 3798
4317 case 0xdb: 3799 case 0xdb:
4318 case 0xdf: /* Load , WriteBack , Pre Inc. */ 3800 case 0xdf: /* Load , WriteBack , Pre Inc. */
4319 lhs = LHS + LSCOff; 3801 lhs = LHS + LSCOff;
4320 state->Base = lhs; 3802 state->Base = lhs;
4321 ARMul_LDC (state, instr, lhs); 3803 ARMul_LDC (state, instr, lhs);
4322 break; 3804 break;
4323 3805
4324 3806
4325 /* Co-Processor Register Transfers (MCR) and Data Ops. */ 3807 /* Co-Processor Register Transfers (MCR) and Data Ops. */
4326 3808
4327 case 0xe2: 3809 case 0xe2:
4328 if (!CP_ACCESS_ALLOWED (state, CPNum)) { 3810 /*if (!CP_ACCESS_ALLOWED (state, CPNum)) {
4329 ARMul_UndefInstr (state, instr); 3811 ARMul_UndefInstr (state, instr);
4330 break; 3812 break;
4331 } 3813 }*/
4332 if (state->is_XScale) 3814
4333 switch (BITS (18, 19)) { 3815 case 0xe0:
4334 case 0x0: 3816 case 0xe4:
4335 if (BITS (4, 11) == 1 3817 case 0xe6:
4336 && BITS (16, 17) == 0) { 3818 case 0xe8:
4337 /* XScale MIA instruction. Signed multiplication of 3819 case 0xea:
4338 two 32 bit values and addition to 40 bit accumulator. */ 3820 case 0xec:
4339 long long Rm = 3821 case 0xee:
4340 state-> 3822 if (BIT (4)) {
4341 Reg 3823 /* MCR. */
4342 [MULLHSReg]; 3824 if (DESTReg == 15) {
4343 long long Rs = 3825 UNDEF_MCRPC;
4344 state->
4345 Reg
4346 [MULACCReg];
4347
4348 if (Rm & (1 << 31))
4349 Rm -= 1ULL <<
4350 32;
4351 if (Rs & (1 << 31))
4352 Rs -= 1ULL <<
4353 32;
4354 state->Accumulator +=
4355 Rm * Rs;
4356 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext;
4357 }
4358 break;
4359
4360 case 0x2:
4361 if (BITS (4, 11) == 1
4362 && BITS (16, 17) == 0) {
4363 /* XScale MIAPH instruction. */
4364 ARMword t1 =
4365 state->
4366 Reg[MULLHSReg]
4367 >> 16;
4368 ARMword t2 =
4369 state->
4370 Reg[MULACCReg]
4371 >> 16;
4372 ARMword t3 =
4373 state->
4374 Reg[MULLHSReg]
4375 & 0xffff;
4376 ARMword t4 =
4377 state->
4378 Reg[MULACCReg]
4379 & 0xffff;
4380 long long t5;
4381
4382 if (t1 & (1 << 15))
4383 t1 -= 1 << 16;
4384 if (t2 & (1 << 15))
4385 t2 -= 1 << 16;
4386 if (t3 & (1 << 15))
4387 t3 -= 1 << 16;
4388 if (t4 & (1 << 15))
4389 t4 -= 1 << 16;
4390 t1 *= t2;
4391 t5 = t1;
4392 if (t5 & (1 << 31))
4393 t5 -= 1ULL <<
4394 32;
4395 state->Accumulator +=
4396 t5;
4397 t3 *= t4;
4398 t5 = t3;
4399 if (t5 & (1 << 31))
4400 t5 -= 1ULL <<
4401 32;
4402 state->Accumulator +=
4403 t5;
4404 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext;
4405 }
4406 break;
4407
4408 case 0x3:
4409 if (BITS (4, 11) == 1) {
4410 /* XScale MIAxy instruction. */
4411 ARMword t1;
4412 ARMword t2;
4413 long long t5;
4414
4415 if (BIT (17))
4416 t1 = state->
4417 Reg
4418 [MULLHSReg]
4419 >> 16;
4420 else
4421 t1 = state->
4422 Reg
4423 [MULLHSReg]
4424 &
4425 0xffff;
4426
4427 if (BIT (16))
4428 t2 = state->
4429 Reg
4430 [MULACCReg]
4431 >> 16;
4432 else
4433 t2 = state->
4434 Reg
4435 [MULACCReg]
4436 &
4437 0xffff;
4438
4439 if (t1 & (1 << 15))
4440 t1 -= 1 << 16;
4441 if (t2 & (1 << 15))
4442 t2 -= 1 << 16;
4443 t1 *= t2;
4444 t5 = t1;
4445 if (t5 & (1 << 31))
4446 t5 -= 1ULL <<
4447 32;
4448 state->Accumulator +=
4449 t5;
4450 _assert_msg_(ARM11, false, "disabled skyeye code 'goto donext'"); //goto donext;
4451 }
4452 break;
4453
4454 default:
4455 break;
4456 }
4457 /* Drop through. */
4458
4459 case 0xe0:
4460 case 0xe4:
4461 case 0xe6:
4462 case 0xe8:
4463 case 0xea:
4464 case 0xec:
4465 case 0xee:
4466 if (BIT (4)) {
4467 /* MCR. */
4468 if (DESTReg == 15) {
4469 UNDEF_MCRPC;
4470#ifdef MODE32 3826#ifdef MODE32
4471 ARMul_MCR (state, instr, 3827 ARMul_MCR (state, instr, state->Reg[15] + isize);
4472 state->Reg[15] +
4473 isize);
4474#else 3828#else
4475 ARMul_MCR (state, instr, 3829 ARMul_MCR (state, instr, ECC | ER15INT | EMODE | ((state->Reg[15] + isize) & R15PCBITS));
4476 ECC | ER15INT | 3830#endif
4477 EMODE | 3831 } else
4478 ((state->Reg[15] + 3832 ARMul_MCR (state, instr, DEST);
4479 isize) & 3833 } else
4480 R15PCBITS)); 3834 /* CDP Part 1. */
4481#endif 3835 ARMul_CDP (state, instr);
4482 } else if (instr != 0xDEADC0DE) // thumbemu uses 0xDEADCODE for debugging to catch non updates 3836 break;
4483 ARMul_MCR (state, instr,
4484 DEST);
4485 }
4486 else
4487 /* CDP Part 1. */
4488 ARMul_CDP (state, instr);
4489 break;
4490 3837
4491 3838
4492 /* Co-Processor Register Transfers (MRC) and Data Ops. */ 3839 /* Co-Processor Register Transfers (MRC) and Data Ops. */
4493 case 0xe1: 3840 case 0xe1:
4494 case 0xe3: 3841 case 0xe3:
4495 case 0xe5: 3842 case 0xe5:
4496 case 0xe7: 3843 case 0xe7:
4497 case 0xe9: 3844 case 0xe9:
4498 case 0xeb: 3845 case 0xeb:
4499 case 0xed: 3846 case 0xed:
4500 case 0xef: 3847 case 0xef:
4501 if (BIT (4)) { 3848 if (BIT (4)) {
4502 /* MRC */ 3849 /* MRC */
4503 temp = ARMul_MRC (state, instr); 3850 temp = ARMul_MRC (state, instr);
4504 if (DESTReg == 15) { 3851 if (DESTReg == 15) {
4505 ASSIGNN ((temp & NBIT) != 0); 3852 ASSIGNN ((temp & NBIT) != 0);
4506 ASSIGNZ ((temp & ZBIT) != 0); 3853 ASSIGNZ ((temp & ZBIT) != 0);
4507 ASSIGNC ((temp & CBIT) != 0); 3854 ASSIGNC ((temp & CBIT) != 0);
4508 ASSIGNV ((temp & VBIT) != 0); 3855 ASSIGNV ((temp & VBIT) != 0);
4509 } 3856 } else
4510 else 3857 DEST = temp;
4511 DEST = temp; 3858 } else
4512 } 3859 /* CDP Part 2. */
4513 else 3860 ARMul_CDP (state, instr);
4514 /* CDP Part 2. */ 3861 break;
4515 ARMul_CDP (state, instr);
4516 break;
4517 3862
4518 3863
4519 /* SWI instruction. */ 3864 /* SWI instruction. */
4520 case 0xf0: 3865 case 0xf0:
4521 case 0xf1: 3866 case 0xf1:
4522 case 0xf2: 3867 case 0xf2:
4523 case 0xf3: 3868 case 0xf3:
4524 case 0xf4: 3869 case 0xf4:
4525 case 0xf5: 3870 case 0xf5:
4526 case 0xf6: 3871 case 0xf6:
4527 case 0xf7: 3872 case 0xf7:
4528 case 0xf8: 3873 case 0xf8:
4529 case 0xf9: 3874 case 0xf9:
4530 case 0xfa: 3875 case 0xfa:
4531 case 0xfb: 3876 case 0xfb:
4532 case 0xfc: 3877 case 0xfc:
4533 case 0xfd: 3878 case 0xfd:
4534 case 0xfe: 3879 case 0xfe:
4535 case 0xff: 3880 case 0xff:
4536 HLE::CallSVC(instr); 3881 //svc_Execute(state, BITS(0, 23));
4537 break; 3882 HLE::CallSVC(instr);
3883
3884 break;
3885 }
4538 } 3886 }
4539 } 3887
4540
4541#ifdef MODET 3888#ifdef MODET
4542 donext: 3889donext:
4543#endif 3890#endif
4544 state->pc = pc; 3891 state->pc = pc;
4545#if 0 3892#if 0
4546 /* shenoubang */ 3893 /* shenoubang */
4547 instr_sum++; 3894 instr_sum++;
4548 int i, j; 3895 int i, j;
4549 i = j = 0; 3896 i = j = 0;
4550 if (instr_sum >= 7388648) { 3897 if (instr_sum >= 7388648) {
4551 //if (pc == 0xc0008ab4) { 3898 //if (pc == 0xc0008ab4) {
4552 // printf("instr_sum: %d\n", instr_sum); 3899 // printf("instr_sum: %d\n", instr_sum);
4553 // start_kernel : 0xc000895c 3900 // start_kernel : 0xc000895c
4554 printf("--------------------------------------------------\n"); 3901 printf("--------------------------------------------------\n");
4555 for (i = 0; i < 16; i++) { 3902 for (i = 0; i < 16; i++) {
@@ -4571,295 +3918,289 @@ ARMul_Emulate26 (ARMul_State * state)
4571#endif 3918#endif
4572 3919
4573#if 0 3920#if 0
4574 fprintf(state->state_log, "PC:0x%x\n", pc); 3921 fprintf(state->state_log, "PC:0x%x\n", pc);
4575 for (reg_index = 0; reg_index < 16; reg_index ++) { 3922 for (reg_index = 0; reg_index < 16; reg_index ++) {
4576 if (state->Reg[reg_index] != mirror_register_file[reg_index]) { 3923 if (state->Reg[reg_index] != mirror_register_file[reg_index]) {
4577 fprintf(state->state_log, "R%d:0x%x\n", reg_index, state->Reg[reg_index]); 3924 fprintf(state->state_log, "R%d:0x%x\n", reg_index, state->Reg[reg_index]);
4578 mirror_register_file[reg_index] = state->Reg[reg_index]; 3925 mirror_register_file[reg_index] = state->Reg[reg_index];
4579 } 3926 }
4580 } 3927 }
4581 if (state->Cpsr != mirror_register_file[CPSR_REG]) { 3928 if (state->Cpsr != mirror_register_file[CPSR_REG]) {
4582 fprintf(state->state_log, "Cpsr:0x%x\n", state->Cpsr); 3929 fprintf(state->state_log, "Cpsr:0x%x\n", state->Cpsr);
4583 mirror_register_file[CPSR_REG] = state->Cpsr; 3930 mirror_register_file[CPSR_REG] = state->Cpsr;
4584 } 3931 }
4585 if (state->RegBank[SVCBANK][13] != mirror_register_file[R13_SVC]) { 3932 if (state->RegBank[SVCBANK][13] != mirror_register_file[R13_SVC]) {
4586 fprintf(state->state_log, "R13_SVC:0x%x\n", state->RegBank[SVCBANK][13]); 3933 fprintf(state->state_log, "R13_SVC:0x%x\n", state->RegBank[SVCBANK][13]);
4587 mirror_register_file[R13_SVC] = state->RegBank[SVCBANK][13]; 3934 mirror_register_file[R13_SVC] = state->RegBank[SVCBANK][13];
4588 } 3935 }
4589 if (state->RegBank[SVCBANK][14] != mirror_register_file[R14_SVC]) { 3936 if (state->RegBank[SVCBANK][14] != mirror_register_file[R14_SVC]) {
4590 fprintf(state->state_log, "R14_SVC:0x%x\n", state->RegBank[SVCBANK][14]); 3937 fprintf(state->state_log, "R14_SVC:0x%x\n", state->RegBank[SVCBANK][14]);
4591 mirror_register_file[R14_SVC] = state->RegBank[SVCBANK][14]; 3938 mirror_register_file[R14_SVC] = state->RegBank[SVCBANK][14];
4592 } 3939 }
4593 if (state->RegBank[ABORTBANK][13] != mirror_register_file[R13_ABORT]) { 3940 if (state->RegBank[ABORTBANK][13] != mirror_register_file[R13_ABORT]) {
4594 fprintf(state->state_log, "R13_ABORT:0x%x\n", state->RegBank[ABORTBANK][13]); 3941 fprintf(state->state_log, "R13_ABORT:0x%x\n", state->RegBank[ABORTBANK][13]);
4595 mirror_register_file[R13_ABORT] = state->RegBank[ABORTBANK][13]; 3942 mirror_register_file[R13_ABORT] = state->RegBank[ABORTBANK][13];
4596 } 3943 }
4597 if (state->RegBank[ABORTBANK][14] != mirror_register_file[R14_ABORT]) { 3944 if (state->RegBank[ABORTBANK][14] != mirror_register_file[R14_ABORT]) {
4598 fprintf(state->state_log, "R14_ABORT:0x%x\n", state->RegBank[ABORTBANK][14]); 3945 fprintf(state->state_log, "R14_ABORT:0x%x\n", state->RegBank[ABORTBANK][14]);
4599 mirror_register_file[R14_ABORT] = state->RegBank[ABORTBANK][14]; 3946 mirror_register_file[R14_ABORT] = state->RegBank[ABORTBANK][14];
4600 } 3947 }
4601 if (state->RegBank[UNDEFBANK][13] != mirror_register_file[R13_UNDEF]) { 3948 if (state->RegBank[UNDEFBANK][13] != mirror_register_file[R13_UNDEF]) {
4602 fprintf(state->state_log, "R13_UNDEF:0x%x\n", state->RegBank[UNDEFBANK][13]); 3949 fprintf(state->state_log, "R13_UNDEF:0x%x\n", state->RegBank[UNDEFBANK][13]);
4603 mirror_register_file[R13_UNDEF] = state->RegBank[UNDEFBANK][13]; 3950 mirror_register_file[R13_UNDEF] = state->RegBank[UNDEFBANK][13];
4604 } 3951 }
4605 if (state->RegBank[UNDEFBANK][14] != mirror_register_file[R14_UNDEF]) { 3952 if (state->RegBank[UNDEFBANK][14] != mirror_register_file[R14_UNDEF]) {
4606 fprintf(state->state_log, "R14_UNDEF:0x%x\n", state->RegBank[UNDEFBANK][14]); 3953 fprintf(state->state_log, "R14_UNDEF:0x%x\n", state->RegBank[UNDEFBANK][14]);
4607 mirror_register_file[R14_UNDEF] = state->RegBank[UNDEFBANK][14]; 3954 mirror_register_file[R14_UNDEF] = state->RegBank[UNDEFBANK][14];
4608 } 3955 }
4609 if (state->RegBank[IRQBANK][13] != mirror_register_file[R13_IRQ]) { 3956 if (state->RegBank[IRQBANK][13] != mirror_register_file[R13_IRQ]) {
4610 fprintf(state->state_log, "R13_IRQ:0x%x\n", state->RegBank[IRQBANK][13]); 3957 fprintf(state->state_log, "R13_IRQ:0x%x\n", state->RegBank[IRQBANK][13]);
4611 mirror_register_file[R13_IRQ] = state->RegBank[IRQBANK][13]; 3958 mirror_register_file[R13_IRQ] = state->RegBank[IRQBANK][13];
4612 } 3959 }
4613 if (state->RegBank[IRQBANK][14] != mirror_register_file[R14_IRQ]) { 3960 if (state->RegBank[IRQBANK][14] != mirror_register_file[R14_IRQ]) {
4614 fprintf(state->state_log, "R14_IRQ:0x%x\n", state->RegBank[IRQBANK][14]); 3961 fprintf(state->state_log, "R14_IRQ:0x%x\n", state->RegBank[IRQBANK][14]);
4615 mirror_register_file[R14_IRQ] = state->RegBank[IRQBANK][14]; 3962 mirror_register_file[R14_IRQ] = state->RegBank[IRQBANK][14];
4616 } 3963 }
4617 if (state->RegBank[FIQBANK][8] != mirror_register_file[R8_FIRQ]) { 3964 if (state->RegBank[FIQBANK][8] != mirror_register_file[R8_FIRQ]) {
4618 fprintf(state->state_log, "R8_FIRQ:0x%x\n", state->RegBank[FIQBANK][8]); 3965 fprintf(state->state_log, "R8_FIRQ:0x%x\n", state->RegBank[FIQBANK][8]);
4619 mirror_register_file[R8_FIRQ] = state->RegBank[FIQBANK][8]; 3966 mirror_register_file[R8_FIRQ] = state->RegBank[FIQBANK][8];
4620 } 3967 }
4621 if (state->RegBank[FIQBANK][9] != mirror_register_file[R9_FIRQ]) { 3968 if (state->RegBank[FIQBANK][9] != mirror_register_file[R9_FIRQ]) {
4622 fprintf(state->state_log, "R9_FIRQ:0x%x\n", state->RegBank[FIQBANK][9]); 3969 fprintf(state->state_log, "R9_FIRQ:0x%x\n", state->RegBank[FIQBANK][9]);
4623 mirror_register_file[R9_FIRQ] = state->RegBank[FIQBANK][9]; 3970 mirror_register_file[R9_FIRQ] = state->RegBank[FIQBANK][9];
4624 } 3971 }
4625 if (state->RegBank[FIQBANK][10] != mirror_register_file[R10_FIRQ]) { 3972 if (state->RegBank[FIQBANK][10] != mirror_register_file[R10_FIRQ]) {
4626 fprintf(state->state_log, "R10_FIRQ:0x%x\n", state->RegBank[FIQBANK][10]); 3973 fprintf(state->state_log, "R10_FIRQ:0x%x\n", state->RegBank[FIQBANK][10]);
4627 mirror_register_file[R10_FIRQ] = state->RegBank[FIQBANK][10]; 3974 mirror_register_file[R10_FIRQ] = state->RegBank[FIQBANK][10];
4628 } 3975 }
4629 if (state->RegBank[FIQBANK][11] != mirror_register_file[R11_FIRQ]) { 3976 if (state->RegBank[FIQBANK][11] != mirror_register_file[R11_FIRQ]) {
4630 fprintf(state->state_log, "R11_FIRQ:0x%x\n", state->RegBank[FIQBANK][11]); 3977 fprintf(state->state_log, "R11_FIRQ:0x%x\n", state->RegBank[FIQBANK][11]);
4631 mirror_register_file[R11_FIRQ] = state->RegBank[FIQBANK][11]; 3978 mirror_register_file[R11_FIRQ] = state->RegBank[FIQBANK][11];
4632 } 3979 }
4633 if (state->RegBank[FIQBANK][12] != mirror_register_file[R12_FIRQ]) { 3980 if (state->RegBank[FIQBANK][12] != mirror_register_file[R12_FIRQ]) {
4634 fprintf(state->state_log, "R12_FIRQ:0x%x\n", state->RegBank[FIQBANK][12]); 3981 fprintf(state->state_log, "R12_FIRQ:0x%x\n", state->RegBank[FIQBANK][12]);
4635 mirror_register_file[R12_FIRQ] = state->RegBank[FIQBANK][12]; 3982 mirror_register_file[R12_FIRQ] = state->RegBank[FIQBANK][12];
4636 } 3983 }
4637 if (state->RegBank[FIQBANK][13] != mirror_register_file[R13_FIRQ]) { 3984 if (state->RegBank[FIQBANK][13] != mirror_register_file[R13_FIRQ]) {
4638 fprintf(state->state_log, "R13_FIRQ:0x%x\n", state->RegBank[FIQBANK][13]); 3985 fprintf(state->state_log, "R13_FIRQ:0x%x\n", state->RegBank[FIQBANK][13]);
4639 mirror_register_file[R13_FIRQ] = state->RegBank[FIQBANK][13]; 3986 mirror_register_file[R13_FIRQ] = state->RegBank[FIQBANK][13];
4640 } 3987 }
4641 if (state->RegBank[FIQBANK][14] != mirror_register_file[R14_FIRQ]) { 3988 if (state->RegBank[FIQBANK][14] != mirror_register_file[R14_FIRQ]) {
4642 fprintf(state->state_log, "R14_FIRQ:0x%x\n", state->RegBank[FIQBANK][14]); 3989 fprintf(state->state_log, "R14_FIRQ:0x%x\n", state->RegBank[FIQBANK][14]);
4643 mirror_register_file[R14_FIRQ] = state->RegBank[FIQBANK][14]; 3990 mirror_register_file[R14_FIRQ] = state->RegBank[FIQBANK][14];
4644 } 3991 }
4645 if (state->Spsr[SVCBANK] != mirror_register_file[SPSR_SVC]) { 3992 if (state->Spsr[SVCBANK] != mirror_register_file[SPSR_SVC]) {
4646 fprintf(state->state_log, "SPSR_SVC:0x%x\n", state->Spsr[SVCBANK]); 3993 fprintf(state->state_log, "SPSR_SVC:0x%x\n", state->Spsr[SVCBANK]);
4647 mirror_register_file[SPSR_SVC] = state->RegBank[SVCBANK]; 3994 mirror_register_file[SPSR_SVC] = state->RegBank[SVCBANK];
4648 } 3995 }
4649 if (state->Spsr[ABORTBANK] != mirror_register_file[SPSR_ABORT]) { 3996 if (state->Spsr[ABORTBANK] != mirror_register_file[SPSR_ABORT]) {
4650 fprintf(state->state_log, "SPSR_ABORT:0x%x\n", state->Spsr[ABORTBANK]); 3997 fprintf(state->state_log, "SPSR_ABORT:0x%x\n", state->Spsr[ABORTBANK]);
4651 mirror_register_file[SPSR_ABORT] = state->RegBank[ABORTBANK]; 3998 mirror_register_file[SPSR_ABORT] = state->RegBank[ABORTBANK];
4652 } 3999 }
4653 if (state->Spsr[UNDEFBANK] != mirror_register_file[SPSR_UNDEF]) { 4000 if (state->Spsr[UNDEFBANK] != mirror_register_file[SPSR_UNDEF]) {
4654 fprintf(state->state_log, "SPSR_UNDEF:0x%x\n", state->Spsr[UNDEFBANK]); 4001 fprintf(state->state_log, "SPSR_UNDEF:0x%x\n", state->Spsr[UNDEFBANK]);
4655 mirror_register_file[SPSR_UNDEF] = state->RegBank[UNDEFBANK]; 4002 mirror_register_file[SPSR_UNDEF] = state->RegBank[UNDEFBANK];
4656 } 4003 }
4657 if (state->Spsr[IRQBANK] != mirror_register_file[SPSR_IRQ]) { 4004 if (state->Spsr[IRQBANK] != mirror_register_file[SPSR_IRQ]) {
4658 fprintf(state->state_log, "SPSR_IRQ:0x%x\n", state->Spsr[IRQBANK]); 4005 fprintf(state->state_log, "SPSR_IRQ:0x%x\n", state->Spsr[IRQBANK]);
4659 mirror_register_file[SPSR_IRQ] = state->RegBank[IRQBANK]; 4006 mirror_register_file[SPSR_IRQ] = state->RegBank[IRQBANK];
4660 } 4007 }
4661 if (state->Spsr[FIQBANK] != mirror_register_file[SPSR_FIRQ]) { 4008 if (state->Spsr[FIQBANK] != mirror_register_file[SPSR_FIRQ]) {
4662 fprintf(state->state_log, "SPSR_FIRQ:0x%x\n", state->Spsr[FIQBANK]); 4009 fprintf(state->state_log, "SPSR_FIRQ:0x%x\n", state->Spsr[FIQBANK]);
4663 mirror_register_file[SPSR_FIRQ] = state->RegBank[FIQBANK]; 4010 mirror_register_file[SPSR_FIRQ] = state->RegBank[FIQBANK];
4664 } 4011 }
4665 4012
4666#endif 4013#endif
4667 4014
4668#ifdef NEED_UI_LOOP_HOOK 4015#ifdef NEED_UI_LOOP_HOOK
4669 if (ui_loop_hook != NULL && ui_loop_hook_counter-- < 0) { 4016 if (ui_loop_hook != NULL && ui_loop_hook_counter-- < 0) {
4670 ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL; 4017 ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL;
4671 ui_loop_hook (0); 4018 ui_loop_hook (0);
4672 } 4019 }
4673#endif /* NEED_UI_LOOP_HOOK */ 4020#endif /* NEED_UI_LOOP_HOOK */
4674 4021
4675 /*added energy_prof statement by ksh in 2004-11-26 */ 4022 /*added energy_prof statement by ksh in 2004-11-26 */
4676 //chy 2005-07-28 for standalone 4023 //chy 2005-07-28 for standalone
4677 //ARMul_do_energy(state,instr,pc); 4024 //ARMul_do_energy(state,instr,pc);
4678//teawater add for record reg value to ./reg.txt 2005.07.10--------------------- 4025//teawater add for record reg value to ./reg.txt 2005.07.10---------------------
4679 if (state->tea_break_ok && pc == state->tea_break_addr) { 4026 if (state->tea_break_ok && pc == state->tea_break_addr) {
4680 ARMul_Debug (state, 0, 0); 4027 //ARMul_Debug (state, 0, 0);
4681 state->tea_break_ok = 0; 4028 state->tea_break_ok = 0;
4682 } 4029 } else {
4683 else { 4030 state->tea_break_ok = 1;
4684 state->tea_break_ok = 1; 4031 }
4685 }
4686//AJ2D-------------------------------------------------------------------------- 4032//AJ2D--------------------------------------------------------------------------
4687//chy 2006-04-14 for ctrl-c debug 4033//chy 2006-04-14 for ctrl-c debug
4688#if 0 4034#if 0
4689 if (debugmode) { 4035 if (debugmode) {
4690 if (instr != ARMul_ABORTWORD) { 4036 if (instr != ARMul_ABORTWORD) {
4691 remote_interrupt_test_time++; 4037 remote_interrupt_test_time++;
4692 //chy 2006-04-14 2000 should be changed in skyeye_conf ???!!! 4038 //chy 2006-04-14 2000 should be changed in skyeye_conf ???!!!
4693 if (remote_interrupt_test_time >= 2000) { 4039 if (remote_interrupt_test_time >= 2000) {
4694 remote_interrupt_test_time=0; 4040 remote_interrupt_test_time=0;
4695 if (remote_interrupt()) { 4041 if (remote_interrupt()) {
4696 //for test 4042 //for test
4697 //printf("SKYEYE: ICE_debug recv Ctrl_C\n"); 4043 //printf("SKYEYE: ICE_debug recv Ctrl_C\n");
4698 state->EndCondition = 0; 4044 state->EndCondition = 0;
4699 state->Emulate = STOP; 4045 state->Emulate = STOP;
4700 } 4046 }
4701 } 4047 }
4702 } 4048 }
4703 } 4049 }
4704#endif 4050#endif
4705 4051
4706 /* jump out every time */ 4052 /* jump out every time */
4707 //state->EndCondition = 0; 4053 //state->EndCondition = 0;
4708 //state->Emulate = STOP; 4054 //state->Emulate = STOP;
4709//chy 2006-04-12 for ICE debug 4055//chy 2006-04-12 for ICE debug
4710TEST_EMULATE: 4056TEST_EMULATE:
4711 if (state->Emulate == ONCE) 4057 if (state->Emulate == ONCE)
4712 state->Emulate = STOP; 4058 state->Emulate = STOP;
4713 //chy: 2003-08-23: should not use CHANGEMODE !!!! 4059 //chy: 2003-08-23: should not use CHANGEMODE !!!!
4714 /* If we have changed mode, allow the PC to advance before stopping. */ 4060 /* If we have changed mode, allow the PC to advance before stopping. */
4715 // else if (state->Emulate == CHANGEMODE) 4061 // else if (state->Emulate == CHANGEMODE)
4716 // continue; 4062 // continue;
4717 else if (state->Emulate != RUN) 4063 else if (state->Emulate != RUN)
4718 break; 4064 break;
4065 }
4066 while (state->NumInstrsToExecute--);
4067
4068 state->decoded = decoded;
4069 state->loaded = loaded;
4070 state->pc = pc;
4071 //chy 2006-04-12, for ICE debug
4072 state->decoded_addr=decoded_addr;
4073 state->loaded_addr=loaded_addr;
4074
4075 return pc;
4719 } 4076 }
4720 while (state->NumInstrsToExecute--);
4721
4722 state->decoded = decoded;
4723 state->loaded = loaded;
4724 state->pc = pc;
4725 //chy 2006-04-12, for ICE debug
4726 state->decoded_addr=decoded_addr;
4727 state->loaded_addr=loaded_addr;
4728
4729 return pc;
4730}
4731 4077
4732//teawater add for arm2x86 2005.02.17------------------------------------------- 4078//teawater add for arm2x86 2005.02.17-------------------------------------------
4733/*ywc 2005-04-01*/ 4079 /*ywc 2005-04-01*/
4734//#include "tb.h" 4080//#include "tb.h"
4735//#include "arm2x86_self.h" 4081//#include "arm2x86_self.h"
4736 4082
4737static volatile void (*gen_func) (void); 4083 static volatile void (*gen_func) (void);
4738//static volatile ARMul_State *tmp_st; 4084//static volatile ARMul_State *tmp_st;
4739//static volatile ARMul_State *save_st; 4085//static volatile ARMul_State *save_st;
4740static volatile uint32_t tmp_st; 4086 static volatile uint32_t tmp_st;
4741static volatile uint32_t save_st; 4087 static volatile uint32_t save_st;
4742static volatile uint32_t save_T0; 4088 static volatile uint32_t save_T0;
4743static volatile uint32_t save_T1; 4089 static volatile uint32_t save_T1;
4744static volatile uint32_t save_T2; 4090 static volatile uint32_t save_T2;
4745 4091
4746#ifdef MODE32 4092#ifdef MODE32
4747#ifdef DBCT 4093#ifdef DBCT
4748//teawater change for debug function 2005.07.09--------------------------------- 4094//teawater change for debug function 2005.07.09---------------------------------
4749ARMword 4095 ARMword
4750ARMul_Emulate32_dbct (ARMul_State * state) 4096 ARMul_Emulate32_dbct (ARMul_State * state) {
4751{ 4097 static int init = 0;
4752 static int init = 0; 4098 static FILE *fd;
4753 static FILE *fd;
4754
4755 /*if (!init) {
4756 4099
4757 fd = fopen("./pc.txt", "w"); 4100 /*if (!init) {
4758 if (!fd) {
4759 exit(-1);
4760 }
4761 init = 1;
4762 } */
4763 4101
4764 state->Reg[15] += INSN_SIZE; 4102 fd = fopen("./pc.txt", "w");
4765 do { 4103 if (!fd) {
4766 /*if (skyeye_config.log.logon>=1) { 4104 exit(-1);
4767 if (state->NumInstrs>=skyeye_config.log.start && state->NumInstrs<=skyeye_config.log.end) {
4768 static int mybegin=0;
4769 static int myinstrnum=0;
4770
4771 if (mybegin==0) mybegin=1;
4772 if (mybegin==1) {
4773 state->Reg[15] -= INSN_SIZE;
4774 if (skyeye_config.log.logon>=1) fprintf(skyeye_logfd,"N %llx :p %x,i %x,",state->NumInstrs, (state->Reg[15] - INSN_SIZE), instr);
4775 if (skyeye_config.log.logon>=2) SKYEYE_OUTREGS(skyeye_logfd);
4776 if (skyeye_config.log.logon>=3) SKYEYE_OUTMOREREGS(skyeye_logfd);
4777 fprintf(skyeye_logfd,"\n");
4778 if (skyeye_config.log.length>0) {
4779 myinstrnum++;
4780 if (myinstrnum>=skyeye_config.log.length) {
4781 myinstrnum=0;
4782 fflush(skyeye_logfd);
4783 fseek(skyeye_logfd,0L,SEEK_SET);
4784 }
4785 }
4786 state->Reg[15] += INSN_SIZE;
4787 }
4788 } 4105 }
4106 init = 1;
4789 } */ 4107 } */
4790 state->trap = 0; 4108
4791 gen_func = 4109 state->Reg[15] += INSN_SIZE;
4792 (void *) tb_find (state, state->Reg[15] - INSN_SIZE); 4110 do {
4793 if (!gen_func) { 4111 /*if (skyeye_config.log.logon>=1) {
4794 //fprintf(stderr, "SKYEYE: tb_find: Error in find the translate block.\n"); 4112 if (state->NumInstrs>=skyeye_config.log.start && state->NumInstrs<=skyeye_config.log.end) {
4795 //exit(-1); 4113 static int mybegin=0;
4796 //TRAP_INSN_ABORT 4114 static int myinstrnum=0;
4797 //TEA_OUT(printf("\n------------\npc:%x\n", state->Reg[15] - INSN_SIZE)); 4115
4798 //TEA_OUT(printf("TRAP_INSN_ABORT\n")); 4116 if (mybegin==0) mybegin=1;
4799//teawater add for xscale(arm v5) 2005.09.01------------------------------------ 4117 if (mybegin==1) {
4800 /*XScale_set_fsr_far(state, ARMul_CP15_R5_MMU_EXCPT, state->Reg[15] - INSN_SIZE); 4118 state->Reg[15] -= INSN_SIZE;
4801 state->Reg[15] += INSN_SIZE; 4119 if (skyeye_config.log.logon>=1) fprintf(skyeye_logfd,"N %llx :p %x,i %x,",state->NumInstrs, (state->Reg[15] - INSN_SIZE), instr);
4802 ARMul_Abort(state, ARMul_PrefetchAbortV); 4120 if (skyeye_config.log.logon>=2) SKYEYE_OUTREGS(skyeye_logfd);
4121 if (skyeye_config.log.logon>=3) SKYEYE_OUTMOREREGS(skyeye_logfd);
4122 fprintf(skyeye_logfd,"\n");
4123 if (skyeye_config.log.length>0) {
4124 myinstrnum++;
4125 if (myinstrnum>=skyeye_config.log.length) {
4126 myinstrnum=0;
4127 fflush(skyeye_logfd);
4128 fseek(skyeye_logfd,0L,SEEK_SET);
4129 }
4130 }
4803 state->Reg[15] += INSN_SIZE; 4131 state->Reg[15] += INSN_SIZE;
4804 goto next; */ 4132 }
4805 state->trap = TRAP_INSN_ABORT; 4133 }
4806 goto check; 4134 } */
4135 state->trap = 0;
4136 gen_func =
4137 (void *) tb_find (state, state->Reg[15] - INSN_SIZE);
4138 if (!gen_func) {
4139 //fprintf(stderr, "SKYEYE: tb_find: Error in find the translate block.\n");
4140 //exit(-1);
4141 //TRAP_INSN_ABORT
4142 //TEA_OUT(printf("\n------------\npc:%x\n", state->Reg[15] - INSN_SIZE));
4143 //TEA_OUT(printf("TRAP_INSN_ABORT\n"));
4144//teawater add for xscale(arm v5) 2005.09.01------------------------------------
4145 /*XScale_set_fsr_far(state, ARMul_CP15_R5_MMU_EXCPT, state->Reg[15] - INSN_SIZE);
4146 state->Reg[15] += INSN_SIZE;
4147 ARMul_Abort(state, ARMul_PrefetchAbortV);
4148 state->Reg[15] += INSN_SIZE;
4149 goto next; */
4150 state->trap = TRAP_INSN_ABORT;
4151 goto check;
4807//AJ2D-------------------------------------------------------------------------- 4152//AJ2D--------------------------------------------------------------------------
4808 } 4153 }
4809 4154
4810 save_st = (uint32_t) st; 4155 save_st = (uint32_t) st;
4811 save_T0 = T0; 4156 save_T0 = T0;
4812 save_T1 = T1; 4157 save_T1 = T1;
4813 save_T2 = T2; 4158 save_T2 = T2;
4814 tmp_st = (uint32_t) state; 4159 tmp_st = (uint32_t) state;
4815 wmb (); 4160 wmb ();
4816 st = (ARMul_State *) tmp_st; 4161 st = (ARMul_State *) tmp_st;
4817 gen_func (); 4162 gen_func ();
4818 st = (ARMul_State *) save_st; 4163 st = (ARMul_State *) save_st;
4819 T0 = save_T0; 4164 T0 = save_T0;
4820 T1 = save_T1; 4165 T1 = save_T1;
4821 T2 = save_T2; 4166 T2 = save_T2;
4822 4167
4823 /*if (state->trap != TRAP_OUT) { 4168 /*if (state->trap != TRAP_OUT) {
4824 state->tea_break_ok = 1; 4169 state->tea_break_ok = 1;
4825 } 4170 }
4826 if (state->trap <= TRAP_SET_R15) { 4171 if (state->trap <= TRAP_SET_R15) {
4827 goto next; 4172 goto next;
4828 } */ 4173 } */
4829 //TEA_OUT(printf("\n------------\npc:%x\n", state->Reg[15] - INSN_SIZE)); 4174 //TEA_OUT(printf("\n------------\npc:%x\n", state->Reg[15] - INSN_SIZE));
4830//teawater add check thumb 2005.07.21------------------------------------------- 4175//teawater add check thumb 2005.07.21-------------------------------------------
4831 /*if (TFLAG) { 4176 /*if (TFLAG) {
4832 state->Reg[15] -= 2; 4177 state->Reg[15] -= 2;
4833 return(state->Reg[15]); 4178 return(state->Reg[15]);
4834 } */ 4179 } */
4835//AJ2D-------------------------------------------------------------------------- 4180//AJ2D--------------------------------------------------------------------------
4836 4181
4837//teawater add for xscale(arm v5) 2005.09.01------------------------------------ 4182//teawater add for xscale(arm v5) 2005.09.01------------------------------------
4838 check: 4183check:
4839//AJ2D-------------------------------------------------------------------------- 4184//AJ2D--------------------------------------------------------------------------
4840 switch (state->trap) { 4185 switch (state->trap) {
4841 case TRAP_RESET: 4186 case TRAP_RESET: {
4842 {
4843 //TEA_OUT(printf("TRAP_RESET\n")); 4187 //TEA_OUT(printf("TRAP_RESET\n"));
4844 ARMul_Abort (state, ARMul_ResetV); 4188 ARMul_Abort (state, ARMul_ResetV);
4845 state->Reg[15] += INSN_SIZE; 4189 state->Reg[15] += INSN_SIZE;
4846 } 4190 }
4847 break; 4191 break;
4848 case TRAP_UNPREDICTABLE: 4192 case TRAP_UNPREDICTABLE: {
4849 { 4193 //ARMul_Debug (state, 0, 0);
4850 ARMul_Debug (state, 0, 0);
4851 } 4194 }
4852 break; 4195 break;
4853 case TRAP_INSN_UNDEF: 4196 case TRAP_INSN_UNDEF: {
4854 {
4855 //TEA_OUT(printf("TRAP_INSN_UNDEF\n")); 4197 //TEA_OUT(printf("TRAP_INSN_UNDEF\n"));
4856 state->Reg[15] += INSN_SIZE; 4198 state->Reg[15] += INSN_SIZE;
4857 ARMul_UndefInstr (state, 0); 4199 ARMul_UndefInstr (state, 0);
4858 state->Reg[15] += INSN_SIZE; 4200 state->Reg[15] += INSN_SIZE;
4859 } 4201 }
4860 break; 4202 break;
4861 case TRAP_SWI: 4203 case TRAP_SWI: {
4862 {
4863 //TEA_OUT(printf("TRAP_SWI\n")); 4204 //TEA_OUT(printf("TRAP_SWI\n"));
4864 state->Reg[15] += INSN_SIZE; 4205 state->Reg[15] += INSN_SIZE;
4865 ARMul_Abort (state, ARMul_SWIV); 4206 ARMul_Abort (state, ARMul_SWIV);
@@ -4867,44 +4208,39 @@ ARMul_Emulate32_dbct (ARMul_State * state)
4867 } 4208 }
4868 break; 4209 break;
4869//teawater add for xscale(arm v5) 2005.09.01------------------------------------ 4210//teawater add for xscale(arm v5) 2005.09.01------------------------------------
4870 case TRAP_INSN_ABORT: 4211 case TRAP_INSN_ABORT: {
4871 { 4212 /*XScale_set_fsr_far (state,
4872 XScale_set_fsr_far (state, 4213 ARMul_CP15_R5_MMU_EXCPT,
4873 ARMul_CP15_R5_MMU_EXCPT, 4214 state->Reg[15] -
4874 state->Reg[15] - 4215 INSN_SIZE);*/
4875 INSN_SIZE);
4876 state->Reg[15] += INSN_SIZE; 4216 state->Reg[15] += INSN_SIZE;
4877 ARMul_Abort (state, ARMul_PrefetchAbortV); 4217 ARMul_Abort (state, ARMul_PrefetchAbortV);
4878 state->Reg[15] += INSN_SIZE; 4218 state->Reg[15] += INSN_SIZE;
4879 } 4219 }
4880 break; 4220 break;
4881//AJ2D-------------------------------------------------------------------------- 4221//AJ2D--------------------------------------------------------------------------
4882 case TRAP_DATA_ABORT: 4222 case TRAP_DATA_ABORT: {
4883 {
4884 //TEA_OUT(printf("TRAP_DATA_ABORT\n")); 4223 //TEA_OUT(printf("TRAP_DATA_ABORT\n"));
4885 state->Reg[15] += INSN_SIZE; 4224 state->Reg[15] += INSN_SIZE;
4886 ARMul_Abort (state, ARMul_DataAbortV); 4225 ARMul_Abort (state, ARMul_DataAbortV);
4887 state->Reg[15] += INSN_SIZE; 4226 state->Reg[15] += INSN_SIZE;
4888 } 4227 }
4889 break; 4228 break;
4890 case TRAP_IRQ: 4229 case TRAP_IRQ: {
4891 {
4892 //TEA_OUT(printf("TRAP_IRQ\n")); 4230 //TEA_OUT(printf("TRAP_IRQ\n"));
4893 state->Reg[15] += INSN_SIZE; 4231 state->Reg[15] += INSN_SIZE;
4894 ARMul_Abort (state, ARMul_IRQV); 4232 ARMul_Abort (state, ARMul_IRQV);
4895 state->Reg[15] += INSN_SIZE; 4233 state->Reg[15] += INSN_SIZE;
4896 } 4234 }
4897 break; 4235 break;
4898 case TRAP_FIQ: 4236 case TRAP_FIQ: {
4899 {
4900 //TEA_OUT(printf("TRAP_FIQ\n")); 4237 //TEA_OUT(printf("TRAP_FIQ\n"));
4901 state->Reg[15] += INSN_SIZE; 4238 state->Reg[15] += INSN_SIZE;
4902 ARMul_Abort (state, ARMul_FIQV); 4239 ARMul_Abort (state, ARMul_FIQV);
4903 state->Reg[15] += INSN_SIZE; 4240 state->Reg[15] += INSN_SIZE;
4904 } 4241 }
4905 break; 4242 break;
4906 case TRAP_SETS_R15: 4243 case TRAP_SETS_R15: {
4907 {
4908 //TEA_OUT(printf("TRAP_SETS_R15\n")); 4244 //TEA_OUT(printf("TRAP_SETS_R15\n"));
4909 /*if (state->Bank > 0) { 4245 /*if (state->Bank > 0) {
4910 state->Cpsr = state->Spsr[state->Bank]; 4246 state->Cpsr = state->Spsr[state->Bank];
@@ -4913,1699 +4249,1785 @@ ARMul_Emulate32_dbct (ARMul_State * state)
4913 WriteSR15 (state, state->Reg[15]); 4249 WriteSR15 (state, state->Reg[15]);
4914 } 4250 }
4915 break; 4251 break;
4916 case TRAP_SET_CPSR: 4252 case TRAP_SET_CPSR: {
4917 {
4918 //TEA_OUT(printf("TRAP_SET_CPSR\n")); 4253 //TEA_OUT(printf("TRAP_SET_CPSR\n"));
4919 //chy 2006-02-15 USERBANK=SYSTEMBANK=0 4254 //chy 2006-02-15 USERBANK=SYSTEMBANK=0
4920 //chy 2006-02-16 should use Mode to test 4255 //chy 2006-02-16 should use Mode to test
4921 //if (state->Bank > 0) { 4256 //if (state->Bank > 0) {
4922 if (state->Mode != USER26MODE && state->Mode != USER32MODE){ 4257 if (state->Mode != USER26MODE && state->Mode != USER32MODE) {
4923 ARMul_CPSRAltered (state); 4258 //ARMul_CPSRAltered (state);
4924 } 4259 }
4925 state->Reg[15] += INSN_SIZE; 4260 state->Reg[15] += INSN_SIZE;
4926 } 4261 }
4927 break; 4262 break;
4928 case TRAP_OUT: 4263 case TRAP_OUT: {
4929 {
4930 //TEA_OUT(printf("TRAP_OUT\n")); 4264 //TEA_OUT(printf("TRAP_OUT\n"));
4931 goto out; 4265 goto out;
4932 } 4266 }
4933 break; 4267 break;
4934 case TRAP_BREAKPOINT: 4268 case TRAP_BREAKPOINT: {
4935 {
4936 //TEA_OUT(printf("TRAP_BREAKPOINT\n")); 4269 //TEA_OUT(printf("TRAP_BREAKPOINT\n"));
4937 state->Reg[15] -= INSN_SIZE; 4270 state->Reg[15] -= INSN_SIZE;
4938 if (!ARMul_OSHandleSWI 4271 if (!ARMul_OSHandleSWI
4939 (state, SWI_Breakpoint)) { 4272 (state, SWI_Breakpoint)) {
4940 ARMul_Abort (state, ARMul_SWIV); 4273 ARMul_Abort (state, ARMul_SWIV);
4941 } 4274 }
4942 state->Reg[15] += INSN_SIZE; 4275 state->Reg[15] += INSN_SIZE;
4943 } 4276 }
4944 break; 4277 break;
4945 } 4278 }
4946 4279
4947 next: 4280next:
4948 if (state->Emulate == ONCE) { 4281 if (state->Emulate == ONCE) {
4949 state->Emulate = STOP; 4282 state->Emulate = STOP;
4950 break; 4283 break;
4951 } 4284 } else if (state->Emulate != RUN) {
4952 else if (state->Emulate != RUN) { 4285 break;
4953 break; 4286 }
4954 } 4287 } while (!state->stop_simulator);
4955 }
4956 while (!state->stop_simulator);
4957 4288
4958 out: 4289out:
4959 state->Reg[15] -= INSN_SIZE; 4290 state->Reg[15] -= INSN_SIZE;
4960 return (state->Reg[15]); 4291 return (state->Reg[15]);
4961} 4292 }
4962#endif 4293#endif
4963//AJ2D-------------------------------------------------------------------------- 4294//AJ2D--------------------------------------------------------------------------
4964#endif 4295#endif
4965//AJ2D-------------------------------------------------------------------------- 4296//AJ2D--------------------------------------------------------------------------
4966 4297
4967/* This routine evaluates most Data Processing register RHS's with the S 4298 /* This routine evaluates most Data Processing register RHS's with the S
4968 bit clear. It is intended to be called from the macro DPRegRHS, which 4299 bit clear. It is intended to be called from the macro DPRegRHS, which
4969 filters the common case of an unshifted register with in line code. */ 4300 filters the common case of an unshifted register with in line code. */
4970 4301
4971static ARMword 4302 static ARMword
4972GetDPRegRHS (ARMul_State * state, ARMword instr) 4303 GetDPRegRHS (ARMul_State * state, ARMword instr) {
4973{ 4304 ARMword shamt, base;
4974 ARMword shamt, base;
4975 4305
4976 base = RHSReg; 4306 base = RHSReg;
4977 if (BIT (4)) { 4307 if (BIT (4)) {
4978 /* Shift amount in a register. */ 4308 /* Shift amount in a register. */
4979 UNDEF_Shift; 4309 UNDEF_Shift;
4980 INCPC; 4310 INCPC;
4981#ifndef MODE32 4311#ifndef MODE32
4982 if (base == 15) 4312 if (base == 15)
4983 base = ECC | ER15INT | R15PC | EMODE; 4313 base = ECC | ER15INT | R15PC | EMODE;
4984 else
4985#endif
4986 base = state->Reg[base];
4987 ARMul_Icycles (state, 1, 0L);
4988 shamt = state->Reg[BITS (8, 11)] & 0xff;
4989 switch ((int) BITS (5, 6)) {
4990 case LSL:
4991 if (shamt == 0)
4992 return (base);
4993 else if (shamt >= 32)
4994 return (0);
4995 else 4314 else
4996 return (base << shamt);
4997 case LSR:
4998 if (shamt == 0)
4999 return (base);
5000 else if (shamt >= 32)
5001 return (0);
5002 else
5003 return (base >> shamt);
5004 case ASR:
5005 if (shamt == 0)
5006 return (base);
5007 else if (shamt >= 32)
5008 return ((ARMword) ((int) base >> 31L));
5009 else
5010 return ((ARMword)
5011 (( int) base >> (int) shamt));
5012 case ROR:
5013 shamt &= 0x1f;
5014 if (shamt == 0)
5015 return (base);
5016 else
5017 return ((base << (32 - shamt)) |
5018 (base >> shamt));
5019 }
5020 }
5021 else {
5022 /* Shift amount is a constant. */
5023#ifndef MODE32
5024 if (base == 15)
5025 base = ECC | ER15INT | R15PC | EMODE;
5026 else
5027#endif 4315#endif
5028 base = state->Reg[base]; 4316 base = state->Reg[base];
5029 shamt = BITS (7, 11); 4317 ARMul_Icycles (state, 1, 0L);
5030 switch ((int) BITS (5, 6)) { 4318 shamt = state->Reg[BITS (8, 11)] & 0xff;
5031 case LSL: 4319 switch ((int) BITS (5, 6)) {
5032 return (base << shamt); 4320 case LSL:
5033 case LSR: 4321 if (shamt == 0)
5034 if (shamt == 0) 4322 return (base);
5035 return (0); 4323 else if (shamt >= 32)
5036 else 4324 return (0);
5037 return (base >> shamt); 4325 else
5038 case ASR: 4326 return (base << shamt);
5039 if (shamt == 0) 4327 case LSR:
5040 return ((ARMword) (( int) base >> 31L)); 4328 if (shamt == 0)
5041 else 4329 return (base);
5042 return ((ARMword) 4330 else if (shamt >= 32)
5043 (( int) base >> (int) shamt)); 4331 return (0);
5044 case ROR: 4332 else
5045 if (shamt == 0) 4333 return (base >> shamt);
5046 /* It's an RRX. */ 4334 case ASR:
5047 return ((base >> 1) | (CFLAG << 31)); 4335 if (shamt == 0)
4336 return (base);
4337 else if (shamt >= 32)
4338 return ((ARMword) ((int) base >> 31L));
4339 else
4340 return ((ARMword)
4341 (( int) base >> (int) shamt));
4342 case ROR:
4343 shamt &= 0x1f;
4344 if (shamt == 0)
4345 return (base);
4346 else
4347 return ((base << (32 - shamt)) |
4348 (base >> shamt));
4349 }
4350 } else {
4351 /* Shift amount is a constant. */
4352#ifndef MODE32
4353 if (base == 15)
4354 base = ECC | ER15INT | R15PC | EMODE;
5048 else 4355 else
5049 return ((base << (32 - shamt)) | 4356#endif
5050 (base >> shamt)); 4357 base = state->Reg[base];
4358 shamt = BITS (7, 11);
4359 switch ((int) BITS (5, 6)) {
4360 case LSL:
4361 return (base << shamt);
4362 case LSR:
4363 if (shamt == 0)
4364 return (0);
4365 else
4366 return (base >> shamt);
4367 case ASR:
4368 if (shamt == 0)
4369 return ((ARMword) (( int) base >> 31L));
4370 else
4371 return ((ARMword)
4372 (( int) base >> (int) shamt));
4373 case ROR:
4374 if (shamt == 0)
4375 /* It's an RRX. */
4376 return ((base >> 1) | (CFLAG << 31));
4377 else
4378 return ((base << (32 - shamt)) |
4379 (base >> shamt));
4380 }
5051 } 4381 }
5052 }
5053 4382
5054 return 0; 4383 return 0;
5055} 4384 }
5056 4385
5057/* This routine evaluates most Logical Data Processing register RHS's 4386 /* This routine evaluates most Logical Data Processing register RHS's
5058 with the S bit set. It is intended to be called from the macro 4387 with the S bit set. It is intended to be called from the macro
5059 DPSRegRHS, which filters the common case of an unshifted register 4388 DPSRegRHS, which filters the common case of an unshifted register
5060 with in line code. */ 4389 with in line code. */
5061 4390
5062static ARMword 4391 static ARMword
5063GetDPSRegRHS (ARMul_State * state, ARMword instr) 4392 GetDPSRegRHS (ARMul_State * state, ARMword instr) {
5064{ 4393 ARMword shamt, base;
5065 ARMword shamt, base;
5066 4394
5067 base = RHSReg; 4395 base = RHSReg;
5068 if (BIT (4)) { 4396 if (BIT (4)) {
5069 /* Shift amount in a register. */ 4397 /* Shift amount in a register. */
5070 UNDEF_Shift; 4398 UNDEF_Shift;
5071 INCPC; 4399 INCPC;
5072#ifndef MODE32 4400#ifndef MODE32
5073 if (base == 15) 4401 if (base == 15)
5074 base = ECC | ER15INT | R15PC | EMODE; 4402 base = ECC | ER15INT | R15PC | EMODE;
5075 else 4403 else
5076#endif 4404#endif
5077 base = state->Reg[base]; 4405 base = state->Reg[base];
5078 ARMul_Icycles (state, 1, 0L); 4406 ARMul_Icycles (state, 1, 0L);
5079 shamt = state->Reg[BITS (8, 11)] & 0xff; 4407 shamt = state->Reg[BITS (8, 11)] & 0xff;
5080 switch ((int) BITS (5, 6)) { 4408 switch ((int) BITS (5, 6)) {
5081 case LSL: 4409 case LSL:
5082 if (shamt == 0) 4410 if (shamt == 0)
5083 return (base); 4411 return (base);
5084 else if (shamt == 32) { 4412 else if (shamt == 32) {
5085 ASSIGNC (base & 1); 4413 ASSIGNC (base & 1);
5086 return (0); 4414 return (0);
5087 } 4415 } else if (shamt > 32) {
5088 else if (shamt > 32) { 4416 CLEARC;
5089 CLEARC; 4417 return (0);
5090 return (0); 4418 } else {
5091 } 4419 ASSIGNC ((base >> (32 - shamt)) & 1);
5092 else { 4420 return (base << shamt);
5093 ASSIGNC ((base >> (32 - shamt)) & 1); 4421 }
5094 return (base << shamt); 4422 case LSR:
5095 } 4423 if (shamt == 0)
5096 case LSR: 4424 return (base);
5097 if (shamt == 0) 4425 else if (shamt == 32) {
5098 return (base); 4426 ASSIGNC (base >> 31);
5099 else if (shamt == 32) { 4427 return (0);
5100 ASSIGNC (base >> 31); 4428 } else if (shamt > 32) {
5101 return (0); 4429 CLEARC;
5102 } 4430 return (0);
5103 else if (shamt > 32) { 4431 } else {
5104 CLEARC; 4432 ASSIGNC ((base >> (shamt - 1)) & 1);
5105 return (0); 4433 return (base >> shamt);
5106 } 4434 }
5107 else { 4435 case ASR:
5108 ASSIGNC ((base >> (shamt - 1)) & 1); 4436 if (shamt == 0)
5109 return (base >> shamt); 4437 return (base);
5110 } 4438 else if (shamt >= 32) {
5111 case ASR: 4439 ASSIGNC (base >> 31L);
5112 if (shamt == 0) 4440 return ((ARMword) (( int) base >> 31L));
5113 return (base); 4441 } else {
5114 else if (shamt >= 32) { 4442 ASSIGNC ((ARMword)
5115 ASSIGNC (base >> 31L); 4443 (( int) base >>
5116 return ((ARMword) (( int) base >> 31L)); 4444 (int) (shamt - 1)) & 1);
5117 } 4445 return ((ARMword)
5118 else { 4446 ((int) base >> (int) shamt));
5119 ASSIGNC ((ARMword) 4447 }
5120 (( int) base >> 4448 case ROR:
5121 (int) (shamt - 1)) & 1); 4449 if (shamt == 0)
5122 return ((ARMword) 4450 return (base);
5123 ((int) base >> (int) shamt)); 4451 shamt &= 0x1f;
5124 } 4452 if (shamt == 0) {
5125 case ROR: 4453 ASSIGNC (base >> 31);
5126 if (shamt == 0) 4454 return (base);
5127 return (base); 4455 } else {
5128 shamt &= 0x1f; 4456 ASSIGNC ((base >> (shamt - 1)) & 1);
5129 if (shamt == 0) { 4457 return ((base << (32 - shamt)) |
5130 ASSIGNC (base >> 31); 4458 (base >> shamt));
5131 return (base); 4459 }
5132 }
5133 else {
5134 ASSIGNC ((base >> (shamt - 1)) & 1);
5135 return ((base << (32 - shamt)) |
5136 (base >> shamt));
5137 } 4460 }
5138 } 4461 } else {
5139 } 4462 /* Shift amount is a constant. */
5140 else {
5141 /* Shift amount is a constant. */
5142#ifndef MODE32 4463#ifndef MODE32
5143 if (base == 15) 4464 if (base == 15)
5144 base = ECC | ER15INT | R15PC | EMODE; 4465 base = ECC | ER15INT | R15PC | EMODE;
5145 else 4466 else
5146#endif 4467#endif
5147 base = state->Reg[base]; 4468 base = state->Reg[base];
5148 shamt = BITS (7, 11); 4469 shamt = BITS (7, 11);
5149 4470
5150 switch ((int) BITS (5, 6)) { 4471 switch ((int) BITS (5, 6)) {
5151 case LSL: 4472 case LSL:
5152 ASSIGNC ((base >> (32 - shamt)) & 1); 4473 ASSIGNC ((base >> (32 - shamt)) & 1);
5153 return (base << shamt); 4474 return (base << shamt);
5154 case LSR: 4475 case LSR:
5155 if (shamt == 0) { 4476 if (shamt == 0) {
5156 ASSIGNC (base >> 31); 4477 ASSIGNC (base >> 31);
5157 return (0); 4478 return (0);
5158 } 4479 } else {
5159 else { 4480 ASSIGNC ((base >> (shamt - 1)) & 1);
5160 ASSIGNC ((base >> (shamt - 1)) & 1); 4481 return (base >> shamt);
5161 return (base >> shamt); 4482 }
5162 } 4483 case ASR:
5163 case ASR: 4484 if (shamt == 0) {
5164 if (shamt == 0) { 4485 ASSIGNC (base >> 31L);
5165 ASSIGNC (base >> 31L); 4486 return ((ARMword) ((int) base >> 31L));
5166 return ((ARMword) ((int) base >> 31L)); 4487 } else {
5167 } 4488 ASSIGNC ((ARMword)
5168 else { 4489 ((int) base >>
5169 ASSIGNC ((ARMword) 4490 (int) (shamt - 1)) & 1);
5170 ((int) base >> 4491 return ((ARMword)
5171 (int) (shamt - 1)) & 1); 4492 (( int) base >> (int) shamt));
5172 return ((ARMword) 4493 }
5173 (( int) base >> (int) shamt)); 4494 case ROR:
5174 } 4495 if (shamt == 0) {
5175 case ROR: 4496 /* It's an RRX. */
5176 if (shamt == 0) { 4497 shamt = CFLAG;
5177 /* It's an RRX. */ 4498 ASSIGNC (base & 1);
5178 shamt = CFLAG; 4499 return ((base >> 1) | (shamt << 31));
5179 ASSIGNC (base & 1); 4500 } else {
5180 return ((base >> 1) | (shamt << 31)); 4501 ASSIGNC ((base >> (shamt - 1)) & 1);
5181 } 4502 return ((base << (32 - shamt)) |
5182 else { 4503 (base >> shamt));
5183 ASSIGNC ((base >> (shamt - 1)) & 1); 4504 }
5184 return ((base << (32 - shamt)) |
5185 (base >> shamt));
5186 } 4505 }
5187 } 4506 }
5188 }
5189 4507
5190 return 0; 4508 return 0;
5191} 4509 }
5192 4510
5193/* This routine handles writes to register 15 when the S bit is not set. */ 4511 /* This routine handles writes to register 15 when the S bit is not set. */
5194 4512
5195static void 4513 static void
5196WriteR15 (ARMul_State * state, ARMword src) 4514 WriteR15 (ARMul_State * state, ARMword src) {
5197{ 4515 /* The ARM documentation states that the two least significant bits
5198 /* The ARM documentation states that the two least significant bits 4516 are discarded when setting PC, except in the cases handled by
5199 are discarded when setting PC, except in the cases handled by 4517 WriteR15Branch() below. It's probably an oversight: in THUMB
5200 WriteR15Branch() below. It's probably an oversight: in THUMB 4518 mode, the second least significant bit should probably not be
5201 mode, the second least significant bit should probably not be 4519 discarded. */
5202 discarded. */
5203#ifdef MODET 4520#ifdef MODET
5204 if (TFLAG) 4521 if (TFLAG)
5205 src &= 0xfffffffe; 4522 src &= 0xfffffffe;
5206 else 4523 else
5207#endif 4524#endif
5208 src &= 0xfffffffc; 4525 src &= 0xfffffffc;
5209 4526
5210#ifdef MODE32 4527#ifdef MODE32
5211 state->Reg[15] = src & PCBITS; 4528 state->Reg[15] = src & PCBITS;
5212#else 4529#else
5213 state->Reg[15] = (src & R15PCBITS) | ECC | ER15INT | EMODE; 4530 state->Reg[15] = (src & R15PCBITS) | ECC | ER15INT | EMODE;
5214 ARMul_R15Altered (state); 4531 ARMul_R15Altered (state);
5215#endif 4532#endif
5216 4533
5217 FLUSHPIPE; 4534 FLUSHPIPE;
5218} 4535 }
5219 4536
5220/* This routine handles writes to register 15 when the S bit is set. */ 4537 /* This routine handles writes to register 15 when the S bit is set. */
5221 4538
5222static void 4539 static void
5223WriteSR15 (ARMul_State * state, ARMword src) 4540 WriteSR15 (ARMul_State * state, ARMword src) {
5224{
5225#ifdef MODE32 4541#ifdef MODE32
5226 if (state->Bank > 0) { 4542 if (state->Bank > 0) {
5227 state->Cpsr = state->Spsr[state->Bank]; 4543 state->Cpsr = state->Spsr[state->Bank];
5228 ARMul_CPSRAltered (state); 4544 //ARMul_CPSRAltered (state);
5229 } 4545 }
5230#ifdef MODET 4546#ifdef MODET
5231 if (TFLAG) 4547 if (TFLAG)
5232 src &= 0xfffffffe; 4548 src &= 0xfffffffe;
5233 else 4549 else
5234#endif 4550#endif
5235 src &= 0xfffffffc; 4551 src &= 0xfffffffc;
5236 state->Reg[15] = src & PCBITS; 4552 state->Reg[15] = src & PCBITS;
5237#else 4553#else
5238#ifdef MODET 4554#ifdef MODET
5239 if (TFLAG) 4555 if (TFLAG)
5240 /* ARMul_R15Altered would have to support it. */ 4556 /* ARMul_R15Altered would have to support it. */
5241 abort (); 4557 abort ();
5242 else 4558 else
5243#endif 4559#endif
5244 src &= 0xfffffffc; 4560 src &= 0xfffffffc;
5245 4561
5246 if (state->Bank == USERBANK) 4562 if (state->Bank == USERBANK)
5247 state->Reg[15] = 4563 state->Reg[15] =
5248 (src & (CCBITS | R15PCBITS)) | ER15INT | EMODE; 4564 (src & (CCBITS | R15PCBITS)) | ER15INT | EMODE;
5249 else 4565 else
5250 state->Reg[15] = src; 4566 state->Reg[15] = src;
5251 4567
5252 ARMul_R15Altered (state); 4568 ARMul_R15Altered (state);
5253#endif 4569#endif
5254 FLUSHPIPE; 4570 FLUSHPIPE;
5255} 4571 }
5256 4572
5257/* In machines capable of running in Thumb mode, BX, BLX, LDR and LDM 4573 /* In machines capable of running in Thumb mode, BX, BLX, LDR and LDM
5258 will switch to Thumb mode if the least significant bit is set. */ 4574 will switch to Thumb mode if the least significant bit is set. */
5259 4575
5260static void 4576 static void
5261WriteR15Branch (ARMul_State * state, ARMword src) 4577 WriteR15Branch (ARMul_State * state, ARMword src) {
5262{
5263#ifdef MODET 4578#ifdef MODET
5264 if (src & 1) { 4579 if (src & 1) {
5265 /* Thumb bit. */ 4580 /* Thumb bit. */
5266 SETT; 4581 SETT;
5267 state->Reg[15] = src & 0xfffffffe; 4582 state->Reg[15] = src & 0xfffffffe;
5268 } 4583 } else {
5269 else { 4584 CLEART;
5270 CLEART; 4585 state->Reg[15] = src & 0xfffffffc;
5271 state->Reg[15] = src & 0xfffffffc; 4586 }
5272 } 4587 state->Cpsr = ARMul_GetCPSR (state);
5273 state->Cpsr = ARMul_GetCPSR (state); 4588 FLUSHPIPE;
5274 FLUSHPIPE;
5275#else 4589#else
5276 WriteR15 (state, src); 4590 WriteR15 (state, src);
5277#endif 4591#endif
5278} 4592 }
5279 4593
5280/* This routine evaluates most Load and Store register RHS's. It is 4594 /* This routine evaluates most Load and Store register RHS's. It is
5281 intended to be called from the macro LSRegRHS, which filters the 4595 intended to be called from the macro LSRegRHS, which filters the
5282 common case of an unshifted register with in line code. */ 4596 common case of an unshifted register with in line code. */
5283 4597
5284static ARMword 4598 static ARMword
5285GetLSRegRHS (ARMul_State * state, ARMword instr) 4599 GetLSRegRHS (ARMul_State * state, ARMword instr) {
5286{ 4600 ARMword shamt, base;
5287 ARMword shamt, base;
5288 4601
5289 base = RHSReg; 4602 base = RHSReg;
5290#ifndef MODE32 4603#ifndef MODE32
5291 if (base == 15) 4604 if (base == 15)
5292 /* Now forbidden, but ... */ 4605 /* Now forbidden, but ... */
5293 base = ECC | ER15INT | R15PC | EMODE; 4606 base = ECC | ER15INT | R15PC | EMODE;
5294 else
5295#endif
5296 base = state->Reg[base];
5297
5298 shamt = BITS (7, 11);
5299 switch ((int) BITS (5, 6)) {
5300 case LSL:
5301 return (base << shamt);
5302 case LSR:
5303 if (shamt == 0)
5304 return (0);
5305 else
5306 return (base >> shamt);
5307 case ASR:
5308 if (shamt == 0)
5309 return ((ARMword) (( int) base >> 31L));
5310 else
5311 return ((ARMword) (( int) base >> (int) shamt));
5312 case ROR:
5313 if (shamt == 0)
5314 /* It's an RRX. */
5315 return ((base >> 1) | (CFLAG << 31));
5316 else 4607 else
5317 return ((base << (32 - shamt)) | (base >> shamt)); 4608#endif
5318 default: 4609 base = state->Reg[base];
5319 break; 4610
4611 shamt = BITS (7, 11);
4612 switch ((int) BITS (5, 6)) {
4613 case LSL:
4614 return (base << shamt);
4615 case LSR:
4616 if (shamt == 0)
4617 return (0);
4618 else
4619 return (base >> shamt);
4620 case ASR:
4621 if (shamt == 0)
4622 return ((ARMword) (( int) base >> 31L));
4623 else
4624 return ((ARMword) (( int) base >> (int) shamt));
4625 case ROR:
4626 if (shamt == 0)
4627 /* It's an RRX. */
4628 return ((base >> 1) | (CFLAG << 31));
4629 else
4630 return ((base << (32 - shamt)) | (base >> shamt));
4631 default:
4632 break;
4633 }
4634 return 0;
5320 } 4635 }
5321 return 0;
5322}
5323 4636
5324/* This routine evaluates the ARM7T halfword and signed transfer RHS's. */ 4637 /* This routine evaluates the ARM7T halfword and signed transfer RHS's. */
5325 4638
5326static ARMword 4639 static ARMword
5327GetLS7RHS (ARMul_State * state, ARMword instr) 4640 GetLS7RHS (ARMul_State * state, ARMword instr) {
5328{ 4641 if (BIT (22) == 0) {
5329 if (BIT (22) == 0) { 4642 /* Register. */
5330 /* Register. */
5331#ifndef MODE32 4643#ifndef MODE32
5332 if (RHSReg == 15) 4644 if (RHSReg == 15)
5333 /* Now forbidden, but ... */ 4645 /* Now forbidden, but ... */
5334 return ECC | ER15INT | R15PC | EMODE; 4646 return ECC | ER15INT | R15PC | EMODE;
5335#endif 4647#endif
5336 return state->Reg[RHSReg]; 4648 return state->Reg[RHSReg];
5337 } 4649 }
5338 4650
5339 /* Immediate. */ 4651 /* Immediate. */
5340 return BITS (0, 3) | (BITS (8, 11) << 4); 4652 return BITS (0, 3) | (BITS (8, 11) << 4);
5341} 4653 }
5342 4654
5343/* This function does the work of loading a word for a LDR instruction. */ 4655 /* This function does the work of loading a word for a LDR instruction. */
5344#define MEM_LOAD_LOG(description) if (skyeye_config.log.memlogon >= 1) { \ 4656#define MEM_LOAD_LOG(description) if (skyeye_config.log.memlogon >= 1) { \
5345 fprintf(skyeye_logfd, \ 4657 fprintf(skyeye_logfd, \
5346 "m LOAD %s: N %llx :p %x :i %x :a %x :d %x\n", \ 4658 "m LOAD %s: N %llx :p %x :i %x :a %x :d %x\n", \
5347 description, state->NumInstrs, state->pc, instr, \ 4659 description, state->NumInstrs, state->pc, instr, \
5348 address, dest); \ 4660 address, dest); \
5349 } 4661 }
5350 4662
5351#define MEM_STORE_LOG(description) if (skyeye_config.log.memlogon >= 1) { \ 4663#define MEM_STORE_LOG(description) if (skyeye_config.log.memlogon >= 1) { \
5352 fprintf(skyeye_logfd, \ 4664 fprintf(skyeye_logfd, \
5353 "m STORE %s: N %llx :p %x :i %x :a %x :d %x\n", \ 4665 "m STORE %s: N %llx :p %x :i %x :a %x :d %x\n", \
5354 description, state->NumInstrs, state->pc, instr, \ 4666 description, state->NumInstrs, state->pc, instr, \
5355 address, DEST); \ 4667 address, DEST); \
5356 } 4668 }
5357 4669
5358 4670
5359 4671
5360static unsigned 4672 static unsigned
5361LoadWord (ARMul_State * state, ARMword instr, ARMword address) 4673 LoadWord (ARMul_State * state, ARMword instr, ARMword address) {
5362{ 4674 ARMword dest;
5363 ARMword dest;
5364 4675
5365 BUSUSEDINCPCS; 4676 BUSUSEDINCPCS;
5366#ifndef MODE32 4677#ifndef MODE32
5367 if (ADDREXCEPT (address)) 4678 if (ADDREXCEPT (address))
5368 INTERNALABORT (address); 4679 INTERNALABORT (address);
5369#endif 4680#endif
5370 4681
5371 dest = ARMul_LoadWordN (state, address); 4682 dest = ARMul_LoadWordN (state, address);
5372 4683
5373 if (state->Aborted) { 4684 if (state->Aborted) {
5374 TAKEABORT; 4685 TAKEABORT;
5375 return state->lateabtSig; 4686 return state->lateabtSig;
5376 } 4687 }
5377 if (address & 3) 4688 if (address & 3)
5378 dest = ARMul_Align (state, address, dest); 4689 dest = ARMul_Align (state, address, dest);
5379 WRITEDESTB (dest); 4690 WRITEDESTB (dest);
5380 ARMul_Icycles (state, 1, 0L); 4691 ARMul_Icycles (state, 1, 0L);
5381 4692
5382 //MEM_LOAD_LOG("WORD"); 4693 //MEM_LOAD_LOG("WORD");
5383 4694
5384 return (DESTReg != LHSReg); 4695 return (DESTReg != LHSReg);
5385} 4696 }
5386 4697
5387#ifdef MODET 4698#ifdef MODET
5388/* This function does the work of loading a halfword. */ 4699 /* This function does the work of loading a halfword. */
5389 4700
5390static unsigned 4701 static unsigned
5391LoadHalfWord (ARMul_State * state, ARMword instr, ARMword address, 4702 LoadHalfWord (ARMul_State * state, ARMword instr, ARMword address,
5392 int signextend) 4703 int signextend) {
5393{ 4704 ARMword dest;
5394 ARMword dest;
5395 4705
5396 BUSUSEDINCPCS; 4706 BUSUSEDINCPCS;
5397#ifndef MODE32 4707#ifndef MODE32
5398 if (ADDREXCEPT (address)) 4708 if (ADDREXCEPT (address))
5399 INTERNALABORT (address); 4709 INTERNALABORT (address);
5400#endif 4710#endif
5401 dest = ARMul_LoadHalfWord (state, address); 4711 dest = ARMul_LoadHalfWord (state, address);
5402 if (state->Aborted) { 4712 if (state->Aborted) {
5403 TAKEABORT; 4713 TAKEABORT;
5404 return state->lateabtSig; 4714 return state->lateabtSig;
5405 } 4715 }
5406 UNDEF_LSRBPC; 4716 UNDEF_LSRBPC;
5407 if (signextend) 4717 if (signextend)
5408 if (dest & 1 << (16 - 1)) 4718 if (dest & 1 << (16 - 1))
5409 dest = (dest & ((1 << 16) - 1)) - (1 << 16); 4719 dest = (dest & ((1 << 16) - 1)) - (1 << 16);
5410 4720
5411 WRITEDEST (dest); 4721 WRITEDEST (dest);
5412 ARMul_Icycles (state, 1, 0L); 4722 ARMul_Icycles (state, 1, 0L);
5413 4723
5414 //MEM_LOAD_LOG("HALFWORD"); 4724 //MEM_LOAD_LOG("HALFWORD");
5415 4725
5416 return (DESTReg != LHSReg); 4726 return (DESTReg != LHSReg);
5417} 4727 }
5418 4728
5419#endif /* MODET */ 4729#endif /* MODET */
5420 4730
5421/* This function does the work of loading a byte for a LDRB instruction. */ 4731 /* This function does the work of loading a byte for a LDRB instruction. */
5422 4732
5423static unsigned 4733 static unsigned
5424LoadByte (ARMul_State * state, ARMword instr, ARMword address, int signextend) 4734 LoadByte (ARMul_State * state, ARMword instr, ARMword address, int signextend) {
5425{ 4735 ARMword dest;
5426 ARMword dest;
5427 4736
5428 BUSUSEDINCPCS; 4737 BUSUSEDINCPCS;
5429#ifndef MODE32 4738#ifndef MODE32
5430 if (ADDREXCEPT (address)) 4739 if (ADDREXCEPT (address))
5431 INTERNALABORT (address); 4740 INTERNALABORT (address);
5432#endif 4741#endif
5433 dest = ARMul_LoadByte (state, address); 4742 dest = ARMul_LoadByte (state, address);
5434 if (state->Aborted) { 4743 if (state->Aborted) {
5435 TAKEABORT; 4744 TAKEABORT;
5436 return state->lateabtSig; 4745 return state->lateabtSig;
5437 } 4746 }
5438 UNDEF_LSRBPC; 4747 UNDEF_LSRBPC;
5439 if (signextend) 4748 if (signextend)
5440 if (dest & 1 << (8 - 1)) 4749 if (dest & 1 << (8 - 1))
5441 dest = (dest & ((1 << 8) - 1)) - (1 << 8); 4750 dest = (dest & ((1 << 8) - 1)) - (1 << 8);
5442 4751
5443 WRITEDEST (dest); 4752 WRITEDEST (dest);
5444 ARMul_Icycles (state, 1, 0L); 4753 ARMul_Icycles (state, 1, 0L);
5445 4754
5446 //MEM_LOAD_LOG("BYTE"); 4755 //MEM_LOAD_LOG("BYTE");
5447 4756
5448 return (DESTReg != LHSReg); 4757 return (DESTReg != LHSReg);
5449} 4758 }
5450 4759
5451/* This function does the work of loading two words for a LDRD instruction. */ 4760 /* This function does the work of loading two words for a LDRD instruction. */
4761
4762 static void
4763 Handle_Load_Double (ARMul_State * state, ARMword instr) {
4764 ARMword dest_reg;
4765 ARMword addr_reg;
4766 ARMword write_back = BIT (21);
4767 ARMword immediate = BIT (22);
4768 ARMword add_to_base = BIT (23);
4769 ARMword pre_indexed = BIT (24);
4770 ARMword offset;
4771 ARMword addr;
4772 ARMword sum;
4773 ARMword base;
4774 ARMword value1;
4775 ARMword value2;
4776
4777 BUSUSEDINCPCS;
4778
4779 /* If the writeback bit is set, the pre-index bit must be clear. */
4780 if (write_back && !pre_indexed) {
4781 ARMul_UndefInstr (state, instr);
4782 return;
4783 }
5452 4784
5453static void 4785 /* Extract the base address register. */
5454Handle_Load_Double (ARMul_State * state, ARMword instr) 4786 addr_reg = LHSReg;
5455{
5456 ARMword dest_reg;
5457 ARMword addr_reg;
5458 ARMword write_back = BIT (21);
5459 ARMword immediate = BIT (22);
5460 ARMword add_to_base = BIT (23);
5461 ARMword pre_indexed = BIT (24);
5462 ARMword offset;
5463 ARMword addr;
5464 ARMword sum;
5465 ARMword base;
5466 ARMword value1;
5467 ARMword value2;
5468
5469 BUSUSEDINCPCS;
5470
5471 /* If the writeback bit is set, the pre-index bit must be clear. */
5472 if (write_back && !pre_indexed) {
5473 ARMul_UndefInstr (state, instr);
5474 return;
5475 }
5476 4787
5477 /* Extract the base address register. */ 4788 /* Extract the destination register and check it. */
5478 addr_reg = LHSReg; 4789 dest_reg = DESTReg;
5479 4790
5480 /* Extract the destination register and check it. */ 4791 /* Destination register must be even. */
5481 dest_reg = DESTReg; 4792 if ((dest_reg & 1)
4793 /* Destination register cannot be LR. */
4794 || (dest_reg == 14)) {
4795 ARMul_UndefInstr (state, instr);
4796 return;
4797 }
5482 4798
5483 /* Destination register must be even. */ 4799 /* Compute the base address. */
5484 if ((dest_reg & 1) 4800 base = state->Reg[addr_reg];
5485 /* Destination register cannot be LR. */
5486 || (dest_reg == 14)) {
5487 ARMul_UndefInstr (state, instr);
5488 return;
5489 }
5490 4801
5491 /* Compute the base address. */ 4802 /* Compute the offset. */
5492 base = state->Reg[addr_reg]; 4803 offset = immediate ? ((BITS (8, 11) << 4) | BITS (0, 3)) : state->
5493 4804 Reg[RHSReg];
5494 /* Compute the offset. */
5495 offset = immediate ? ((BITS (8, 11) << 4) | BITS (0, 3)) : state->
5496 Reg[RHSReg];
5497
5498 /* Compute the sum of the two. */
5499 if (add_to_base)
5500 sum = base + offset;
5501 else
5502 sum = base - offset;
5503
5504 /* If this is a pre-indexed mode use the sum. */
5505 if (pre_indexed)
5506 addr = sum;
5507 else
5508 addr = base;
5509
5510 /* The address must be aligned on a 8 byte boundary. */
5511 // FIX(Normatt): Disable strict alignment on LDRD/STRD
5512// if (addr & 0x7) {
5513//#ifdef ABORTS
5514// ARMul_DATAABORT (addr);
5515//#else
5516// ARMul_UndefInstr (state, instr);
5517//#endif
5518// return;
5519// }
5520
5521 /* For pre indexed or post indexed addressing modes,
5522 check that the destination registers do not overlap
5523 the address registers. */
5524 if ((!pre_indexed || write_back)
5525 && (addr_reg == dest_reg || addr_reg == dest_reg + 1)) {
5526 ARMul_UndefInstr (state, instr);
5527 return;
5528 }
5529 4805
5530 /* Load the words. */ 4806 /* Compute the sum of the two. */
5531 value1 = ARMul_LoadWordN (state, addr); 4807 if (add_to_base)
5532 value2 = ARMul_LoadWordN (state, addr + 4); 4808 sum = base + offset;
4809 else
4810 sum = base - offset;
5533 4811
5534 /* Check for data aborts. */ 4812 /* If this is a pre-indexed mode use the sum. */
5535 if (state->Aborted) { 4813 if (pre_indexed)
5536 TAKEABORT; 4814 addr = sum;
5537 return; 4815 else
5538 } 4816 addr = base;
4817
4818 /* The address must be aligned on a 8 byte boundary. */
4819 /*if (addr & 0x7) {
4820 #ifdef ABORTS
4821 ARMul_DATAABORT (addr);
4822 #else
4823 ARMul_UndefInstr (state, instr);
4824 #endif
4825 return;
4826 }*/
4827 /* Lets just forcibly align it for now */
4828 //addr = (addr + 7) & ~7;
4829
4830 /* For pre indexed or post indexed addressing modes,
4831 check that the destination registers do not overlap
4832 the address registers. */
4833 if ((!pre_indexed || write_back)
4834 && (addr_reg == dest_reg || addr_reg == dest_reg + 1)) {
4835 ARMul_UndefInstr (state, instr);
4836 return;
4837 }
5539 4838
5540 ARMul_Icycles (state, 2, 0L); 4839 /* Load the words. */
4840 value1 = ARMul_LoadWordN (state, addr);
4841 value2 = ARMul_LoadWordN (state, addr + 4);
5541 4842
5542 /* Store the values. */ 4843 /* Check for data aborts. */
5543 state->Reg[dest_reg] = value1; 4844 if (state->Aborted) {
5544 state->Reg[dest_reg + 1] = value2; 4845 TAKEABORT;
4846 return;
4847 }
5545 4848
5546 /* Do the post addressing and writeback. */ 4849 ARMul_Icycles (state, 2, 0L);
5547 if (!pre_indexed)
5548 addr = sum;
5549 4850
5550 if (!pre_indexed || write_back) 4851 /* Store the values. */
5551 state->Reg[addr_reg] = addr; 4852 state->Reg[dest_reg] = value1;
5552} 4853 state->Reg[dest_reg + 1] = value2;
5553 4854
5554/* This function does the work of storing two words for a STRD instruction. */ 4855 /* Do the post addressing and writeback. */
4856 if (!pre_indexed)
4857 addr = sum;
5555 4858
5556static void 4859 if (!pre_indexed || write_back)
5557Handle_Store_Double (ARMul_State * state, ARMword instr) 4860 state->Reg[addr_reg] = addr;
5558{
5559 ARMword src_reg;
5560 ARMword addr_reg;
5561 ARMword write_back = BIT (21);
5562 ARMword immediate = BIT (22);
5563 ARMword add_to_base = BIT (23);
5564 ARMword pre_indexed = BIT (24);
5565 ARMword offset;
5566 ARMword addr;
5567 ARMword sum;
5568 ARMword base;
5569
5570 BUSUSEDINCPCS;
5571
5572 /* If the writeback bit is set, the pre-index bit must be clear. */
5573 if (write_back && !pre_indexed) {
5574 ARMul_UndefInstr (state, instr);
5575 return;
5576 } 4861 }
5577 4862
5578 /* Extract the base address register. */ 4863 /* This function does the work of storing two words for a STRD instruction. */
5579 addr_reg = LHSReg; 4864
4865 static void
4866 Handle_Store_Double (ARMul_State * state, ARMword instr) {
4867 ARMword src_reg;
4868 ARMword addr_reg;
4869 ARMword write_back = BIT (21);
4870 ARMword immediate = BIT (22);
4871 ARMword add_to_base = BIT (23);
4872 ARMword pre_indexed = BIT (24);
4873 ARMword offset;
4874 ARMword addr;
4875 ARMword sum;
4876 ARMword base;
4877
4878 BUSUSEDINCPCS;
4879
4880 /* If the writeback bit is set, the pre-index bit must be clear. */
4881 if (write_back && !pre_indexed) {
4882 ARMul_UndefInstr (state, instr);
4883 return;
4884 }
5580 4885
5581 /* Base register cannot be PC. */ 4886 /* Extract the base address register. */
5582 if (addr_reg == 15) { 4887 addr_reg = LHSReg;
5583 ARMul_UndefInstr (state, instr);
5584 return;
5585 }
5586 4888
5587 /* Extract the source register. */ 4889 /* Base register cannot be PC. */
5588 src_reg = DESTReg; 4890 if (addr_reg == 15) {
4891 ARMul_UndefInstr (state, instr);
4892 return;
4893 }
5589 4894
5590 /* Source register must be even. */ 4895 /* Extract the source register. */
5591 if (src_reg & 1) { 4896 src_reg = DESTReg;
5592 ARMul_UndefInstr (state, instr);
5593 return;
5594 }
5595 4897
5596 /* Compute the base address. */ 4898 /* Source register must be even. */
5597 base = state->Reg[addr_reg]; 4899 if (src_reg & 1) {
5598 4900 ARMul_UndefInstr (state, instr);
5599 /* Compute the offset. */ 4901 return;
5600 offset = immediate ? ((BITS (8, 11) << 4) | BITS (0, 3)) : state-> 4902 }
5601 Reg[RHSReg];
5602
5603 /* Compute the sum of the two. */
5604 if (add_to_base)
5605 sum = base + offset;
5606 else
5607 sum = base - offset;
5608
5609 /* If this is a pre-indexed mode use the sum. */
5610 if (pre_indexed)
5611 addr = sum;
5612 else
5613 addr = base;
5614
5615 /* The address must be aligned on a 8 byte boundary. */
5616 // FIX(Normatt): Disable strict alignment on LDRD/STRD
5617// if (addr & 0x7) {
5618//#ifdef ABORTS
5619// ARMul_DATAABORT (addr);
5620//#else
5621// ARMul_UndefInstr (state, instr);
5622//#endif
5623// return;
5624// }
5625
5626 /* For pre indexed or post indexed addressing modes,
5627 check that the destination registers do not overlap
5628 the address registers. */
5629 if ((!pre_indexed || write_back)
5630 && (addr_reg == src_reg || addr_reg == src_reg + 1)) {
5631 ARMul_UndefInstr (state, instr);
5632 return;
5633 }
5634 4903
5635 /* Load the words. */ 4904 /* Compute the base address. */
5636 ARMul_StoreWordN (state, addr, state->Reg[src_reg]); 4905 base = state->Reg[addr_reg];
5637 ARMul_StoreWordN (state, addr + 4, state->Reg[src_reg + 1]);
5638 4906
5639 if (state->Aborted) { 4907 /* Compute the offset. */
5640 TAKEABORT; 4908 offset = immediate ? ((BITS (8, 11) << 4) | BITS (0, 3)) : state->
5641 return; 4909 Reg[RHSReg];
5642 }
5643 4910
5644 /* Do the post addressing and writeback. */ 4911 /* Compute the sum of the two. */
5645 if (!pre_indexed) 4912 if (add_to_base)
5646 addr = sum; 4913 sum = base + offset;
4914 else
4915 sum = base - offset;
5647 4916
5648 if (!pre_indexed || write_back) 4917 /* If this is a pre-indexed mode use the sum. */
5649 state->Reg[addr_reg] = addr; 4918 if (pre_indexed)
5650} 4919 addr = sum;
4920 else
4921 addr = base;
4922
4923 /* The address must be aligned on a 8 byte boundary. */
4924 /*if (addr & 0x7) {
4925 #ifdef ABORTS
4926 ARMul_DATAABORT (addr);
4927 #else
4928 ARMul_UndefInstr (state, instr);
4929 #endif
4930 return;
4931 }*/
4932 /* Lets just forcibly align it for now */
4933 //addr = (addr + 7) & ~7;
4934
4935 /* For pre indexed or post indexed addressing modes,
4936 check that the destination registers do not overlap
4937 the address registers. */
4938 if ((!pre_indexed || write_back)
4939 && (addr_reg == src_reg || addr_reg == src_reg + 1)) {
4940 ARMul_UndefInstr (state, instr);
4941 return;
4942 }
5651 4943
5652/* This function does the work of storing a word from a STR instruction. */ 4944 /* Load the words. */
4945 ARMul_StoreWordN (state, addr, state->Reg[src_reg]);
4946 ARMul_StoreWordN (state, addr + 4, state->Reg[src_reg + 1]);
5653 4947
5654static unsigned 4948 if (state->Aborted) {
5655StoreWord (ARMul_State * state, ARMword instr, ARMword address) 4949 TAKEABORT;
5656{ 4950 return;
5657 //MEM_STORE_LOG("WORD"); 4951 }
4952
4953 /* Do the post addressing and writeback. */
4954 if (!pre_indexed)
4955 addr = sum;
4956
4957 if (!pre_indexed || write_back)
4958 state->Reg[addr_reg] = addr;
4959 }
4960
4961 /* This function does the work of storing a word from a STR instruction. */
5658 4962
5659 BUSUSEDINCPCN; 4963 static unsigned
4964 StoreWord (ARMul_State * state, ARMword instr, ARMword address) {
4965 //MEM_STORE_LOG("WORD");
4966
4967 BUSUSEDINCPCN;
5660#ifndef MODE32 4968#ifndef MODE32
5661 if (DESTReg == 15) 4969 if (DESTReg == 15)
5662 state->Reg[15] = ECC | ER15INT | R15PC | EMODE; 4970 state->Reg[15] = ECC | ER15INT | R15PC | EMODE;
5663#endif 4971#endif
5664#ifdef MODE32 4972#ifdef MODE32
5665 ARMul_StoreWordN (state, address, DEST);
5666#else
5667 if (VECTORACCESS (address) || ADDREXCEPT (address)) {
5668 INTERNALABORT (address);
5669 (void) ARMul_LoadWordN (state, address);
5670 }
5671 else
5672 ARMul_StoreWordN (state, address, DEST); 4973 ARMul_StoreWordN (state, address, DEST);
4974#else
4975 if (VECTORACCESS (address) || ADDREXCEPT (address)) {
4976 INTERNALABORT (address);
4977 (void) ARMul_LoadWordN (state, address);
4978 } else
4979 ARMul_StoreWordN (state, address, DEST);
5673#endif 4980#endif
5674 if (state->Aborted) { 4981 if (state->Aborted) {
5675 TAKEABORT; 4982 TAKEABORT;
5676 return state->lateabtSig; 4983 return state->lateabtSig;
5677 } 4984 }
5678 4985
5679 return TRUE; 4986 return TRUE;
5680} 4987 }
5681 4988
5682#ifdef MODET 4989#ifdef MODET
5683/* This function does the work of storing a byte for a STRH instruction. */ 4990 /* This function does the work of storing a byte for a STRH instruction. */
5684 4991
5685static unsigned 4992 static unsigned
5686StoreHalfWord (ARMul_State * state, ARMword instr, ARMword address) 4993 StoreHalfWord (ARMul_State * state, ARMword instr, ARMword address) {
5687{ 4994 //MEM_STORE_LOG("HALFWORD");
5688 //MEM_STORE_LOG("HALFWORD");
5689 4995
5690 BUSUSEDINCPCN; 4996 BUSUSEDINCPCN;
5691 4997
5692#ifndef MODE32 4998#ifndef MODE32
5693 if (DESTReg == 15) 4999 if (DESTReg == 15)
5694 state->Reg[15] = ECC | ER15INT | R15PC | EMODE; 5000 state->Reg[15] = ECC | ER15INT | R15PC | EMODE;
5695#endif 5001#endif
5696 5002
5697#ifdef MODE32 5003#ifdef MODE32
5698 ARMul_StoreHalfWord (state, address, DEST);
5699#else
5700 if (VECTORACCESS (address) || ADDREXCEPT (address)) {
5701 INTERNALABORT (address);
5702 (void) ARMul_LoadHalfWord (state, address);
5703 }
5704 else
5705 ARMul_StoreHalfWord (state, address, DEST); 5004 ARMul_StoreHalfWord (state, address, DEST);
5005#else
5006 if (VECTORACCESS (address) || ADDREXCEPT (address)) {
5007 INTERNALABORT (address);
5008 (void) ARMul_LoadHalfWord (state, address);
5009 } else
5010 ARMul_StoreHalfWord (state, address, DEST);
5706#endif 5011#endif
5707 5012
5708 if (state->Aborted) { 5013 if (state->Aborted) {
5709 TAKEABORT; 5014 TAKEABORT;
5710 return state->lateabtSig; 5015 return state->lateabtSig;
5016 }
5017 return TRUE;
5711 } 5018 }
5712 return TRUE;
5713}
5714 5019
5715#endif /* MODET */ 5020#endif /* MODET */
5716 5021
5717/* This function does the work of storing a byte for a STRB instruction. */ 5022 /* This function does the work of storing a byte for a STRB instruction. */
5718 5023
5719static unsigned 5024 static unsigned
5720StoreByte (ARMul_State * state, ARMword instr, ARMword address) 5025 StoreByte (ARMul_State * state, ARMword instr, ARMword address) {
5721{ 5026 //MEM_STORE_LOG("BYTE");
5722 //MEM_STORE_LOG("BYTE");
5723 5027
5724 BUSUSEDINCPCN; 5028 BUSUSEDINCPCN;
5725#ifndef MODE32 5029#ifndef MODE32
5726 if (DESTReg == 15) 5030 if (DESTReg == 15)
5727 state->Reg[15] = ECC | ER15INT | R15PC | EMODE; 5031 state->Reg[15] = ECC | ER15INT | R15PC | EMODE;
5728#endif 5032#endif
5729#ifdef MODE32 5033#ifdef MODE32
5730 ARMul_StoreByte (state, address, DEST);
5731#else
5732 if (VECTORACCESS (address) || ADDREXCEPT (address)) {
5733 INTERNALABORT (address);
5734 (void) ARMul_LoadByte (state, address);
5735 }
5736 else
5737 ARMul_StoreByte (state, address, DEST); 5034 ARMul_StoreByte (state, address, DEST);
5035#else
5036 if (VECTORACCESS (address) || ADDREXCEPT (address)) {
5037 INTERNALABORT (address);
5038 (void) ARMul_LoadByte (state, address);
5039 } else
5040 ARMul_StoreByte (state, address, DEST);
5738#endif 5041#endif
5739 if (state->Aborted) { 5042 if (state->Aborted) {
5740 TAKEABORT; 5043 TAKEABORT;
5741 return state->lateabtSig; 5044 return state->lateabtSig;
5045 }
5046 //UNDEF_LSRBPC;
5047 return TRUE;
5742 } 5048 }
5743 //UNDEF_LSRBPC;
5744 return TRUE;
5745}
5746 5049
5747/* This function does the work of loading the registers listed in an LDM 5050 /* This function does the work of loading the registers listed in an LDM
5748 instruction, when the S bit is clear. The code here is always increment 5051 instruction, when the S bit is clear. The code here is always increment
5749 after, it's up to the caller to get the input address correct and to 5052 after, it's up to the caller to get the input address correct and to
5750 handle base register modification. */ 5053 handle base register modification. */
5751 5054
5752static void 5055 static void
5753LoadMult (ARMul_State * state, ARMword instr, ARMword address, ARMword WBBase) 5056 LoadMult (ARMul_State * state, ARMword instr, ARMword address, ARMword WBBase) {
5754{ 5057 ARMword dest, temp;
5755 ARMword dest, temp;
5756 5058
5757 //UNDEF_LSMNoRegs; 5059 //UNDEF_LSMNoRegs;
5758 //UNDEF_LSMPCBase; 5060 //UNDEF_LSMPCBase;
5759 //UNDEF_LSMBaseInListWb; 5061 //UNDEF_LSMBaseInListWb;
5760 BUSUSEDINCPCS; 5062 BUSUSEDINCPCS;
5761#ifndef MODE32 5063#ifndef MODE32
5762 if (ADDREXCEPT (address)) 5064 if (ADDREXCEPT (address))
5763 INTERNALABORT (address); 5065 INTERNALABORT (address);
5764#endif 5066#endif
5765/*chy 2004-05-23 may write twice 5067 /*chy 2004-05-23 may write twice
5766 if (BIT (21) && LHSReg != 15) 5068 if (BIT (21) && LHSReg != 15)
5767 LSBase = WBBase; 5069 LSBase = WBBase;
5768*/ 5070 */
5769 /* N cycle first. */ 5071 /* N cycle first. */
5770 for (temp = 0; !BIT (temp); temp++); 5072 for (temp = 0; !BIT (temp); temp++);
5771 5073
5772 dest = ARMul_LoadWordN (state, address); 5074 dest = ARMul_LoadWordN (state, address);
5075
5076 if (!state->abortSig && !state->Aborted)
5077 state->Reg[temp++] = dest;
5078 else if (!state->Aborted) {
5079 //XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address);
5080 state->Aborted = ARMul_DataAbortV;
5081 }
5082 /*chy 2004-05-23 chy goto end*/
5083 if (state->Aborted)
5084 goto L_ldm_makeabort;
5085 /* S cycles from here on. */
5086 for (; temp < 16; temp++)
5087 if (BIT (temp)) {
5088 /* Load this register. */
5089 address += 4;
5090 dest = ARMul_LoadWordS (state, address);
5091
5092 if (!state->abortSig && !state->Aborted)
5093 state->Reg[temp] = dest;
5094 else if (!state->Aborted) {
5095 /*XScale_set_fsr_far (state,
5096 ARMul_CP15_R5_ST_ALIGN,
5097 address);*/
5098 state->Aborted = ARMul_DataAbortV;
5099 }
5100 /*chy 2004-05-23 chy goto end */
5101 if (state->Aborted)
5102 goto L_ldm_makeabort;
5773 5103
5774 if (!state->abortSig && !state->Aborted)
5775 state->Reg[temp++] = dest;
5776 else if (!state->Aborted) {
5777 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address);
5778 state->Aborted = ARMul_DataAbortV;
5779 }
5780/*chy 2004-05-23 chy goto end*/
5781 if (state->Aborted)
5782 goto L_ldm_makeabort;
5783 /* S cycles from here on. */
5784 for (; temp < 16; temp++)
5785 if (BIT (temp)) {
5786 /* Load this register. */
5787 address += 4;
5788 dest = ARMul_LoadWordS (state, address);
5789
5790 if (!state->abortSig && !state->Aborted)
5791 state->Reg[temp] = dest;
5792 else if (!state->Aborted) {
5793 XScale_set_fsr_far (state,
5794 ARMul_CP15_R5_ST_ALIGN,
5795 address);
5796 state->Aborted = ARMul_DataAbortV;
5797 } 5104 }
5798 /*chy 2004-05-23 chy goto end */
5799 if (state->Aborted)
5800 goto L_ldm_makeabort;
5801 5105
5802 } 5106 if (BIT (15) && !state->Aborted)
5107 /* PC is in the reg list. */
5108 WriteR15Branch (state, PC);
5803 5109
5804 if (BIT (15) && !state->Aborted) 5110 /* To write back the final register. */
5805 /* PC is in the reg list. */ 5111 /* ARMul_Icycles (state, 1, 0L);*/
5806 WriteR15Branch(state, (state->Reg[15] & PCMASK)); 5112 /*chy 2004-05-23, see below
5113 if (state->Aborted)
5114 {
5115 if (BIT (21) && LHSReg != 15)
5116 LSBase = WBBase;
5807 5117
5808 /* To write back the final register. */ 5118 TAKEABORT;
5809/* ARMul_Icycles (state, 1, 0L);*/ 5119 }
5810/*chy 2004-05-23, see below 5120 */
5811 if (state->Aborted) 5121 /*chy 2004-05-23 should compare the Abort Models*/
5812 { 5122L_ldm_makeabort:
5813 if (BIT (21) && LHSReg != 15) 5123 /* To write back the final register. */
5814 LSBase = WBBase; 5124 ARMul_Icycles (state, 1, 0L);
5815 5125
5816 TAKEABORT; 5126 /* chy 2005-11-24, bug found by benjl@cse.unsw.edu.au, etc */
5817 } 5127 /*
5818*/ 5128 if (state->Aborted)
5819/*chy 2004-05-23 should compare the Abort Models*/ 5129 {
5820 L_ldm_makeabort: 5130 if (BIT (21) && LHSReg != 15)
5821 /* To write back the final register. */ 5131 if (!(state->abortSig && state->Aborted && state->lateabtSig == LOW))
5822 ARMul_Icycles (state, 1, 0L); 5132 LSBase = WBBase;
5823 5133 TAKEABORT;
5824 /* chy 2005-11-24, bug found by benjl@cse.unsw.edu.au, etc */ 5134 }else if (BIT (21) && LHSReg != 15)
5825 /* 5135 LSBase = WBBase;
5826 if (state->Aborted) 5136 */
5827 { 5137 if (state->Aborted) {
5828 if (BIT (21) && LHSReg != 15) 5138 if (BIT (21) && LHSReg != 15) {
5829 if (!(state->abortSig && state->Aborted && state->lateabtSig == LOW)) 5139 if (!(state->abortSig)) {
5830 LSBase = WBBase; 5140 }
5831 TAKEABORT;
5832 }else if (BIT (21) && LHSReg != 15)
5833 LSBase = WBBase;
5834 */
5835 if (state->Aborted) {
5836 if (BIT (21) && LHSReg != 15) {
5837 if (!(state->abortSig)) {
5838 } 5141 }
5142 TAKEABORT;
5143 } else if (BIT (21) && LHSReg != 15) {
5144 LSBase = WBBase;
5839 } 5145 }
5840 TAKEABORT; 5146 /* chy 2005-11-24, over */
5841 } 5147
5842 else if (BIT (21) && LHSReg != 15) {
5843 LSBase = WBBase;
5844 } 5148 }
5845 /* chy 2005-11-24, over */
5846 5149
5847} 5150 /* This function does the work of loading the registers listed in an LDM
5151 instruction, when the S bit is set. The code here is always increment
5152 after, it's up to the caller to get the input address correct and to
5153 handle base register modification. */
5848 5154
5849/* This function does the work of loading the registers listed in an LDM 5155 static void
5850 instruction, when the S bit is set. The code here is always increment 5156 LoadSMult (ARMul_State * state,
5851 after, it's up to the caller to get the input address correct and to 5157 ARMword instr, ARMword address, ARMword WBBase) {
5852 handle base register modification. */ 5158 ARMword dest, temp;
5853 5159
5854static void 5160 //UNDEF_LSMNoRegs;
5855LoadSMult (ARMul_State * state, 5161 //UNDEF_LSMPCBase;
5856 ARMword instr, ARMword address, ARMword WBBase) 5162 //UNDEF_LSMBaseInListWb;
5857{
5858 ARMword dest, temp;
5859 5163
5860 //UNDEF_LSMNoRegs; 5164 BUSUSEDINCPCS;
5861 //UNDEF_LSMPCBase;
5862 //UNDEF_LSMBaseInListWb;
5863
5864 BUSUSEDINCPCS;
5865 5165
5866#ifndef MODE32 5166#ifndef MODE32
5867 if (ADDREXCEPT (address)) 5167 if (ADDREXCEPT (address))
5868 INTERNALABORT (address); 5168 INTERNALABORT (address);
5869#endif 5169#endif
5870/* chy 2004-05-23, may write twice 5170 /* chy 2004-05-23, may write twice
5871 if (BIT (21) && LHSReg != 15) 5171 if (BIT (21) && LHSReg != 15)
5872 LSBase = WBBase; 5172 LSBase = WBBase;
5873*/ 5173 */
5874 if (!BIT (15) && state->Bank != USERBANK) { 5174 if (!BIT (15) && state->Bank != USERBANK) {
5875 /* Temporary reg bank switch. */ 5175 /* Temporary reg bank switch. */
5876 (void) ARMul_SwitchMode (state, state->Mode, USER26MODE); 5176 (void) ARMul_SwitchMode (state, state->Mode, USER26MODE);
5877 UNDEF_LSMUserBankWb; 5177 UNDEF_LSMUserBankWb;
5878 } 5178 }
5879 5179
5880 /* N cycle first. */ 5180 /* N cycle first. */
5881 for (temp = 0; !BIT (temp); temp++); 5181 for (temp = 0; !BIT (temp); temp++);
5882 5182
5883 dest = ARMul_LoadWordN (state, address); 5183 dest = ARMul_LoadWordN (state, address);
5884 5184
5885 if (!state->abortSig) 5185 if (!state->abortSig)
5886 state->Reg[temp++] = dest; 5186 state->Reg[temp++] = dest;
5887 else if (!state->Aborted) { 5187 else if (!state->Aborted) {
5888 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); 5188 //XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address);
5889 state->Aborted = ARMul_DataAbortV; 5189 state->Aborted = ARMul_DataAbortV;
5890 } 5190 }
5891 5191
5892/*chy 2004-05-23 chy goto end*/ 5192 /*chy 2004-05-23 chy goto end*/
5893 if (state->Aborted) 5193 if (state->Aborted)
5894 goto L_ldm_s_makeabort; 5194 goto L_ldm_s_makeabort;
5895 /* S cycles from here on. */ 5195 /* S cycles from here on. */
5896 for (; temp < 16; temp++) 5196 for (; temp < 16; temp++)
5897 if (BIT (temp)) { 5197 if (BIT (temp)) {
5898 /* Load this register. */ 5198 /* Load this register. */
5899 address += 4; 5199 address += 4;
5900 dest = ARMul_LoadWordS (state, address); 5200 dest = ARMul_LoadWordS (state, address);
5901 5201
5902 if (!state->abortSig && !state->Aborted) 5202 if (!state->abortSig && !state->Aborted)
5903 state->Reg[temp] = dest; 5203 state->Reg[temp] = dest;
5904 else if (!state->Aborted) { 5204 else if (!state->Aborted) {
5905 XScale_set_fsr_far (state, 5205 /*XScale_set_fsr_far (state,
5906 ARMul_CP15_R5_ST_ALIGN, 5206 ARMul_CP15_R5_ST_ALIGN,
5907 address); 5207 address);*/
5908 state->Aborted = ARMul_DataAbortV; 5208 state->Aborted = ARMul_DataAbortV;
5209 }
5210 /*chy 2004-05-23 chy goto end */
5211 if (state->Aborted)
5212 goto L_ldm_s_makeabort;
5909 } 5213 }
5910 /*chy 2004-05-23 chy goto end */
5911 if (state->Aborted)
5912 goto L_ldm_s_makeabort;
5913 }
5914 5214
5915/*chy 2004-05-23 label of ldm_s_makeabort*/ 5215 /*chy 2004-05-23 label of ldm_s_makeabort*/
5916 L_ldm_s_makeabort: 5216L_ldm_s_makeabort:
5917/*chy 2004-06-06 LSBase process should be here, not in the end of this function. Because ARMul_CPSRAltered maybe change R13(SP) R14(lr). If not, simulate INSTR ldmia sp!,[....pc]^ error.*/ 5217 /*chy 2004-06-06 LSBase process should be here, not in the end of this function. Because ARMul_CPSRAltered maybe change R13(SP) R14(lr). If not, simulate INSTR ldmia sp!,[....pc]^ error.*/
5918/*chy 2004-05-23 should compare the Abort Models*/ 5218 /*chy 2004-05-23 should compare the Abort Models*/
5919 if (state->Aborted) { 5219 if (state->Aborted) {
5920 if (BIT (21) && LHSReg != 15) 5220 if (BIT (21) && LHSReg != 15)
5921 if (! 5221 if (!
5922 (state->abortSig && state->Aborted 5222 (state->abortSig && state->Aborted
5923 && state->lateabtSig == LOW)) 5223 && state->lateabtSig == LOW))
5924 LSBase = WBBase; 5224 LSBase = WBBase;
5925 TAKEABORT; 5225 TAKEABORT;
5926 } 5226 } else if (BIT (21) && LHSReg != 15)
5927 else if (BIT (21) && LHSReg != 15) 5227 LSBase = WBBase;
5928 LSBase = WBBase;
5929 5228
5930 if (BIT (15) && !state->Aborted) { 5229 if (BIT (15) && !state->Aborted) {
5931 /* PC is in the reg list. */ 5230 /* PC is in the reg list. */
5932#ifdef MODE32 5231#ifdef MODE32
5933 //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode 5232 //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode
5934 if (state->Mode != USER26MODE && state->Mode != USER32MODE ){ 5233 if (state->Mode != USER26MODE && state->Mode != USER32MODE ) {
5935 state->Cpsr = GETSPSR (state->Bank); 5234 state->Cpsr = GETSPSR (state->Bank);
5936 ARMul_CPSRAltered (state); 5235 //ARMul_CPSRAltered (state);
5937 } 5236 }
5938 5237
5939 WriteR15 (state, (state->Reg[15] & PCMASK)); 5238 WriteR15 (state, PC);
5940#else 5239#else
5941 //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode 5240 //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode
5942 if (state->Mode == USER26MODE || state->Mode == USER32MODE ) { 5241 if (state->Mode == USER26MODE || state->Mode == USER32MODE ) {
5943 /* Protect bits in user mode. */ 5242 /* Protect bits in user mode. */
5944 ASSIGNN ((state->Reg[15] & NBIT) != 0); 5243 ASSIGNN ((state->Reg[15] & NBIT) != 0);
5945 ASSIGNZ ((state->Reg[15] & ZBIT) != 0); 5244 ASSIGNZ ((state->Reg[15] & ZBIT) != 0);
5946 ASSIGNC ((state->Reg[15] & CBIT) != 0); 5245 ASSIGNC ((state->Reg[15] & CBIT) != 0);
5947 ASSIGNV ((state->Reg[15] & VBIT) != 0); 5246 ASSIGNV ((state->Reg[15] & VBIT) != 0);
5247 } else
5248 ARMul_R15Altered (state);
5249
5250 FLUSHPIPE;
5251#endif
5948 } 5252 }
5949 else
5950 ARMul_R15Altered (state);
5951 5253
5952 FLUSHPIPE; 5254 //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode
5953#endif 5255 if (!BIT (15) && state->Mode != USER26MODE
5954 } 5256 && state->Mode != USER32MODE )
5257 /* Restore the correct bank. */
5258 (void) ARMul_SwitchMode (state, USER26MODE, state->Mode);
5955 5259
5956 //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode 5260 /* To write back the final register. */
5957 if (!BIT (15) && state->Mode != USER26MODE 5261 ARMul_Icycles (state, 1, 0L);
5958 && state->Mode != USER32MODE ) 5262 /* chy 2004-05-23, see below
5959 /* Restore the correct bank. */ 5263 if (state->Aborted)
5960 (void) ARMul_SwitchMode (state, USER26MODE, state->Mode); 5264 {
5961 5265 if (BIT (21) && LHSReg != 15)
5962 /* To write back the final register. */ 5266 LSBase = WBBase;
5963 ARMul_Icycles (state, 1, 0L);
5964/* chy 2004-05-23, see below
5965 if (state->Aborted)
5966 {
5967 if (BIT (21) && LHSReg != 15)
5968 LSBase = WBBase;
5969 5267
5970 TAKEABORT; 5268 TAKEABORT;
5269 }
5270 */
5971 } 5271 }
5972*/
5973}
5974 5272
5975/* This function does the work of storing the registers listed in an STM 5273 /* This function does the work of storing the registers listed in an STM
5976 instruction, when the S bit is clear. The code here is always increment 5274 instruction, when the S bit is clear. The code here is always increment
5977 after, it's up to the caller to get the input address correct and to 5275 after, it's up to the caller to get the input address correct and to
5978 handle base register modification. */ 5276 handle base register modification. */
5979 5277
5980static void 5278 static void
5981StoreMult (ARMul_State * state, 5279 StoreMult (ARMul_State * state,
5982 ARMword instr, ARMword address, ARMword WBBase) 5280 ARMword instr, ARMword address, ARMword WBBase) {
5983{ 5281 ARMword temp;
5984 ARMword temp;
5985 5282
5986 UNDEF_LSMNoRegs; 5283 UNDEF_LSMNoRegs;
5987 UNDEF_LSMPCBase; 5284 UNDEF_LSMPCBase;
5988 UNDEF_LSMBaseInListWb; 5285 UNDEF_LSMBaseInListWb;
5989 5286
5990 if (!TFLAG) 5287 if (!TFLAG)
5991 /* N-cycle, increment the PC and update the NextInstr state. */ 5288 /* N-cycle, increment the PC and update the NextInstr state. */
5992 BUSUSEDINCPCN; 5289 BUSUSEDINCPCN;
5993 5290
5994#ifndef MODE32 5291#ifndef MODE32
5995 if (VECTORACCESS (address) || ADDREXCEPT (address)) 5292 if (VECTORACCESS (address) || ADDREXCEPT (address))
5996 INTERNALABORT (address); 5293 INTERNALABORT (address);
5997 5294
5998 if (BIT (15)) 5295 if (BIT (15))
5999 PATCHR15; 5296 PATCHR15;
6000#endif 5297#endif
6001 5298
6002 /* N cycle first. */ 5299 /* N cycle first. */
6003 for (temp = 0; !BIT (temp); temp++); 5300 for (temp = 0; !BIT (temp); temp++);
6004 5301
6005#ifdef MODE32 5302#ifdef MODE32
6006 ARMul_StoreWordN (state, address, state->Reg[temp++]); 5303 ARMul_StoreWordN (state, address, state->Reg[temp++]);
6007#else 5304#else
6008 if (state->Aborted) { 5305 if (state->Aborted) {
6009 (void) ARMul_LoadWordN (state, address); 5306 (void) ARMul_LoadWordN (state, address);
6010 5307
6011 /* Fake the Stores as Loads. */ 5308 /* Fake the Stores as Loads. */
5309 for (; temp < 16; temp++)
5310 if (BIT (temp)) {
5311 /* Save this register. */
5312 address += 4;
5313 (void) ARMul_LoadWordS (state, address);
5314 }
5315
5316 if (BIT (21) && LHSReg != 15)
5317 LSBase = WBBase;
5318 TAKEABORT;
5319 return;
5320 } else
5321 ARMul_StoreWordN (state, address, state->Reg[temp++]);
5322#endif
5323
5324 if (state->abortSig && !state->Aborted) {
5325 //XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address);
5326 state->Aborted = ARMul_DataAbortV;
5327 }
5328
5329//chy 2004-05-23, needn't store other when aborted
5330 if (state->Aborted)
5331 goto L_stm_takeabort;
5332
5333 /* S cycles from here on. */
6012 for (; temp < 16; temp++) 5334 for (; temp < 16; temp++)
6013 if (BIT (temp)) { 5335 if (BIT (temp)) {
6014 /* Save this register. */ 5336 /* Save this register. */
6015 address += 4; 5337 address += 4;
6016 (void) ARMul_LoadWordS (state, address);
6017 }
6018 5338
6019 if (BIT (21) && LHSReg != 15) 5339 ARMul_StoreWordS (state, address, state->Reg[temp]);
6020 LSBase = WBBase;
6021 TAKEABORT;
6022 return;
6023 }
6024 else
6025 ARMul_StoreWordN (state, address, state->Reg[temp++]);
6026#endif
6027 5340
6028 if (state->abortSig && !state->Aborted) { 5341 if (state->abortSig && !state->Aborted) {
6029 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); 5342 /*XScale_set_fsr_far (state,
6030 state->Aborted = ARMul_DataAbortV; 5343 ARMul_CP15_R5_ST_ALIGN,
6031 } 5344 address);*/
5345 state->Aborted = ARMul_DataAbortV;
5346 }
5347 //chy 2004-05-23, needn't store other when aborted
5348 if (state->Aborted)
5349 goto L_stm_takeabort;
6032 5350
6033//chy 2004-05-23, needn't store other when aborted
6034 if (state->Aborted)
6035 goto L_stm_takeabort;
6036
6037 /* S cycles from here on. */
6038 for (; temp < 16; temp++)
6039 if (BIT (temp)) {
6040 /* Save this register. */
6041 address += 4;
6042
6043 ARMul_StoreWordS (state, address, state->Reg[temp]);
6044
6045 if (state->abortSig && !state->Aborted) {
6046 XScale_set_fsr_far (state,
6047 ARMul_CP15_R5_ST_ALIGN,
6048 address);
6049 state->Aborted = ARMul_DataAbortV;
6050 } 5351 }
6051 //chy 2004-05-23, needn't store other when aborted
6052 if (state->Aborted)
6053 goto L_stm_takeabort;
6054
6055 }
6056 5352
6057//chy 2004-05-23,should compare the Abort Models 5353//chy 2004-05-23,should compare the Abort Models
6058 L_stm_takeabort: 5354L_stm_takeabort:
6059 if (BIT (21) && LHSReg != 15) { 5355 if (BIT (21) && LHSReg != 15) {
6060 if (! 5356 if (!
6061 (state->abortSig && state->Aborted 5357 (state->abortSig && state->Aborted
6062 && state->lateabtSig == LOW)) 5358 && state->lateabtSig == LOW))
6063 LSBase = WBBase; 5359 LSBase = WBBase;
5360 }
5361 if (state->Aborted)
5362 TAKEABORT;
6064 } 5363 }
6065 if (state->Aborted)
6066 TAKEABORT;
6067}
6068 5364
6069/* This function does the work of storing the registers listed in an STM 5365 /* This function does the work of storing the registers listed in an STM
6070 instruction when the S bit is set. The code here is always increment 5366 instruction when the S bit is set. The code here is always increment
6071 after, it's up to the caller to get the input address correct and to 5367 after, it's up to the caller to get the input address correct and to
6072 handle base register modification. */ 5368 handle base register modification. */
6073 5369
6074static void 5370 static void
6075StoreSMult (ARMul_State * state, 5371 StoreSMult (ARMul_State * state,
6076 ARMword instr, ARMword address, ARMword WBBase) 5372 ARMword instr, ARMword address, ARMword WBBase) {
6077{ 5373 ARMword temp;
6078 ARMword temp;
6079 5374
6080 UNDEF_LSMNoRegs; 5375 UNDEF_LSMNoRegs;
6081 UNDEF_LSMPCBase; 5376 UNDEF_LSMPCBase;
6082 UNDEF_LSMBaseInListWb; 5377 UNDEF_LSMBaseInListWb;
6083 5378
6084 BUSUSEDINCPCN; 5379 BUSUSEDINCPCN;
6085 5380
6086#ifndef MODE32 5381#ifndef MODE32
6087 if (VECTORACCESS (address) || ADDREXCEPT (address)) 5382 if (VECTORACCESS (address) || ADDREXCEPT (address))
6088 INTERNALABORT (address); 5383 INTERNALABORT (address);
6089 5384
6090 if (BIT (15)) 5385 if (BIT (15))
6091 PATCHR15; 5386 PATCHR15;
6092#endif 5387#endif
6093 5388
6094 if (state->Bank != USERBANK) { 5389 if (state->Bank != USERBANK) {
6095 /* Force User Bank. */ 5390 /* Force User Bank. */
6096 (void) ARMul_SwitchMode (state, state->Mode, USER26MODE); 5391 (void) ARMul_SwitchMode (state, state->Mode, USER26MODE);
6097 UNDEF_LSMUserBankWb; 5392 UNDEF_LSMUserBankWb;
6098 } 5393 }
6099 5394
6100 for (temp = 0; !BIT (temp); temp++); /* N cycle first. */ 5395 for (temp = 0; !BIT (temp); temp++); /* N cycle first. */
6101 5396
6102#ifdef MODE32 5397#ifdef MODE32
6103 ARMul_StoreWordN (state, address, state->Reg[temp++]); 5398 ARMul_StoreWordN (state, address, state->Reg[temp++]);
6104#else 5399#else
6105 if (state->Aborted) { 5400 if (state->Aborted) {
6106 (void) ARMul_LoadWordN (state, address); 5401 (void) ARMul_LoadWordN (state, address);
5402
5403 for (; temp < 16; temp++)
5404 /* Fake the Stores as Loads. */
5405 if (BIT (temp)) {
5406 /* Save this register. */
5407 address += 4;
5408
5409 (void) ARMul_LoadWordS (state, address);
5410 }
5411
5412 if (BIT (21) && LHSReg != 15)
5413 LSBase = WBBase;
6107 5414
5415 TAKEABORT;
5416 return;
5417 } else
5418 ARMul_StoreWordN (state, address, state->Reg[temp++]);
5419#endif
5420
5421 if (state->abortSig && !state->Aborted) {
5422 //XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address);
5423 state->Aborted = ARMul_DataAbortV;
5424 }
5425
5426//chy 2004-05-23, needn't store other when aborted
5427 if (state->Aborted)
5428 goto L_stm_s_takeabort;
5429 /* S cycles from here on. */
6108 for (; temp < 16; temp++) 5430 for (; temp < 16; temp++)
6109 /* Fake the Stores as Loads. */
6110 if (BIT (temp)) { 5431 if (BIT (temp)) {
6111 /* Save this register. */ 5432 /* Save this register. */
6112 address += 4; 5433 address += 4;
6113 5434
6114 (void) ARMul_LoadWordS (state, address); 5435 ARMul_StoreWordS (state, address, state->Reg[temp]);
5436
5437 if (state->abortSig && !state->Aborted) {
5438 /*XScale_set_fsr_far (state,
5439 ARMul_CP15_R5_ST_ALIGN,
5440 address);*/
5441 state->Aborted = ARMul_DataAbortV;
5442 }
5443 //chy 2004-05-23, needn't store other when aborted
5444 if (state->Aborted)
5445 goto L_stm_s_takeabort;
6115 } 5446 }
6116 5447
6117 if (BIT (21) && LHSReg != 15) 5448 //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode
6118 LSBase = WBBase; 5449 if (state->Mode != USER26MODE && state->Mode != USER32MODE )
5450 /* Restore the correct bank. */
5451 (void) ARMul_SwitchMode (state, USER26MODE, state->Mode);
5452
5453
5454//chy 2004-05-23,should compare the Abort Models
5455L_stm_s_takeabort:
5456 if (BIT (21) && LHSReg != 15) {
5457 if (!
5458 (state->abortSig && state->Aborted
5459 && state->lateabtSig == LOW))
5460 LSBase = WBBase;
5461 }
6119 5462
6120 TAKEABORT; 5463 if (state->Aborted)
6121 return; 5464 TAKEABORT;
6122 } 5465 }
6123 else
6124 ARMul_StoreWordN (state, address, state->Reg[temp++]);
6125#endif
6126 5466
6127 if (state->abortSig && !state->Aborted) { 5467 /* This function does the work of adding two 32bit values
6128 XScale_set_fsr_far (state, ARMul_CP15_R5_ST_ALIGN, address); 5468 together, and calculating if a carry has occurred. */
6129 state->Aborted = ARMul_DataAbortV; 5469
5470 static ARMword
5471 Add32 (ARMword a1, ARMword a2, int *carry) {
5472 ARMword result = (a1 + a2);
5473 unsigned int uresult = (unsigned int) result;
5474 unsigned int ua1 = (unsigned int) a1;
5475
5476 /* If (result == RdLo) and (state->Reg[nRdLo] == 0),
5477 or (result > RdLo) then we have no carry. */
5478 if ((uresult == ua1) ? (a2 != 0) : (uresult < ua1))
5479 *carry = 1;
5480 else
5481 *carry = 0;
5482
5483 return result;
6130 } 5484 }
6131 5485
6132//chy 2004-05-23, needn't store other when aborted 5486 /* This function does the work of multiplying
6133 if (state->Aborted) 5487 two 32bit values to give a 64bit result. */
6134 goto L_stm_s_takeabort; 5488
6135 /* S cycles from here on. */ 5489 static unsigned
6136 for (; temp < 16; temp++) 5490 Multiply64 (ARMul_State * state, ARMword instr, int msigned, int scc) {
6137 if (BIT (temp)) { 5491 /* Operand register numbers. */
6138 /* Save this register. */ 5492 int nRdHi, nRdLo, nRs, nRm;
6139 address += 4; 5493 ARMword RdHi = 0, RdLo = 0, Rm;
6140 5494 /* Cycle count. */
6141 ARMul_StoreWordS (state, address, state->Reg[temp]); 5495 int scount;
6142 5496
6143 if (state->abortSig && !state->Aborted) { 5497 nRdHi = BITS (16, 19);
6144 XScale_set_fsr_far (state, 5498 nRdLo = BITS (12, 15);
6145 ARMul_CP15_R5_ST_ALIGN, 5499 nRs = BITS (8, 11);
6146 address); 5500 nRm = BITS (0, 3);
6147 state->Aborted = ARMul_DataAbortV; 5501
5502 /* Needed to calculate the cycle count. */
5503 Rm = state->Reg[nRm];
5504
5505 /* Check for illegal operand combinations first. */
5506 if (nRdHi != 15
5507 && nRdLo != 15
5508 && nRs != 15
5509 //&& nRm != 15 && nRdHi != nRdLo && nRdHi != nRm && nRdLo != nRm) {
5510 && nRm != 15 && nRdHi != nRdLo ) {
5511 /* Intermediate results. */
5512 ARMword lo, mid1, mid2, hi;
5513 int carry;
5514 ARMword Rs = state->Reg[nRs];
5515 int sign = 0;
5516
5517 if (msigned) {
5518 /* Compute sign of result and adjust operands if necessary. */
5519 sign = (Rm ^ Rs) & 0x80000000;
5520
5521 if (((signed int) Rm) < 0)
5522 Rm = -Rm;
5523
5524 if (((signed int) Rs) < 0)
5525 Rs = -Rs;
6148 } 5526 }
6149 //chy 2004-05-23, needn't store other when aborted
6150 if (state->Aborted)
6151 goto L_stm_s_takeabort;
6152 }
6153 5527
6154 //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode 5528 /* We can split the 32x32 into four 16x16 operations. This
6155 if (state->Mode != USER26MODE && state->Mode != USER32MODE ) 5529 ensures that we do not lose precision on 32bit only hosts. */
6156 /* Restore the correct bank. */ 5530 lo = ((Rs & 0xFFFF) * (Rm & 0xFFFF));
6157 (void) ARMul_SwitchMode (state, USER26MODE, state->Mode); 5531 mid1 = ((Rs & 0xFFFF) * ((Rm >> 16) & 0xFFFF));
5532 mid2 = (((Rs >> 16) & 0xFFFF) * (Rm & 0xFFFF));
5533 hi = (((Rs >> 16) & 0xFFFF) * ((Rm >> 16) & 0xFFFF));
5534
5535 /* We now need to add all of these results together, taking
5536 care to propogate the carries from the additions. */
5537 RdLo = Add32 (lo, (mid1 << 16), &carry);
5538 RdHi = carry;
5539 RdLo = Add32 (RdLo, (mid2 << 16), &carry);
5540 RdHi += (carry + ((mid1 >> 16) & 0xFFFF) +
5541 ((mid2 >> 16) & 0xFFFF) + hi);
5542
5543 if (sign) {
5544 /* Negate result if necessary. */
5545 RdLo = ~RdLo;
5546 RdHi = ~RdHi;
5547 if (RdLo == 0xFFFFFFFF) {
5548 RdLo = 0;
5549 RdHi += 1;
5550 } else
5551 RdLo += 1;
5552 }
6158 5553
5554 state->Reg[nRdLo] = RdLo;
5555 state->Reg[nRdHi] = RdHi;
5556 } else {
5557 fprintf (stderr, "sim: MULTIPLY64 - INVALID ARGUMENTS, instr=0x%x\n", instr);
5558 }
5559 if (scc)
5560 /* Ensure that both RdHi and RdLo are used to compute Z,
5561 but don't let RdLo's sign bit make it to N. */
5562 ARMul_NegZero (state, RdHi | (RdLo >> 16) | (RdLo & 0xFFFF));
5563
5564 /* The cycle count depends on whether the instruction is a signed or
5565 unsigned multiply, and what bits are clear in the multiplier. */
5566 if (msigned && (Rm & ((unsigned) 1 << 31)))
5567 /* Invert the bits to make the check against zero. */
5568 Rm = ~Rm;
5569
5570 if ((Rm & 0xFFFFFF00) == 0)
5571 scount = 1;
5572 else if ((Rm & 0xFFFF0000) == 0)
5573 scount = 2;
5574 else if ((Rm & 0xFF000000) == 0)
5575 scount = 3;
5576 else
5577 scount = 4;
6159 5578
6160//chy 2004-05-23,should compare the Abort Models 5579 return 2 + scount;
6161 L_stm_s_takeabort:
6162 if (BIT (21) && LHSReg != 15) {
6163 if (!
6164 (state->abortSig && state->Aborted
6165 && state->lateabtSig == LOW))
6166 LSBase = WBBase;
6167 } 5580 }
6168 5581
6169 if (state->Aborted) 5582 /* This function does the work of multiplying two 32bit
6170 TAKEABORT; 5583 values and adding a 64bit value to give a 64bit result. */
6171}
6172 5584
6173/* This function does the work of adding two 32bit values 5585 static unsigned
6174 together, and calculating if a carry has occurred. */ 5586 MultiplyAdd64 (ARMul_State * state, ARMword instr, int msigned, int scc) {
5587 unsigned scount;
5588 ARMword RdLo, RdHi;
5589 int nRdHi, nRdLo;
5590 int carry = 0;
6175 5591
6176static ARMword 5592 nRdHi = BITS (16, 19);
6177Add32 (ARMword a1, ARMword a2, int *carry) 5593 nRdLo = BITS (12, 15);
6178{
6179 ARMword result = (a1 + a2);
6180 unsigned int uresult = (unsigned int) result;
6181 unsigned int ua1 = (unsigned int) a1;
6182
6183 /* If (result == RdLo) and (state->Reg[nRdLo] == 0),
6184 or (result > RdLo) then we have no carry. */
6185 if ((uresult == ua1) ? (a2 != 0) : (uresult < ua1))
6186 *carry = 1;
6187 else
6188 *carry = 0;
6189
6190 return result;
6191}
6192 5594
6193/* This function does the work of multiplying 5595 RdHi = state->Reg[nRdHi];
6194 two 32bit values to give a 64bit result. */ 5596 RdLo = state->Reg[nRdLo];
6195 5597
6196static unsigned 5598 scount = Multiply64 (state, instr, msigned, LDEFAULT);
6197Multiply64 (ARMul_State * state, ARMword instr, int msigned, int scc)
6198{
6199 /* Operand register numbers. */
6200 int nRdHi, nRdLo, nRs, nRm;
6201 ARMword RdHi = 0, RdLo = 0, Rm;
6202 /* Cycle count. */
6203 int scount;
6204
6205 nRdHi = BITS (16, 19);
6206 nRdLo = BITS (12, 15);
6207 nRs = BITS (8, 11);
6208 nRm = BITS (0, 3);
6209
6210 /* Needed to calculate the cycle count. */
6211 Rm = state->Reg[nRm];
6212
6213 /* Check for illegal operand combinations first. */
6214 if (nRdHi != 15
6215 && nRdLo != 15
6216 && nRs != 15
6217 //&& nRm != 15 && nRdHi != nRdLo && nRdHi != nRm && nRdLo != nRm) {
6218 && nRm != 15 && nRdHi != nRdLo ) {
6219 /* Intermediate results. */
6220 ARMword lo, mid1, mid2, hi;
6221 int carry;
6222 ARMword Rs = state->Reg[nRs];
6223 int sign = 0;
6224
6225 if (msigned) {
6226 /* Compute sign of result and adjust operands if necessary. */
6227 sign = (Rm ^ Rs) & 0x80000000;
6228
6229 if (((signed int) Rm) < 0)
6230 Rm = -Rm;
6231
6232 if (((signed int) Rs) < 0)
6233 Rs = -Rs;
6234 }
6235 5599
6236 /* We can split the 32x32 into four 16x16 operations. This 5600 RdLo = Add32 (RdLo, state->Reg[nRdLo], &carry);
6237 ensures that we do not lose precision on 32bit only hosts. */ 5601 RdHi = (RdHi + state->Reg[nRdHi]) + carry;
6238 lo = ((Rs & 0xFFFF) * (Rm & 0xFFFF));
6239 mid1 = ((Rs & 0xFFFF) * ((Rm >> 16) & 0xFFFF));
6240 mid2 = (((Rs >> 16) & 0xFFFF) * (Rm & 0xFFFF));
6241 hi = (((Rs >> 16) & 0xFFFF) * ((Rm >> 16) & 0xFFFF));
6242
6243 /* We now need to add all of these results together, taking
6244 care to propogate the carries from the additions. */
6245 RdLo = Add32 (lo, (mid1 << 16), &carry);
6246 RdHi = carry;
6247 RdLo = Add32 (RdLo, (mid2 << 16), &carry);
6248 RdHi += (carry + ((mid1 >> 16) & 0xFFFF) +
6249 ((mid2 >> 16) & 0xFFFF) + hi);
6250
6251 if (sign) {
6252 /* Negate result if necessary. */
6253 RdLo = ~RdLo;
6254 RdHi = ~RdHi;
6255 if (RdLo == 0xFFFFFFFF) {
6256 RdLo = 0;
6257 RdHi += 1;
6258 }
6259 else
6260 RdLo += 1;
6261 }
6262 5602
6263 state->Reg[nRdLo] = RdLo; 5603 state->Reg[nRdLo] = RdLo;
6264 state->Reg[nRdHi] = RdHi; 5604 state->Reg[nRdHi] = RdHi;
5605
5606 if (scc)
5607 /* Ensure that both RdHi and RdLo are used to compute Z,
5608 but don't let RdLo's sign bit make it to N. */
5609 ARMul_NegZero (state, RdHi | (RdLo >> 16) | (RdLo & 0xFFFF));
5610
5611 /* Extra cycle for addition. */
5612 return scount + 1;
6265 } 5613 }
6266 else{
6267 fprintf (stderr, "sim: MULTIPLY64 - INVALID ARGUMENTS, instr=0x%x\n", instr);
6268 }
6269 if (scc)
6270 /* Ensure that both RdHi and RdLo are used to compute Z,
6271 but don't let RdLo's sign bit make it to N. */
6272 ARMul_NegZero (state, RdHi | (RdLo >> 16) | (RdLo & 0xFFFF));
6273
6274 /* The cycle count depends on whether the instruction is a signed or
6275 unsigned multiply, and what bits are clear in the multiplier. */
6276 if (msigned && (Rm & ((unsigned) 1 << 31)))
6277 /* Invert the bits to make the check against zero. */
6278 Rm = ~Rm;
6279
6280 if ((Rm & 0xFFFFFF00) == 0)
6281 scount = 1;
6282 else if ((Rm & 0xFFFF0000) == 0)
6283 scount = 2;
6284 else if ((Rm & 0xFF000000) == 0)
6285 scount = 3;
6286 else
6287 scount = 4;
6288
6289 return 2 + scount;
6290}
6291 5614
6292/* This function does the work of multiplying two 32bit 5615 /* Attempt to emulate an ARMv6 instruction.
6293 values and adding a 64bit value to give a 64bit result. */ 5616 Returns non-zero upon success. */
5617
5618 static int
5619 handle_v6_insn (ARMul_State * state, ARMword instr) {
5620 switch (BITS (20, 27)) {
5621 //ichfly
5622 case 0x66: //UQSUB8
5623 if ((instr & 0x0FF00FF0) == 0x06600FF0) {
5624 u32 rd = (instr >> 12) & 0xF;
5625 u32 rm = (instr >> 16) & 0xF;
5626 u32 rn = (instr >> 0) & 0xF;
5627 u32 subfrom = state->Reg[rm];
5628 u32 tosub = state->Reg[rn];
5629
5630 u8 b1 = (u8)((u8)(subfrom)-(u8)(tosub));
5631 if (b1 > (u8)(subfrom)) b1 = 0;
5632 u8 b2 = (u8)((u8)(subfrom >> 8) - (u8)(tosub >> 8));
5633 if (b2 > (u8)(subfrom >> 8)) b2 = 0;
5634 u8 b3 = (u8)((u8)(subfrom >> 16) - (u8)(tosub >> 16));
5635 if (b3 > (u8)(subfrom >> 16)) b3 = 0;
5636 u8 b4 = (u8)((u8)(subfrom >> 24) - (u8)(tosub >> 24));
5637 if (b4 > (u8)(subfrom >> 24)) b4 = 0;
5638 state->Reg[rd] = (u32)(b1 | b2 << 8 | b3 << 16 | b4 << 24);
5639 return 1;
5640 } else {
5641 printf("UQSUB8 decoding fail %08X",instr);
5642 }
5643#if 0
5644 case 0x03:
5645 printf ("Unhandled v6 insn: ldr\n");
5646 break;
5647 case 0x04:
5648 printf ("Unhandled v6 insn: umaal\n");
5649 break;
5650 case 0x06:
5651 printf ("Unhandled v6 insn: mls/str\n");
5652 break;
5653 case 0x16:
5654 printf ("Unhandled v6 insn: smi\n");
5655 break;
5656 case 0x18:
5657 printf ("Unhandled v6 insn: strex\n");
5658 break;
5659 case 0x19:
5660 printf ("Unhandled v6 insn: ldrex\n");
5661 break;
5662 case 0x1a:
5663 printf ("Unhandled v6 insn: strexd\n");
5664 break;
5665 case 0x1b:
5666 printf ("Unhandled v6 insn: ldrexd\n");
5667 break;
5668 case 0x1c:
5669 printf ("Unhandled v6 insn: strexb\n");
5670 break;
5671 case 0x1d:
5672 printf ("Unhandled v6 insn: ldrexb\n");
5673 break;
5674 case 0x1e:
5675 printf ("Unhandled v6 insn: strexh\n");
5676 break;
5677 case 0x1f:
5678 printf ("Unhandled v6 insn: ldrexh\n");
5679 break;
5680 case 0x30:
5681 printf ("Unhandled v6 insn: movw\n");
5682 break;
5683 case 0x32:
5684 printf ("Unhandled v6 insn: nop/sev/wfe/wfi/yield\n");
5685 break;
5686 case 0x34:
5687 printf ("Unhandled v6 insn: movt\n");
5688 break;
5689 case 0x3f:
5690 printf ("Unhandled v6 insn: rbit\n");
5691 break;
5692 case 0x61:
5693 printf ("Unhandled v6 insn: sadd/ssub\n");
5694 break;
5695 case 0x62:
5696 printf ("Unhandled v6 insn: qadd/qsub\n");
5697 break;
5698 case 0x63:
5699 printf ("Unhandled v6 insn: shadd/shsub\n");
5700 break;
5701 case 0x65:
5702 printf ("Unhandled v6 insn: uadd/usub\n");
5703 break;
5704 case 0x66:
5705 printf ("Unhandled v6 insn: uqadd/uqsub\n");
5706 break;
5707 case 0x67:
5708 printf ("Unhandled v6 insn: uhadd/uhsub\n");
5709 break;
5710 case 0x68:
5711 printf ("Unhandled v6 insn: pkh/sxtab/selsxtb\n");
5712 break;
5713#endif
5714 case 0x6c:
5715 printf ("Unhandled v6 insn: uxtb16/uxtab16\n");
5716 break;
5717 case 0x70:
5718 printf ("Unhandled v6 insn: smuad/smusd/smlad/smlsd\n");
5719 break;
5720 case 0x74:
5721 printf ("Unhandled v6 insn: smlald/smlsld\n");
5722 break;
5723 case 0x75:
5724 printf ("Unhandled v6 insn: smmla/smmls/smmul\n");
5725 break;
5726 case 0x78:
5727 printf ("Unhandled v6 insn: usad/usada8\n");
5728 break;
5729#if 0
5730 case 0x7a:
5731 printf ("Unhandled v6 insn: usbfx\n");
5732 break;
5733 case 0x7c:
5734 printf ("Unhandled v6 insn: bfc/bfi\n");
5735 break;
5736#endif
6294 5737
6295static unsigned
6296MultiplyAdd64 (ARMul_State * state, ARMword instr, int msigned, int scc)
6297{
6298 unsigned scount;
6299 ARMword RdLo, RdHi;
6300 int nRdHi, nRdLo;
6301 int carry = 0;
6302 5738
6303 nRdHi = BITS (16, 19); 5739 /* add new instr for arm v6. */
6304 nRdLo = BITS (12, 15); 5740 ARMword lhs, temp;
5741 case 0x18: { /* ORR reg */
5742 /* dyf add armv6 instr strex 2010.9.17 */
5743 if (BITS (4, 7) == 0x9) {
5744 u32 l = LHSReg;
5745 u32 r = RHSReg;
5746 lhs = LHS;
6305 5747
6306 RdHi = state->Reg[nRdHi]; 5748 bool enter = false;
6307 RdLo = state->Reg[nRdLo];
6308 5749
6309 scount = Multiply64 (state, instr, msigned, LDEFAULT); 5750 if (state->currentexval == (u32)ARMul_ReadWord(state, state->currentexaddr))enter = true;
5751 ARMul_StoreWordS(state, lhs, RHS);
5752 //StoreWord(state, lhs, RHS)
5753 if (state->Aborted) {
5754 TAKEABORT;
5755 }
5756
5757 if (enter)
5758 {
5759 state->Reg[DESTReg] = 0;
5760 }
5761 else
5762 {
5763 state->Reg[DESTReg] = 1;
5764 }
6310 5765
6311 RdLo = Add32 (RdLo, state->Reg[nRdLo], &carry); 5766 return 1;
6312 RdHi = (RdHi + state->Reg[nRdHi]) + carry; 5767 }
5768 break;
5769 }
6313 5770
6314 state->Reg[nRdLo] = RdLo; 5771 case 0x19: { /* orrs reg */
6315 state->Reg[nRdHi] = RdHi; 5772 /* dyf add armv6 instr ldrex */
5773 if (BITS (4, 7) == 0x9) {
5774 lhs = LHS;
6316 5775
6317 if (scc) 5776 state->currentexaddr = lhs;
6318 /* Ensure that both RdHi and RdLo are used to compute Z, 5777 state->currentexval = ARMul_ReadWord(state, lhs);
6319 but don't let RdLo's sign bit make it to N. */
6320 ARMul_NegZero (state, RdHi | (RdLo >> 16) | (RdLo & 0xFFFF));
6321 5778
6322 /* Extra cycle for addition. */ 5779 LoadWord (state, instr, lhs);
6323 return scount + 1; 5780 return 1;
6324} 5781 }
5782 break;
5783 }
6325 5784
6326/* Attempt to emulate an ARMv6 instruction. 5785 case 0x1c: { /* BIC reg */
6327 Returns non-zero upon success. */ 5786 /* dyf add for STREXB */
5787 if (BITS (4, 7) == 0x9) {
5788 lhs = LHS;
6328 5789
6329static int 5790 bool enter = false;
6330handle_v6_insn (ARMul_State * state, ARMword instr)
6331{
6332 switch (BITS (20, 27))
6333 {
6334#if 0
6335 case 0x03: printf ("Unhandled v6 insn: ldr\n"); break;
6336 case 0x04: printf ("Unhandled v6 insn: umaal\n"); break;
6337 case 0x06: printf ("Unhandled v6 insn: mls/str\n"); break;
6338 case 0x16: printf ("Unhandled v6 insn: smi\n"); break;
6339 case 0x18: printf ("Unhandled v6 insn: strex\n"); break;
6340 case 0x19: printf ("Unhandled v6 insn: ldrex\n"); break;
6341 case 0x1a: printf ("Unhandled v6 insn: strexd\n"); break;
6342 case 0x1b: printf ("Unhandled v6 insn: ldrexd\n"); break;
6343 case 0x1c: printf ("Unhandled v6 insn: strexb\n"); break;
6344 case 0x1d: printf ("Unhandled v6 insn: ldrexb\n"); break;
6345 case 0x1e: printf ("Unhandled v6 insn: strexh\n"); break;
6346 case 0x1f: printf ("Unhandled v6 insn: ldrexh\n"); break;
6347 case 0x30: printf ("Unhandled v6 insn: movw\n"); break;
6348 case 0x32: printf ("Unhandled v6 insn: nop/sev/wfe/wfi/yield\n"); break;
6349 case 0x34: printf ("Unhandled v6 insn: movt\n"); break;
6350 case 0x3f: printf ("Unhandled v6 insn: rbit\n"); break;
6351 case 0x61: printf ("Unhandled v6 insn: sadd/ssub\n"); break;
6352 case 0x62: printf ("Unhandled v6 insn: qadd/qsub\n"); break;
6353 case 0x63: printf ("Unhandled v6 insn: shadd/shsub\n"); break;
6354 case 0x65: printf ("Unhandled v6 insn: uadd/usub\n"); break;
6355 case 0x66: printf ("Unhandled v6 insn: uqadd/uqsub\n"); break;
6356 case 0x67: printf ("Unhandled v6 insn: uhadd/uhsub\n"); break;
6357 case 0x68: printf ("Unhandled v6 insn: pkh/sxtab/selsxtb\n"); break;
6358#endif
6359 case 0x6c: printf ("Unhandled v6 insn: uxtb16/uxtab16\n"); break;
6360 case 0x70: printf ("Unhandled v6 insn: smuad/smusd/smlad/smlsd\n"); break;
6361 case 0x74: printf ("Unhandled v6 insn: smlald/smlsld\n"); break;
6362 case 0x75: printf ("Unhandled v6 insn: smmla/smmls/smmul\n"); break;
6363 case 0x78: printf ("Unhandled v6 insn: usad/usada8\n"); break;
6364#if 0
6365 case 0x7a: printf ("Unhandled v6 insn: usbfx\n"); break;
6366 case 0x7c: printf ("Unhandled v6 insn: bfc/bfi\n"); break;
6367#endif
6368 5791
5792 if (state->currentexval == (u32)ARMul_ReadByte(state, state->currentexaddr))enter = true;
6369 5793
6370/* add new instr for arm v6. */ 5794 ARMul_StoreByte (state, lhs, RHS);
6371 ARMword lhs, temp; 5795 BUSUSEDINCPCN;
6372 case 0x18: /* ORR reg */ 5796 if (state->Aborted) {
6373 { 5797 TAKEABORT;
6374 /* dyf add armv6 instr strex 2010.9.17 */ 5798 }
6375 if (BITS (4, 7) == 0x9) { 5799
6376 lhs = LHS; 5800
6377 ARMul_StoreWordS(state, lhs, RHS); 5801 if (enter)
6378 //StoreWord(state, lhs, RHS) 5802 {
6379 if (state->Aborted) { 5803 state->Reg[DESTReg] = 0;
6380 TAKEABORT; 5804 }
5805 else
5806 {
5807 state->Reg[DESTReg] = 1;
5808 }
5809
5810 //printf("In %s, strexb not implemented\n", __FUNCTION__);
5811 UNDEF_LSRBPC;
5812 /* WRITESDEST (dest); */
5813 return 1;
5814 }
5815 break;
6381 } 5816 }
6382 // FIX(Normmatt): Handle RD in STREX/STREXB
6383 state->Reg[DESTReg] = 0; //Always succeed
6384 5817
6385 return 1; 5818 case 0x1d: { /* BICS reg */
6386 } 5819 if ((BITS (4, 7)) == 0x9) {
6387 break; 5820 /* ldrexb */
6388 } 5821 temp = LHS;
6389 5822 LoadByte (state, instr, temp, LUNSIGNED);
6390 case 0x19: /* orrs reg */ 5823
6391 { 5824 state->currentexaddr = temp;
6392 /* dyf add armv6 instr ldrex */ 5825 state->currentexval = (u32)ARMul_ReadByte(state, temp);
6393 if (BITS (4, 7) == 0x9) { 5826
6394 lhs = LHS; 5827 //state->Reg[BITS(12, 15)] = ARMul_LoadByte(state, state->Reg[BITS(16, 19)]);
6395 LoadWord (state, instr, lhs); 5828 //printf("ldrexb\n");
6396 return 1; 5829 //printf("instr is %x rm is %d\n", instr, BITS(16, 19));
6397 } 5830 //exit(-1);
6398 break; 5831
6399 } 5832 //printf("In %s, ldrexb not implemented\n", __FUNCTION__);
6400 5833 return 1;
6401 case 0x1c: /* BIC reg */ 5834 }
6402 { 5835 break;
6403 /* dyf add for STREXB */ 5836 }
6404 if (BITS (4, 7) == 0x9) { 5837 /* add end */
6405 lhs = LHS; 5838
6406 ARMul_StoreByte (state, lhs, RHS); 5839 case 0x6a: {
6407 BUSUSEDINCPCN; 5840 ARMword Rm;
6408 if (state->Aborted) { 5841 int ror = -1;
6409 TAKEABORT; 5842
5843 switch (BITS (4, 11)) {
5844 case 0x07:
5845 ror = 0;
5846 break;
5847 case 0x47:
5848 ror = 8;
5849 break;
5850 case 0x87:
5851 ror = 16;
5852 break;
5853 case 0xc7:
5854 ror = 24;
5855 break;
5856
5857 case 0x01:
5858 case 0xf3:
5859 printf ("Unhandled v6 insn: ssat\n");
5860 return 0;
5861 default:
5862 break;
5863 }
5864
5865 if (ror == -1) {
5866 if (BITS (4, 6) == 0x7) {
5867 printf ("Unhandled v6 insn: ssat\n");
5868 return 0;
5869 }
5870 break;
5871 }
5872
5873 Rm = ((state->Reg[BITS (0, 3)] >> ror) & 0xFF);
5874 if (Rm & 0x80)
5875 Rm |= 0xffffff00;
5876
5877 if (BITS (16, 19) == 0xf)
5878 /* SXTB */
5879 state->Reg[BITS (12, 15)] = Rm;
5880 else
5881 /* SXTAB */
5882 state->Reg[BITS (12, 15)] += Rm;
6410 } 5883 }
6411 // FIX(Normmatt): Handle RD in STREX/STREXB
6412 state->Reg[DESTReg] = 0; //Always succeed
6413 //printf("In %s, strexb not implemented\n", __FUNCTION__);
6414 UNDEF_LSRBPC;
6415 /* WRITESDEST (dest); */
6416 return 1;
6417 }
6418 break;
6419 }
6420
6421 case 0x1d: /* BICS reg */
6422 {
6423 if ((BITS (4, 7)) == 0x9) {
6424 /* ldrexb */
6425 temp = LHS;
6426 LoadByte (state, instr, temp, LUNSIGNED);
6427 //state->Reg[BITS(12, 15)] = ARMul_LoadByte(state, state->Reg[BITS(16, 19)]);
6428 //printf("ldrexb\n");
6429 //printf("instr is %x rm is %d\n", instr, BITS(16, 19));
6430 //exit(-1);
6431
6432 //printf("In %s, ldrexb not implemented\n", __FUNCTION__);
6433 return 1; 5884 return 1;
6434 } 5885
6435 break; 5886 case 0x6b: {
6436 } 5887 ARMword Rm;
6437/* add end */ 5888 int ror = -1;
6438 5889
6439 case 0x6a: 5890 switch (BITS (4, 11)) {
6440 { 5891 case 0x07:
6441 ARMword Rm; 5892 ror = 0;
6442 int ror = -1; 5893 break;
6443 5894 case 0x47:
6444 switch (BITS (4, 11)) 5895 ror = 8;
6445 { 5896 break;
6446 case 0x07: ror = 0; break; 5897 case 0x87:
6447 case 0x47: ror = 8; break; 5898 ror = 16;
6448 case 0x87: ror = 16; break; 5899 break;
6449 case 0xc7: ror = 24; break; 5900 case 0xc7:
6450 5901 ror = 24;
6451 case 0x01: 5902 break;
6452 case 0xf3: 5903
6453 printf ("Unhandled v6 insn: ssat\n"); 5904 case 0xf3:
6454 return 0; 5905 DEST = ((RHS & 0xFF) << 24) | ((RHS & 0xFF00)) << 8 | ((RHS & 0xFF0000) >> 8) | ((RHS & 0xFF000000) >> 24);
6455 default: 5906 return 1;
6456 break; 5907 case 0xfb:
6457 } 5908 DEST = ((RHS & 0xFF) << 8) | ((RHS & 0xFF00)) >> 8 | ((RHS & 0xFF0000) << 8) | ((RHS & 0xFF000000) >> 8);
6458 5909 return 1;
6459 if (ror == -1) 5910 default:
6460 { 5911 break;
6461 if (BITS (4, 6) == 0x7) 5912 }
6462 { 5913
6463 printf ("Unhandled v6 insn: ssat\n"); 5914 if (ror == -1)
6464 return 0; 5915 break;
6465 } 5916
6466 break; 5917 Rm = ((state->Reg[BITS (0, 3)] >> ror) & 0xFFFF);
6467 } 5918 if (Rm & 0x8000)
6468 5919 Rm |= 0xffff0000;
6469 Rm = ((state->Reg[BITS (0, 3)] >> ror) & 0xFF); 5920
6470 if (Rm & 0x80) 5921 if (BITS (16, 19) == 0xf)
6471 Rm |= 0xffffff00; 5922 /* SXTH */
6472 5923 state->Reg[BITS (12, 15)] = Rm;
6473 if (BITS (16, 19) == 0xf) 5924 else
6474 /* SXTB */ 5925 /* SXTAH */
6475 state->Reg[BITS (12, 15)] = Rm; 5926 state->Reg[BITS (12, 15)] = state->Reg[BITS (16, 19)] + Rm;
6476 else 5927 }
6477 /* SXTAB */
6478 state->Reg[BITS (12, 15)] += Rm;
6479 }
6480 return 1;
6481
6482 case 0x6b:
6483 {
6484 ARMword Rm;
6485 int ror = -1;
6486
6487 switch (BITS (4, 11))
6488 {
6489 case 0x07: ror = 0; break;
6490 case 0x47: ror = 8; break;
6491 case 0x87: ror = 16; break;
6492 case 0xc7: ror = 24; break;
6493
6494 case 0xf3:
6495 DEST = ((RHS & 0xFF) << 24) | ((RHS & 0xFF00)) << 8 | ((RHS & 0xFF0000) >> 8) | ((RHS & 0xFF000000) >> 24);
6496 return 1; 5928 return 1;
6497 case 0xfb: 5929
6498 DEST = ((RHS & 0xFF) << 8) | ((RHS & 0xFF00)) >> 8 | ((RHS & 0xFF0000) << 8) | ((RHS & 0xFF000000) >> 8); 5930 case 0x6e: {
5931 ARMword Rm;
5932 int ror = -1;
5933
5934 switch (BITS (4, 11)) {
5935 case 0x07:
5936 ror = 0;
5937 break;
5938 case 0x47:
5939 ror = 8;
5940 break;
5941 case 0x87:
5942 ror = 16;
5943 break;
5944 case 0xc7:
5945 ror = 24;
5946 break;
5947
5948 case 0x01:
5949 case 0xf3:
5950 printf ("Unhandled v6 insn: usat\n");
5951 return 0;
5952 default:
5953 break;
5954 }
5955
5956 if (ror == -1) {
5957 if (BITS (4, 6) == 0x7) {
5958 printf ("Unhandled v6 insn: usat\n");
5959 return 0;
5960 }
5961 break;
5962 }
5963
5964 Rm = ((state->Reg[BITS (0, 3)] >> ror) & 0xFF);
5965
5966 if (BITS (16, 19) == 0xf)
5967 /* UXTB */
5968 state->Reg[BITS (12, 15)] = Rm;
5969 else
5970 /* UXTAB */
5971 state->Reg[BITS (12, 15)] = state->Reg[BITS (16, 19)] + Rm;
5972 }
6499 return 1; 5973 return 1;
6500 default: 5974
6501 break; 5975 case 0x6f: {
6502 } 5976 ARMword Rm;
6503 5977 int ror = -1;
6504 if (ror == -1) 5978
6505 break; 5979 switch (BITS (4, 11)) {
6506 5980 case 0x07:
6507 Rm = ((state->Reg[BITS (0, 3)] >> ror) & 0xFFFF); 5981 ror = 0;
6508 if (Rm & 0x8000) 5982 break;
6509 Rm |= 0xffff0000; 5983 case 0x47:
6510 5984 ror = 8;
6511 if (BITS (16, 19) == 0xf) 5985 break;
6512 /* SXTH */ 5986 case 0x87:
6513 state->Reg[BITS (12, 15)] = Rm; 5987 ror = 16;
6514 else 5988 break;
6515 /* SXTAH */ 5989 case 0xc7:
6516 state->Reg[BITS (12, 15)] = state->Reg[BITS (16, 19)] + Rm; 5990 ror = 24;
6517 } 5991 break;
6518 return 1; 5992
6519 5993 case 0xfb:
6520 case 0x6e: 5994 printf ("Unhandled v6 insn: revsh\n");
6521 { 5995 return 0;
6522 ARMword Rm; 5996 default:
6523 int ror = -1; 5997 break;
6524 5998 }
6525 switch (BITS (4, 11)) 5999
6526 { 6000 if (ror == -1)
6527 case 0x07: ror = 0; break; 6001 break;
6528 case 0x47: ror = 8; break; 6002
6529 case 0x87: ror = 16; break; 6003 Rm = ((state->Reg[BITS (0, 3)] >> ror) & 0xFFFF);
6530 case 0xc7: ror = 24; break; 6004
6531 6005 /* UXT */
6532 case 0x01: 6006 /* state->Reg[BITS (12, 15)] = Rm; */
6533 case 0xf3: 6007 /* dyf add */
6534 printf ("Unhandled v6 insn: usat\n"); 6008 if (BITS (16, 19) == 0xf) {
6535 return 0; 6009 state->Reg[BITS (12, 15)] = (Rm >> (8 * BITS(10, 11))) & 0x0000FFFF;
6536 default: 6010 } else {
6537 break; 6011 /* UXTAH */
6538 } 6012 /* state->Reg[BITS (12, 15)] = state->Reg [BITS (16, 19)] + Rm; */
6539
6540 if (ror == -1)
6541 {
6542 if (BITS (4, 6) == 0x7)
6543 {
6544 printf ("Unhandled v6 insn: usat\n");
6545 return 0;
6546 }
6547 break;
6548 }
6549
6550 Rm = ((state->Reg[BITS (0, 3)] >> ror) & 0xFF);
6551
6552 if (BITS (16, 19) == 0xf)
6553 /* UXTB */
6554 state->Reg[BITS (12, 15)] = Rm;
6555 else
6556 /* UXTAB */
6557 state->Reg[BITS (12, 15)] = state->Reg[BITS (16, 19)] + Rm;
6558 }
6559 return 1;
6560
6561 case 0x6f:
6562 {
6563 ARMword Rm;
6564 int ror = -1;
6565
6566 switch (BITS (4, 11))
6567 {
6568 case 0x07: ror = 0; break;
6569 case 0x47: ror = 8; break;
6570 case 0x87: ror = 16; break;
6571 case 0xc7: ror = 24; break;
6572
6573 case 0xfb:
6574 printf ("Unhandled v6 insn: revsh\n");
6575 return 0;
6576 default:
6577 break;
6578 }
6579
6580 if (ror == -1)
6581 break;
6582
6583 Rm = ((state->Reg[BITS (0, 3)] >> ror) & 0xFFFF);
6584
6585 /* UXT */
6586 /* state->Reg[BITS (12, 15)] = Rm; */
6587 /* dyf add */
6588 if (BITS (16, 19) == 0xf) {
6589 state->Reg[BITS (12, 15)] = (Rm >> (8 * BITS(10, 11))) & 0x0000FFFF;
6590 } else {
6591 /* UXTAH */
6592 /* state->Reg[BITS (12, 15)] = state->Reg [BITS (16, 19)] + Rm; */
6593// printf("rd is %x rn is %x rm is %x rotate is %x\n", state->Reg[BITS (12, 15)], state->Reg[BITS (16, 19)] 6013// printf("rd is %x rn is %x rm is %x rotate is %x\n", state->Reg[BITS (12, 15)], state->Reg[BITS (16, 19)]
6594// , Rm, BITS(10, 11)); 6014// , Rm, BITS(10, 11));
6595// printf("icounter is %lld\n", state->NumInstrs); 6015// printf("icounter is %lld\n", state->NumInstrs);
6596 state->Reg[BITS (12, 15)] = (state->Reg[BITS (16, 19)] >> (8 * (BITS(10, 11)))) + Rm; 6016 state->Reg[BITS (12, 15)] = (state->Reg[BITS (16, 19)] >> (8 * (BITS(10, 11)))) + Rm;
6597// printf("rd is %x\n", state->Reg[BITS (12, 15)]); 6017// printf("rd is %x\n", state->Reg[BITS (12, 15)]);
6598// exit(-1); 6018// exit(-1);
6599 } 6019 }
6600 } 6020 }
6601 return 1; 6021 return 1;
6602 6022
6603#if 0 6023#if 0
6604 case 0x84: printf ("Unhandled v6 insn: srs\n"); break; 6024 case 0x84:
6025 printf ("Unhandled v6 insn: srs\n");
6026 break;
6605#endif 6027#endif
6606 default: 6028 default:
6607 break; 6029 break;
6030 }
6031 printf("Unhandled v6 insn: UNKNOWN: %08x %08X\n", instr, BITS(20, 27));
6032 return 0;
6608 } 6033 }
6609 printf ("Unhandled v6 insn: UNKNOWN: %08x\n", instr);
6610 return 0;
6611}
diff --git a/src/core/arm/interpreter/armemu.h b/src/core/arm/interpreter/armemu.h
index 7ccb07e8d..36fb2d09b 100644
--- a/src/core/arm/interpreter/armemu.h
+++ b/src/core/arm/interpreter/armemu.h
@@ -18,10 +18,12 @@
18#define __ARMEMU_H__ 18#define __ARMEMU_H__
19 19
20 20
21#include "core/arm/interpreter/skyeye_defs.h" 21#include "armdefs.h"
22#include "core/arm/interpreter/armdefs.h" 22//#include "skyeye.h"
23 23
24extern ARMword isize; 24//extern ARMword isize;
25
26#define DEBUG(...) DEBUG_LOG(ARM11, __VA_ARGS__)
25 27
26/* Condition code values. */ 28/* Condition code values. */
27#define EQ 0 29#define EQ 0
@@ -228,17 +230,6 @@ extern ARMword isize;
228 } \ 230 } \
229 while (0) 231 while (0)
230 232
231#define SETABORT_SKIPBRANCH(i, m, d) \
232 do \
233 { \
234 int SETABORT_mode = (m); \
235 \
236 ARMul_SetSPSR (state, SETABORT_mode, ARMul_GetCPSR (state)); \
237 ARMul_SetCPSR (state, ((ARMul_GetCPSR (state) & ~(EMODE | TBIT)) \
238 | (i) | SETABORT_mode)); \
239 } \
240 while (0)
241
242#ifndef MODE32 233#ifndef MODE32
243#define VECTORS 0x20 234#define VECTORS 0x20
244#define LEGALADDR 0x03ffffff 235#define LEGALADDR 0x03ffffff
@@ -306,7 +297,7 @@ extern ARMword isize;
306 if (! state->is_v4) \ 297 if (! state->is_v4) \
307 { \ 298 { \
308 /* A standard PC inc and an S cycle. */ \ 299 /* A standard PC inc and an S cycle. */ \
309 state->Reg[15] += isize; \ 300 state->Reg[15] += INSN_SIZE; \
310 state->NextInstr = (state->NextInstr & 0xff) | 2; \ 301 state->NextInstr = (state->NextInstr & 0xff) | 2; \
311 } \ 302 } \
312 } \ 303 } \
@@ -320,7 +311,7 @@ extern ARMword isize;
320 else \ 311 else \
321 { \ 312 { \
322 /* A standard PC inc and an N cycle. */ \ 313 /* A standard PC inc and an N cycle. */ \
323 state->Reg[15] += isize; \ 314 state->Reg[15] += INSN_SIZE; \
324 state->NextInstr |= 3; \ 315 state->NextInstr |= 3; \
325 } \ 316 } \
326 } \ 317 } \
@@ -330,7 +321,7 @@ extern ARMword isize;
330 do \ 321 do \
331 { \ 322 { \
332 /* A standard PC inc. */ \ 323 /* A standard PC inc. */ \
333 state->Reg[15] += isize; \ 324 state->Reg[15] += INSN_SIZE; \
334 state->NextInstr |= 2; \ 325 state->NextInstr |= 2; \
335 } \ 326 } \
336 while (0) 327 while (0)
@@ -420,9 +411,7 @@ extern ARMword isize;
420 || (read_cp15_reg (15, 0, 1) & (1 << (CP)))) 411 || (read_cp15_reg (15, 0, 1) & (1 << (CP))))
421*/ 412*/
422#define CP_ACCESS_ALLOWED(STATE, CP) \ 413#define CP_ACCESS_ALLOWED(STATE, CP) \
423 ( ((CP) >= 14) \ 414 ( ((CP) >= 14) ) \
424 || (! (STATE)->is_XScale) \
425 || (xscale_cp15_cp_access_allowed(STATE,15,CP)))
426 415
427/* Macro to rotate n right by b bits. */ 416/* Macro to rotate n right by b bits. */
428#define ROTATER(n, b) (((n) >> (b)) | ((n) << (32 - (b)))) 417#define ROTATER(n, b) (((n) >> (b)) | ((n) << (32 - (b))))
diff --git a/src/core/arm/interpreter/arminit.cpp b/src/core/arm/interpreter/arminit.cpp
index e05667bea..6fbab3bfb 100644
--- a/src/core/arm/interpreter/arminit.cpp
+++ b/src/core/arm/interpreter/arminit.cpp
@@ -1,30 +1,21 @@
1/* arminit.c -- ARMulator initialization: ARM6 Instruction Emulator. 1/* arminit.c -- ARMulator initialization: ARM6 Instruction Emulator.
2 Copyright (C) 1994 Advanced RISC Machines Ltd. 2 Copyright (C) 1994 Advanced RISC Machines Ltd.
3 3
4 This program is free software; you can redistribute it and/or modify 4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by 5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or 6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version. 7 (at your option) any later version.
8 8
9 This program is distributed in the hope that it will be useful, 9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of 10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details. 12 GNU General Public License for more details.
13 13
14 You should have received a copy of the GNU General Public License 14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software 15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
17 17
18 18//#include <unistd.h>
19#include "common/platform.h"
20
21#if EMU_PLATFORM == PLATFORM_LINUX
22#include <unistd.h>
23#elif EMU_PLATFORM == PLATFORM_WINDOWS
24#include <windows.h>
25#endif
26
27#include <math.h>
28 19
29#include "core/arm/interpreter/armdefs.h" 20#include "core/arm/interpreter/armdefs.h"
30#include "core/arm/interpreter/armemu.h" 21#include "core/arm/interpreter/armemu.h"
@@ -42,9 +33,9 @@ ARMword ARMul_DoProg (ARMul_State * state);
42ARMword ARMul_DoInstr (ARMul_State * state); 33ARMword ARMul_DoInstr (ARMul_State * state);
43void ARMul_Abort (ARMul_State * state, ARMword address); 34void ARMul_Abort (ARMul_State * state, ARMword address);
44 35
45unsigned ARMul_MultTable[32] = 36unsigned ARMul_MultTable[32] = {
46 { 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 37 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9,
47 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 16, 16, 16 38 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 16, 16, 16
48}; 39};
49ARMword ARMul_ImmedTable[4096]; /* immediate DP LHS values */ 40ARMword ARMul_ImmedTable[4096]; /* immediate DP LHS values */
50char ARMul_BitList[256]; /* number of bits in a byte table */ 41char ARMul_BitList[256]; /* number of bits in a byte table */
@@ -56,78 +47,34 @@ extern int remote_interrupt( void );
56 47
57void arm_dyncom_Abort(ARMul_State * state, ARMword vector) 48void arm_dyncom_Abort(ARMul_State * state, ARMword vector)
58{ 49{
59 ARMul_Abort(state, vector); 50 ARMul_Abort(state, vector);
60} 51}
61 52
62 53
63/* ahe-ykl : the following code to initialize user mode 54/* ahe-ykl : the following code to initialize user mode
64 code is architecture dependent and probably model dependant. */ 55 code is architecture dependent and probably model dependant. */
65 56
66//#include "skyeye_arch.h" 57/*#include "skyeye_arch.h"
67//#include "skyeye_pref.h" 58#include "skyeye_pref.h"
68//#include "skyeye_exec_info.h" 59#include "skyeye_exec_info.h"
69//#include "bank_defs.h" 60#include "bank_defs.h"*/
70#include "armcpu.h" 61//#include "armcpu.h"
71//#include "skyeye_callback.h" 62//#include "skyeye_callback.h"
72 63
73//void arm_user_mode_init(generic_arch_t * arch_instance) 64/*
74//{ 65 ARM_CPU_State* cpu = get_current_cpu();
75// sky_pref_t *pref = get_skyeye_pref(); 66 arm_core_t* core = &cpu->core[0];
76//
77// if (pref->user_mode_sim)
78// {
79// sky_exec_info_t *info = get_skyeye_exec_info();
80// info->arch_page_size = 0x1000;
81// info->arch_stack_top = 0x1ffffff0;// + 0x401fe7 - 0xff0; /* arbitrary value */
82// /* stack initial address specific to architecture may be placed here */
83//
84// /* we need to mmap the stack space, if we are using skyeye space */
85// if (info->mmap_access)
86// {
87// /* get system stack size */
88// size_t stacksize = 0;
89// pthread_attr_t attr;
90// pthread_attr_init(&attr);
91// pthread_attr_getstacksize(&attr, &stacksize);
92// if (stacksize > info->arch_stack_top)
93// {
94// printf("arch_stack_top is too low\n");
95// stacksize = info->arch_stack_top;
96// }
97//
98// /* Note: Skyeye is occupating 0x400000 to 0x600000 */
99// /* We do a mmap */
100// void* ret = mmap( (info->arch_stack_top) - stacksize,
101// stacksize + 0x1000 , PROT_READ | PROT_WRITE, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0);
102// if (ret == MAP_FAILED){
103// /* ideally, we should find an empty space until it works */
104// printf("mmap error, stack couldn't be mapped: errno %d\n", errno);
105// exit(-1);
106// } else {
107// memset(ret, '\0', stacksize);
108// //printf("stack top has been defined at %x size %x\n", (uint32_t) ret + stacksize, stacksize);
109// //info->arch_stack_top = (uint32_t) ret + stacksize;
110// }
111// }
112//
113// exec_stack_init();
114//
115// ARM_CPU_State* cpu = get_current_cpu();
116// arm_core_t* core = &cpu->core[0];
117//
118// uint32_t sp = info->initial_sp;
119//
120// core->Cpsr = 0x10; /* User mode */
121// /* FIXME: may need to add thumb */
122// core->Reg[13] = sp;
123// core->Reg[10] = info->start_data;
124// core->Reg[0] = 0;
125// bus_read(32, sp + 4, &(core->Reg[1]));
126// bus_read(32, sp + 8, &(core->Reg[2]));
127// }
128//
129//}
130 67
68 uint32_t sp = info->initial_sp;
69
70 core->Cpsr = 0x10; // User mode
71// FIXME: may need to add thumb
72core->Reg[13] = sp;
73core->Reg[10] = info->start_data;
74core->Reg[0] = 0;
75bus_read(32, sp + 4, &(core->Reg[1]));
76bus_read(32, sp + 8, &(core->Reg[2]));
77*/
131/***************************************************************************\ 78/***************************************************************************\
132* Call this routine once to set up the emulator's tables. * 79* Call this routine once to set up the emulator's tables. *
133\***************************************************************************/ 80\***************************************************************************/
@@ -135,20 +82,20 @@ void arm_dyncom_Abort(ARMul_State * state, ARMword vector)
135void 82void
136ARMul_EmulateInit (void) 83ARMul_EmulateInit (void)
137{ 84{
138 unsigned int i, j; 85 unsigned int i, j;
139 86
140 for (i = 0; i < 4096; i++) { /* the values of 12 bit dp rhs's */ 87 for (i = 0; i < 4096; i++) { /* the values of 12 bit dp rhs's */
141 ARMul_ImmedTable[i] = ROTATER (i & 0xffL, (i >> 7L) & 0x1eL); 88 ARMul_ImmedTable[i] = ROTATER (i & 0xffL, (i >> 7L) & 0x1eL);
142 } 89 }
143 90
144 for (i = 0; i < 256; ARMul_BitList[i++] = 0); /* how many bits in LSM */ 91 for (i = 0; i < 256; ARMul_BitList[i++] = 0); /* how many bits in LSM */
145 for (j = 1; j < 256; j <<= 1) 92 for (j = 1; j < 256; j <<= 1)
146 for (i = 0; i < 256; i++) 93 for (i = 0; i < 256; i++)
147 if ((i & j) > 0) 94 if ((i & j) > 0)
148 ARMul_BitList[i]++; 95 ARMul_BitList[i]++;
149 96
150 for (i = 0; i < 256; i++) 97 for (i = 0; i < 256; i++)
151 ARMul_BitList[i] *= 4; /* you always need 4 times these values */ 98 ARMul_BitList[i] *= 4; /* you always need 4 times these values */
152 99
153} 100}
154 101
@@ -159,80 +106,82 @@ ARMul_EmulateInit (void)
159ARMul_State * 106ARMul_State *
160ARMul_NewState (ARMul_State *state) 107ARMul_NewState (ARMul_State *state)
161{ 108{
162 unsigned i, j; 109 unsigned i, j;
163 110
164 memset (state, 0, sizeof (ARMul_State)); 111 memset (state, 0, sizeof (ARMul_State));
165 112
166 state->Emulate = RUN; 113 state->Emulate = RUN;
167 for (i = 0; i < 16; i++) { 114 for (i = 0; i < 16; i++) {
168 state->Reg[i] = 0; 115 state->Reg[i] = 0;
169 for (j = 0; j < 7; j++) 116 for (j = 0; j < 7; j++)
170 state->RegBank[j][i] = 0; 117 state->RegBank[j][i] = 0;
171 } 118 }
172 for (i = 0; i < 7; i++) 119 for (i = 0; i < 7; i++)
173 state->Spsr[i] = 0; 120 state->Spsr[i] = 0;
174 state->Mode = 0; 121 state->Mode = 0;
175 122
176 state->CallDebug = FALSE; 123 state->CallDebug = FALSE;
177 state->Debug = FALSE; 124 state->Debug = FALSE;
178 state->VectorCatch = 0; 125 state->VectorCatch = 0;
179 state->Aborted = FALSE; 126 state->Aborted = FALSE;
180 state->Reseted = FALSE; 127 state->Reseted = FALSE;
181 state->Inted = 3; 128 state->Inted = 3;
182 state->LastInted = 3; 129 state->LastInted = 3;
183 130
184 state->CommandLine = NULL; 131 state->CommandLine = NULL;
185 132
186 state->EventSet = 0; 133 state->EventSet = 0;
187 state->Now = 0; 134 state->Now = 0;
188 state->EventPtr = 135 state->EventPtr =
189 (struct EventNode **) malloc ((unsigned) EVENTLISTSIZE * 136 (struct EventNode **) malloc ((unsigned) EVENTLISTSIZE *
190 sizeof (struct EventNode *)); 137 sizeof (struct EventNode *));
191#if DIFF_STATE 138#if DIFF_STATE
192 state->state_log = fopen("/data/state.log", "w"); 139 state->state_log = fopen("/data/state.log", "w");
193 printf("create pc log file.\n"); 140 printf("create pc log file.\n");
194#endif 141#endif
195 if (state->EventPtr == NULL) { 142 if (state->EventPtr == NULL) {
196 printf ("SKYEYE: ARMul_NewState malloc state->EventPtr error\n"); 143 printf ("SKYEYE: ARMul_NewState malloc state->EventPtr error\n");
197 exit(-1); 144 exit(-1);
198 } 145 //skyeye_exit (-1);
199 for (i = 0; i < EVENTLISTSIZE; i++) 146 }
200 *(state->EventPtr + i) = NULL; 147 for (i = 0; i < EVENTLISTSIZE; i++)
148 *(state->EventPtr + i) = NULL;
201#if SAVE_LOG 149#if SAVE_LOG
202 state->state_log = fopen("/tmp/state.log", "w"); 150 state->state_log = fopen("/tmp/state.log", "w");
203 printf("create pc log file.\n"); 151 printf("create pc log file.\n");
204#else 152#else
205#if DIFF_LOG 153#if DIFF_LOG
206 state->state_log = fopen("/tmp/state.log", "r"); 154 state->state_log = fopen("/tmp/state.log", "r");
207 printf("loaded pc log file.\n"); 155 printf("loaded pc log file.\n");
208#endif 156#endif
209#endif 157#endif
210 158
211#ifdef ARM61 159#ifdef ARM61
212 state->prog32Sig = LOW; 160 state->prog32Sig = LOW;
213 state->data32Sig = LOW; 161 state->data32Sig = LOW;
214#else 162#else
215 state->prog32Sig = HIGH; 163 state->prog32Sig = HIGH;
216 state->data32Sig = HIGH; 164 state->data32Sig = HIGH;
217#endif 165#endif
218 166
219 state->lateabtSig = HIGH; 167 state->lateabtSig = HIGH;
220 state->bigendSig = LOW; 168 state->bigendSig = LOW;
221 169
222 //chy:2003-08-19 170 //chy:2003-08-19
223 state->LastTime = 0; 171 state->LastTime = 0;
224 state->CP14R0_CCD = -1; 172 state->CP14R0_CCD = -1;
225 173
226 /* ahe-ykl: common function for interpret and dyncom */ 174 /* ahe-ykl: common function for interpret and dyncom */
227 //sky_pref_t *pref = get_skyeye_pref(); 175 /*sky_pref_t *pref = get_skyeye_pref();
228 //if (pref->user_mode_sim) 176 if (pref->user_mode_sim)
229 // register_callback(arm_user_mode_init, Bootmach_callback); 177 register_callback(arm_user_mode_init, Bootmach_callback);
230 178 */
231 memset(&state->exclusive_tag_array[0], 0xFF, sizeof(state->exclusive_tag_array[0]) * 128); 179
232 state->exclusive_access_state = 0; 180 memset(&state->exclusive_tag_array[0], 0xFF, sizeof(state->exclusive_tag_array[0]) * 128);
233 //state->cpu = (cpu_config_t *) malloc (sizeof (cpu_config_t)); 181 state->exclusive_access_state = 0;
234 //state->mem_bank = (mem_config_t *) malloc (sizeof (mem_config_t)); 182 //state->cpu = (cpu_config_t *) malloc (sizeof (cpu_config_t));
235 return (state); 183 //state->mem_bank = (mem_config_t *) malloc (sizeof (mem_config_t));
184 return (state);
236} 185}
237 186
238/***************************************************************************\ 187/***************************************************************************\
@@ -242,39 +191,38 @@ ARMul_NewState (ARMul_State *state)
242void 191void
243ARMul_SelectProcessor (ARMul_State * state, unsigned properties) 192ARMul_SelectProcessor (ARMul_State * state, unsigned properties)
244{ 193{
245 if (properties & ARM_Fix26_Prop) { 194 if (properties & ARM_Fix26_Prop) {
246 state->prog32Sig = LOW; 195 state->prog32Sig = LOW;
247 state->data32Sig = LOW; 196 state->data32Sig = LOW;
248 } 197 } else {
249 else { 198 state->prog32Sig = HIGH;
250 state->prog32Sig = HIGH; 199 state->data32Sig = HIGH;
251 state->data32Sig = HIGH; 200 }
252 } 201 /* 2004-05-09 chy
253/* 2004-05-09 chy 202 below line sould be in skyeye_mach_XXX.c 's XXX_mach_init function
254below line sould be in skyeye_mach_XXX.c 's XXX_mach_init function 203 */
255*/ 204 // state->lateabtSig = HIGH;
256 // state->lateabtSig = HIGH; 205
257 206
258 207 state->is_v4 =
259 state->is_v4 = 208 (properties & (ARM_v4_Prop | ARM_v5_Prop)) ? HIGH : LOW;
260 (properties & (ARM_v4_Prop | ARM_v5_Prop)) ? HIGH : LOW; 209 state->is_v5 = (properties & ARM_v5_Prop) ? HIGH : LOW;
261 state->is_v5 = (properties & ARM_v5_Prop) ? HIGH : LOW; 210 state->is_v5e = (properties & ARM_v5e_Prop) ? HIGH : LOW;
262 state->is_v5e = (properties & ARM_v5e_Prop) ? HIGH : LOW; 211 state->is_XScale = (properties & ARM_XScale_Prop) ? HIGH : LOW;
263 state->is_XScale = (properties & ARM_XScale_Prop) ? HIGH : LOW; 212 state->is_iWMMXt = (properties & ARM_iWMMXt_Prop) ? HIGH : LOW;
264 state->is_iWMMXt = (properties & ARM_iWMMXt_Prop) ? HIGH : LOW; 213 /* state->is_v6 = LOW */;
265 /* state->is_v6 = LOW */; 214 /* jeff.du 2010-08-05 */
266 /* jeff.du 2010-08-05 */ 215 state->is_v6 = (properties & ARM_v6_Prop) ? HIGH : LOW;
267 state->is_v6 = (properties & ARM_v6_Prop) ? HIGH : LOW; 216 state->is_ep9312 = (properties & ARM_ep9312_Prop) ? HIGH : LOW;
268 state->is_ep9312 = (properties & ARM_ep9312_Prop) ? HIGH : LOW; 217 //chy 2005-09-19
269 //chy 2005-09-19 218 state->is_pxa27x = (properties & ARM_PXA27X_Prop) ? HIGH : LOW;
270 state->is_pxa27x = (properties & ARM_PXA27X_Prop) ? HIGH : LOW; 219
271 220 /* shenoubang 2012-3-11 */
272 /* shenoubang 2012-3-11 */ 221 state->is_v7 = (properties & ARM_v7_Prop) ? HIGH : LOW;
273 state->is_v7 = (properties & ARM_v7_Prop) ? HIGH : LOW; 222
274 223 /* Only initialse the coprocessor support once we
275 /* Only initialse the coprocessor support once we 224 know what kind of chip we are dealing with. */
276 know what kind of chip we are dealing with. */ 225 //ARMul_CoProInit (state);
277 ARMul_CoProInit (state);
278 226
279} 227}
280 228
@@ -285,66 +233,65 @@ below line sould be in skyeye_mach_XXX.c 's XXX_mach_init function
285void 233void
286ARMul_Reset (ARMul_State * state) 234ARMul_Reset (ARMul_State * state)
287{ 235{
288 //fprintf(stderr,"armul_reset 0: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode); 236 //fprintf(stderr,"armul_reset 0: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode);
289 state->NextInstr = 0; 237 state->NextInstr = 0;
290 if (state->prog32Sig) { 238 if (state->prog32Sig) {
291 state->Reg[15] = 0; 239 state->Reg[15] = 0;
292 state->Cpsr = INTBITS | SVC32MODE; 240 state->Cpsr = INTBITS | SVC32MODE;
293 state->Mode = SVC32MODE; 241 state->Mode = SVC32MODE;
294 } 242 } else {
295 else { 243 state->Reg[15] = R15INTBITS | SVC26MODE;
296 state->Reg[15] = R15INTBITS | SVC26MODE; 244 state->Cpsr = INTBITS | SVC26MODE;
297 state->Cpsr = INTBITS | SVC26MODE; 245 state->Mode = SVC26MODE;
298 state->Mode = SVC26MODE; 246 }
299 } 247 //fprintf(stderr,"armul_reset 1: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode);
300 //fprintf(stderr,"armul_reset 1: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode); 248 //ARMul_CPSRAltered (state);
301 ARMul_CPSRAltered (state); 249 state->Bank = SVCBANK;
302 state->Bank = SVCBANK; 250 FLUSHPIPE;
303 FLUSHPIPE; 251
304 252 state->EndCondition = 0;
305 state->EndCondition = 0; 253 state->ErrorCode = 0;
306 state->ErrorCode = 0; 254
307 255 //fprintf(stderr,"armul_reset 2: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode);
308 //fprintf(stderr,"armul_reset 2: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode); 256 state->NresetSig = HIGH;
309 state->NresetSig = HIGH; 257 state->NfiqSig = HIGH;
310 state->NfiqSig = HIGH; 258 state->NirqSig = HIGH;
311 state->NirqSig = HIGH; 259 state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
312 state->NtransSig = (state->Mode & 3) ? HIGH : LOW; 260 state->abortSig = LOW;
313 state->abortSig = LOW; 261 state->AbortAddr = 1;
314 state->AbortAddr = 1; 262
315 263 state->NumInstrs = 0;
316 state->NumInstrs = 0; 264 state->NumNcycles = 0;
317 state->NumNcycles = 0; 265 state->NumScycles = 0;
318 state->NumScycles = 0; 266 state->NumIcycles = 0;
319 state->NumIcycles = 0; 267 state->NumCcycles = 0;
320 state->NumCcycles = 0; 268 state->NumFcycles = 0;
321 state->NumFcycles = 0; 269
322 270 //fprintf(stderr,"armul_reset 3: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode);
323 //fprintf(stderr,"armul_reset 3: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode); 271 //mmu_reset (state);
324 mmu_reset (state); 272 //fprintf(stderr,"armul_reset 4: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode);
325 //fprintf(stderr,"armul_reset 4: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode); 273
326 274 //mem_reset (state); /* move to memory/ram.c */
327 //mem_reset (state); /* move to memory/ram.c */ 275
328 276 //fprintf(stderr,"armul_reset 5: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode);
329 //fprintf(stderr,"armul_reset 5: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode); 277 /*remove later. walimis 03.7.17 */
330 /*remove later. walimis 03.7.17 */ 278 //io_reset(state);
331 //io_reset(state); 279 //lcd_disable(state);
332 //lcd_disable(state); 280
333 281 /*ywc 2005-04-07 move from ARMul_NewState , because skyeye_config.no_dbct will
334 /*ywc 2005-04-07 move from ARMul_NewState , because skyeye_config.no_dbct will 282 *be configured in skyeye_option_init and it is called after ARMul_NewState*/
335 *be configured in skyeye_option_init and it is called after ARMul_NewState*/ 283 state->tea_break_ok = 0;
336 state->tea_break_ok = 0; 284 state->tea_break_addr = 0;
337 state->tea_break_addr = 0; 285 state->tea_pc = 0;
338 state->tea_pc = 0;
339#ifdef DBCT 286#ifdef DBCT
340 if (!skyeye_config.no_dbct) { 287 if (!skyeye_config.no_dbct) {
341 //teawater add for arm2x86 2005.02.14------------------------------------------- 288 //teawater add for arm2x86 2005.02.14-------------------------------------------
342 if (arm2x86_init (state)) { 289 if (arm2x86_init (state)) {
343 printf ("SKYEYE: arm2x86_init error\n"); 290 printf ("SKYEYE: arm2x86_init error\n");
344 skyeye_exit (-1); 291 //skyeye_exit (-1);
345 } 292 }
346 //AJ2D-------------------------------------------------------------------------- 293 //AJ2D--------------------------------------------------------------------------
347 } 294 }
348#endif 295#endif
349} 296}
350 297
@@ -361,8 +308,9 @@ static ARMul_State *dbct_test_speed_state = NULL;
361static void 308static void
362dbct_test_speed_sig(int signo) 309dbct_test_speed_sig(int signo)
363{ 310{
364 printf("\n0x%llx %llu\n", dbct_test_speed_state->instr_count, dbct_test_speed_state->instr_count); 311 printf("\n0x%llx %llu\n", dbct_test_speed_state->instr_count, dbct_test_speed_state->instr_count);
365 skyeye_exit(0); 312 exit(0);
313 //skyeye_exit(0);
366} 314}
367#endif //DBCT_TEST_SPEED 315#endif //DBCT_TEST_SPEED
368//AJ2D-------------------------------------------------------------------------- 316//AJ2D--------------------------------------------------------------------------
@@ -370,92 +318,91 @@ dbct_test_speed_sig(int signo)
370ARMword 318ARMword
371ARMul_DoProg (ARMul_State * state) 319ARMul_DoProg (ARMul_State * state)
372{ 320{
373 ARMword pc = 0; 321 ARMword pc = 0;
374 322
375 /* 323 /*
376 * 2007-01-24 removed the term-io functions by Anthony Lee, 324 * 2007-01-24 removed the term-io functions by Anthony Lee,
377 * moved to "device/uart/skyeye_uart_stdio.c". 325 * moved to "device/uart/skyeye_uart_stdio.c".
378 */ 326 */
379 327
380//teawater add DBCT_TEST_SPEED 2005.10.04--------------------------------------- 328//teawater add DBCT_TEST_SPEED 2005.10.04---------------------------------------
381#ifdef DBCT_TEST_SPEED 329#ifdef DBCT_TEST_SPEED
382 { 330 {
383 if (!dbct_test_speed_state) { 331 if (!dbct_test_speed_state) {
384 //init timer 332 //init timer
385 struct itimerval value; 333 struct itimerval value;
386 struct sigaction act; 334 struct sigaction act;
387 335
388 dbct_test_speed_state = state; 336 dbct_test_speed_state = state;
389 state->instr_count = 0; 337 state->instr_count = 0;
390 act.sa_handler = dbct_test_speed_sig; 338 act.sa_handler = dbct_test_speed_sig;
391 act.sa_flags = SA_RESTART; 339 act.sa_flags = SA_RESTART;
392 //cygwin don't support ITIMER_VIRTUAL or ITIMER_PROF 340 //cygwin don't support ITIMER_VIRTUAL or ITIMER_PROF
393#ifndef __CYGWIN__ 341#ifndef __CYGWIN__
394 if (sigaction(SIGVTALRM, &act, NULL) == -1) { 342 if (sigaction(SIGVTALRM, &act, NULL) == -1) {
395#else 343#else
396 if (sigaction(SIGALRM, &act, NULL) == -1) { 344 if (sigaction(SIGALRM, &act, NULL) == -1) {
397#endif //__CYGWIN__ 345#endif //__CYGWIN__
398 fprintf(stderr, "init timer error.\n"); 346 fprintf(stderr, "init timer error.\n");
399 skyeye_exit(-1); 347 exit(-1);
400 } 348 //skyeye_exit(-1);
401 if (skyeye_config.dbct_test_speed_sec) { 349 }
402 value.it_value.tv_sec = skyeye_config.dbct_test_speed_sec; 350 if (skyeye_config.dbct_test_speed_sec) {
403 } 351 value.it_value.tv_sec = skyeye_config.dbct_test_speed_sec;
404 else { 352 } else {
405 value.it_value.tv_sec = DBCT_TEST_SPEED_SEC; 353 value.it_value.tv_sec = DBCT_TEST_SPEED_SEC;
406 } 354 }
407 printf("dbct_test_speed_sec = %ld\n", value.it_value.tv_sec); 355 printf("dbct_test_speed_sec = %ld\n", value.it_value.tv_sec);
408 value.it_value.tv_usec = 0; 356 value.it_value.tv_usec = 0;
409 value.it_interval.tv_sec = 0; 357 value.it_interval.tv_sec = 0;
410 value.it_interval.tv_usec = 0; 358 value.it_interval.tv_usec = 0;
411#ifndef __CYGWIN__ 359#ifndef __CYGWIN__
412 if (setitimer(ITIMER_VIRTUAL, &value, NULL) == -1) { 360 if (setitimer(ITIMER_VIRTUAL, &value, NULL) == -1) {
413#else 361#else
414 if (setitimer(ITIMER_REAL, &value, NULL) == -1) { 362 if (setitimer(ITIMER_REAL, &value, NULL) == -1) {
415#endif //__CYGWIN__ 363#endif //__CYGWIN__
416 fprintf(stderr, "init timer error.\n"); 364 fprintf(stderr, "init timer error.\n");
417 skyeye_exit(-1); 365 //skyeye_exit(-1);
418 } 366 }
419 } 367 }
420 } 368 }
421#endif //DBCT_TEST_SPEED 369#endif //DBCT_TEST_SPEED
422//AJ2D-------------------------------------------------------------------------- 370//AJ2D--------------------------------------------------------------------------
423 state->Emulate = RUN; 371 state->Emulate = RUN;
424 while (state->Emulate != STOP) { 372 while (state->Emulate != STOP) {
425 state->Emulate = RUN; 373 state->Emulate = RUN;
426 374
427 /*ywc 2005-03-31 */ 375 /*ywc 2005-03-31 */
428 if (state->prog32Sig && ARMul_MODE32BIT) { 376 if (state->prog32Sig && ARMul_MODE32BIT) {
429#ifdef DBCT 377#ifdef DBCT
430 if (skyeye_config.no_dbct) { 378 if (skyeye_config.no_dbct) {
431 pc = ARMul_Emulate32 (state); 379 pc = ARMul_Emulate32 (state);
432 } 380 } else {
433 else { 381 pc = ARMul_Emulate32_dbct (state);
434 pc = ARMul_Emulate32_dbct (state); 382 }
435 }
436#else 383#else
437 pc = ARMul_Emulate32 (state); 384 pc = ARMul_Emulate32 (state);
438#endif 385#endif
439 } 386 }
440 387
441 else { 388 else {
442 _dbg_assert_msg_(ARM11, false, "Unsupported ARM 26-bit Mode!"); 389 //pc = ARMul_Emulate26 (state);
443 } 390 }
444 //chy 2006-02-22, should test debugmode first 391 //chy 2006-02-22, should test debugmode first
445 //chy 2006-04-14, put below codes in ARMul_Emulate 392 //chy 2006-04-14, put below codes in ARMul_Emulate
446#if 0 393#if 0
447 if(debugmode) 394 if(debugmode)
448 if(remote_interrupt()) 395 if(remote_interrupt())
449 state->Emulate = STOP; 396 state->Emulate = STOP;
450#endif 397#endif
451 } 398 }
452 399
453 /* 400 /*
454 * 2007-01-24 removed the term-io functions by Anthony Lee, 401 * 2007-01-24 removed the term-io functions by Anthony Lee,
455 * moved to "device/uart/skyeye_uart_stdio.c". 402 * moved to "device/uart/skyeye_uart_stdio.c".
456 */ 403 */
457 404
458 return (pc); 405 return (pc);
459} 406}
460 407
461/***************************************************************************\ 408/***************************************************************************\
@@ -467,36 +414,34 @@ ARMul_DoProg (ARMul_State * state)
467ARMword 414ARMword
468ARMul_DoInstr (ARMul_State * state) 415ARMul_DoInstr (ARMul_State * state)
469{ 416{
470 ARMword pc = 0; 417 ARMword pc = 0;
471 418
472 state->Emulate = ONCE; 419 state->Emulate = ONCE;
473 420
474 /*ywc 2005-03-31 */ 421 /*ywc 2005-03-31 */
475 if (state->prog32Sig && ARMul_MODE32BIT) { 422 if (state->prog32Sig && ARMul_MODE32BIT) {
476#ifdef DBCT 423#ifdef DBCT
477 if (skyeye_config.no_dbct) { 424 if (skyeye_config.no_dbct) {
478 pc = ARMul_Emulate32 (state); 425 pc = ARMul_Emulate32 (state);
479 } 426 } else {
480 else {
481//teawater add compile switch for DBCT GDB RSP function 2005.10.21-------------- 427//teawater add compile switch for DBCT GDB RSP function 2005.10.21--------------
482#ifndef DBCT_GDBRSP 428#ifndef DBCT_GDBRSP
483 printf("DBCT GDBRSP function switch is off.\n"); 429 printf("DBCT GDBRSP function switch is off.\n");
484 printf("To use this function, open \"#define DBCT_GDBRSP\" in arch/arm/common/armdefs.h & recompile skyeye.\n"); 430 printf("To use this function, open \"#define DBCT_GDBRSP\" in arch/arm/common/armdefs.h & recompile skyeye.\n");
485 skyeye_exit(-1); 431 skyeye_exit(-1);
486#endif //DBCT_GDBRSP 432#endif //DBCT_GDBRSP
487//AJ2D-------------------------------------------------------------------------- 433//AJ2D--------------------------------------------------------------------------
488 pc = ARMul_Emulate32_dbct (state); 434 pc = ARMul_Emulate32_dbct (state);
489 } 435 }
490#else 436#else
491 pc = ARMul_Emulate32 (state); 437 pc = ARMul_Emulate32 (state);
492#endif 438#endif
493 } 439 }
494 440
495 else { 441 //else
496 _dbg_assert_msg_(ARM11, false, "Unsupported ARM 26-bit Mode!"); 442 //pc = ARMul_Emulate26 (state);
497 }
498 443
499 return (pc); 444 return (pc);
500} 445}
501 446
502/***************************************************************************\ 447/***************************************************************************\
@@ -508,79 +453,74 @@ ARMul_DoInstr (ARMul_State * state)
508void 453void
509ARMul_Abort (ARMul_State * state, ARMword vector) 454ARMul_Abort (ARMul_State * state, ARMword vector)
510{ 455{
511 ARMword temp; 456 ARMword temp;
512 int isize = INSN_SIZE; 457 int isize = INSN_SIZE;
513 int esize = (TFLAG ? 0 : 4); 458 int esize = (TFLAG ? 0 : 4);
514 int e2size = (TFLAG ? -4 : 0); 459 int e2size = (TFLAG ? -4 : 0);
515 460
516 state->Aborted = FALSE; 461 state->Aborted = FALSE;
517 462
518 if (state->prog32Sig) 463 if (state->prog32Sig)
519 if (ARMul_MODE26BIT) 464 if (ARMul_MODE26BIT)
520 temp = R15PC; 465 temp = R15PC;
521 else 466 else
522 temp = state->Reg[15]; 467 temp = state->Reg[15];
523 else 468 else
524 temp = R15PC | ECC | ER15INT | EMODE; 469 temp = R15PC | ECC | ER15INT | EMODE;
525 470
526 switch (vector) { 471 switch (vector) {
527 case ARMul_ResetV: /* RESET */ 472 case ARMul_ResetV: /* RESET */
528 SETABORT (INTBITS, state->prog32Sig ? SVC32MODE : SVC26MODE, 473 SETABORT (INTBITS, state->prog32Sig ? SVC32MODE : SVC26MODE,
529 0); 474 0);
530 break; 475 break;
531 case ARMul_UndefinedInstrV: /* Undefined Instruction */ 476 case ARMul_UndefinedInstrV: /* Undefined Instruction */
532 SETABORT (IBIT, state->prog32Sig ? UNDEF32MODE : SVC26MODE, 477 SETABORT (IBIT, state->prog32Sig ? UNDEF32MODE : SVC26MODE,
533 isize); 478 isize);
534 break; 479 break;
535 case ARMul_SWIV: /* Software Interrupt */ 480 case ARMul_SWIV: /* Software Interrupt */
536 // Modified SETABORT that doesn't branch to a SVC vector as we are implementing this in HLE 481 SETABORT (IBIT, state->prog32Sig ? SVC32MODE : SVC26MODE,
537 // Instead of doing normal routine, backup R15 by one instruction (this is what PC will get 482 isize);
538 // set to, making it the next instruction after the SVC call), and skip setting the LR. 483 break;
539 SETABORT_SKIPBRANCH (IBIT, state->prog32Sig ? SVC32MODE : SVC26MODE, 484 case ARMul_PrefetchAbortV: /* Prefetch Abort */
540 isize); 485 state->AbortAddr = 1;
541 state->Reg[15] -= 4; 486 SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE,
542 return; 487 esize);
543 case ARMul_PrefetchAbortV: /* Prefetch Abort */ 488 break;
544 state->AbortAddr = 1; 489 case ARMul_DataAbortV: /* Data Abort */
545 SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE, 490 SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE,
546 esize); 491 e2size);
547 break; 492 break;
548 case ARMul_DataAbortV: /* Data Abort */ 493 case ARMul_AddrExceptnV: /* Address Exception */
549 SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE, 494 SETABORT (IBIT, SVC26MODE, isize);
550 e2size); 495 break;
551 break; 496 case ARMul_IRQV: /* IRQ */
552 case ARMul_AddrExceptnV: /* Address Exception */ 497 //chy 2003-09-02 the if sentence seems no use
553 SETABORT (IBIT, SVC26MODE, isize);
554 break;
555 case ARMul_IRQV: /* IRQ */
556 //chy 2003-09-02 the if sentence seems no use
557#if 0 498#if 0
558 if (!state->is_XScale || !state->CPRead[13] (state, 0, &temp) 499 if (!state->is_XScale || !state->CPRead[13] (state, 0, &temp)
559 || (temp & ARMul_CP13_R0_IRQ)) 500 || (temp & ARMul_CP13_R0_IRQ))
560#endif 501#endif
561 SETABORT (IBIT, 502 SETABORT (IBIT,
562 state->prog32Sig ? IRQ32MODE : IRQ26MODE, 503 state->prog32Sig ? IRQ32MODE : IRQ26MODE,
563 esize); 504 esize);
564 break; 505 break;
565 case ARMul_FIQV: /* FIQ */ 506 case ARMul_FIQV: /* FIQ */
566 //chy 2003-09-02 the if sentence seems no use 507 //chy 2003-09-02 the if sentence seems no use
567#if 0 508#if 0
568 if (!state->is_XScale || !state->CPRead[13] (state, 0, &temp) 509 if (!state->is_XScale || !state->CPRead[13] (state, 0, &temp)
569 || (temp & ARMul_CP13_R0_FIQ)) 510 || (temp & ARMul_CP13_R0_FIQ))
570#endif 511#endif
571 SETABORT (INTBITS, 512 SETABORT (INTBITS,
572 state->prog32Sig ? FIQ32MODE : FIQ26MODE, 513 state->prog32Sig ? FIQ32MODE : FIQ26MODE,
573 esize); 514 esize);
574 break; 515 break;
575 } 516 }
576 517
577 if (ARMul_MODE32BIT) { 518 if (ARMul_MODE32BIT) {
578 if (state->mmu.control & CONTROL_VECTOR) 519 /*if (state->mmu.control & CONTROL_VECTOR)
579 vector += 0xffff0000; //for v4 high exception address 520 vector += 0xffff0000; //for v4 high exception address*/
580 if (state->vector_remap_flag) 521 if (state->vector_remap_flag)
581 vector += state->vector_remap_addr; /* support some remap function in LPC processor */ 522 vector += state->vector_remap_addr; /* support some remap function in LPC processor */
582 ARMul_SetR15 (state, vector); 523 ARMul_SetR15 (state, vector);
583 } 524 } else
584 else 525 ARMul_SetR15 (state, R15CCINTMODE | vector);
585 ARMul_SetR15 (state, R15CCINTMODE | vector);
586} 526}
diff --git a/src/core/arm/interpreter/armsupp.cpp b/src/core/arm/interpreter/armsupp.cpp
index 7816c4c42..219ba78ce 100644
--- a/src/core/arm/interpreter/armsupp.cpp
+++ b/src/core/arm/interpreter/armsupp.cpp
@@ -1,38 +1,39 @@
1/* armsupp.c -- ARMulator support code: ARM6 Instruction Emulator. 1/* armsupp.c -- ARMulator support code: ARM6 Instruction Emulator.
2 Copyright (C) 1994 Advanced RISC Machines Ltd. 2 Copyright (C) 1994 Advanced RISC Machines Ltd.
3 3
4 This program is free software; you can redistribute it and/or modify 4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by 5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or 6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version. 7 (at your option) any later version.
8 8
9 This program is distributed in the hope that it will be useful, 9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of 10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details. 12 GNU General Public License for more details.
13 13
14 You should have received a copy of the GNU General Public License 14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software 15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
17 17
18//#include <util.h>
19
18#include "core/arm/interpreter/armdefs.h" 20#include "core/arm/interpreter/armdefs.h"
19#include "core/arm/interpreter/armemu.h" 21#include "core/arm/interpreter/armemu.h"
20#include "core/arm/interpreter/skyeye_defs.h"
21#include "core/hle/coprocessor.h" 22#include "core/hle/coprocessor.h"
22#include "core/arm/disassembler/arm_disasm.h" 23#include "core/arm/disassembler/arm_disasm.h"
23 24
24unsigned xscale_cp15_cp_access_allowed (ARMul_State * state, unsigned reg, 25//#include "ansidecl.h"
25 unsigned cpnum); 26//#include "skyeye.h"
26//extern int skyeye_instr_debug; 27//extern int skyeye_instr_debug;
27/* Definitions for the support routines. */ 28/* Definitions for the support routines. */
28 29
29static ARMword ModeToBank (ARMword); 30static ARMword ModeToBank (ARMword);
30static void EnvokeList (ARMul_State *, unsigned int, unsigned int); 31static void EnvokeList (ARMul_State *, unsigned int, unsigned int);
31 32
32struct EventNode 33struct EventNode {
33{ /* An event list node. */ 34 /* An event list node. */
34 unsigned (*func) (ARMul_State *); /* The function to call. */ 35 unsigned (*func) (ARMul_State *); /* The function to call. */
35 struct EventNode *next; 36 struct EventNode *next;
36}; 37};
37 38
38/* This routine returns the value of a register from a mode. */ 39/* This routine returns the value of a register from a mode. */
@@ -40,11 +41,11 @@ struct EventNode
40ARMword 41ARMword
41ARMul_GetReg (ARMul_State * state, unsigned mode, unsigned reg) 42ARMul_GetReg (ARMul_State * state, unsigned mode, unsigned reg)
42{ 43{
43 mode &= MODEBITS; 44 mode &= MODEBITS;
44 if (mode != state->Mode) 45 if (mode != state->Mode)
45 return (state->RegBank[ModeToBank ((ARMword) mode)][reg]); 46 return (state->RegBank[ModeToBank ((ARMword) mode)][reg]);
46 else 47 else
47 return (state->Reg[reg]); 48 return (state->Reg[reg]);
48} 49}
49 50
50/* This routine sets the value of a register for a mode. */ 51/* This routine sets the value of a register for a mode. */
@@ -52,11 +53,11 @@ ARMul_GetReg (ARMul_State * state, unsigned mode, unsigned reg)
52void 53void
53ARMul_SetReg (ARMul_State * state, unsigned mode, unsigned reg, ARMword value) 54ARMul_SetReg (ARMul_State * state, unsigned mode, unsigned reg, ARMword value)
54{ 55{
55 mode &= MODEBITS; 56 mode &= MODEBITS;
56 if (mode != state->Mode) 57 if (mode != state->Mode)
57 state->RegBank[ModeToBank ((ARMword) mode)][reg] = value; 58 state->RegBank[ModeToBank ((ARMword) mode)][reg] = value;
58 else 59 else
59 state->Reg[reg] = value; 60 state->Reg[reg] = value;
60} 61}
61 62
62/* This routine returns the value of the PC, mode independently. */ 63/* This routine returns the value of the PC, mode independently. */
@@ -64,10 +65,10 @@ ARMul_SetReg (ARMul_State * state, unsigned mode, unsigned reg, ARMword value)
64ARMword 65ARMword
65ARMul_GetPC (ARMul_State * state) 66ARMul_GetPC (ARMul_State * state)
66{ 67{
67 if (state->Mode > SVC26MODE) 68 if (state->Mode > SVC26MODE)
68 return state->Reg[15]; 69 return state->Reg[15];
69 else 70 else
70 return R15PC; 71 return R15PC;
71} 72}
72 73
73/* This routine returns the value of the PC, mode independently. */ 74/* This routine returns the value of the PC, mode independently. */
@@ -75,10 +76,10 @@ ARMul_GetPC (ARMul_State * state)
75ARMword 76ARMword
76ARMul_GetNextPC (ARMul_State * state) 77ARMul_GetNextPC (ARMul_State * state)
77{ 78{
78 if (state->Mode > SVC26MODE) 79 if (state->Mode > SVC26MODE)
79 return state->Reg[15] + isize; 80 return state->Reg[15] + INSN_SIZE;
80 else 81 else
81 return (state->Reg[15] + isize) & R15PCBITS; 82 return (state->Reg[15] + INSN_SIZE) & R15PCBITS;
82} 83}
83 84
84/* This routine sets the value of the PC. */ 85/* This routine sets the value of the PC. */
@@ -86,11 +87,11 @@ ARMul_GetNextPC (ARMul_State * state)
86void 87void
87ARMul_SetPC (ARMul_State * state, ARMword value) 88ARMul_SetPC (ARMul_State * state, ARMword value)
88{ 89{
89 if (ARMul_MODE32BIT) 90 if (ARMul_MODE32BIT)
90 state->Reg[15] = value & PCBITS; 91 state->Reg[15] = value & PCBITS;
91 else 92 else
92 state->Reg[15] = R15CCINTMODE | (value & R15PCBITS); 93 state->Reg[15] = R15CCINTMODE | (value & R15PCBITS);
93 FLUSHPIPE; 94 FLUSHPIPE;
94} 95}
95 96
96/* This routine returns the value of register 15, mode independently. */ 97/* This routine returns the value of register 15, mode independently. */
@@ -98,10 +99,10 @@ ARMul_SetPC (ARMul_State * state, ARMword value)
98ARMword 99ARMword
99ARMul_GetR15 (ARMul_State * state) 100ARMul_GetR15 (ARMul_State * state)
100{ 101{
101 if (state->Mode > SVC26MODE) 102 if (state->Mode > SVC26MODE)
102 return (state->Reg[15]); 103 return (state->Reg[15]);
103 else 104 else
104 return (R15PC | ECC | ER15INT | EMODE); 105 return (R15PC | ECC | ER15INT | EMODE);
105} 106}
106 107
107/* This routine sets the value of Register 15. */ 108/* This routine sets the value of Register 15. */
@@ -109,13 +110,13 @@ ARMul_GetR15 (ARMul_State * state)
109void 110void
110ARMul_SetR15 (ARMul_State * state, ARMword value) 111ARMul_SetR15 (ARMul_State * state, ARMword value)
111{ 112{
112 if (ARMul_MODE32BIT) 113 if (ARMul_MODE32BIT)
113 state->Reg[15] = value & PCBITS; 114 state->Reg[15] = value & PCBITS;
114 else { 115 else {
115 state->Reg[15] = value; 116 state->Reg[15] = value;
116 ARMul_R15Altered (state); 117 ARMul_R15Altered (state);
117 } 118 }
118 FLUSHPIPE; 119 FLUSHPIPE;
119} 120}
120 121
121/* This routine returns the value of the CPSR. */ 122/* This routine returns the value of the CPSR. */
@@ -123,9 +124,9 @@ ARMul_SetR15 (ARMul_State * state, ARMword value)
123ARMword 124ARMword
124ARMul_GetCPSR (ARMul_State * state) 125ARMul_GetCPSR (ARMul_State * state)
125{ 126{
126 //chy 2003-08-20: below is from gdb20030716, maybe isn't suitable for system simulator 127 //chy 2003-08-20: below is from gdb20030716, maybe isn't suitable for system simulator
127 //return (CPSR | state->Cpsr); for gdb20030716 128 //return (CPSR | state->Cpsr); for gdb20030716
128 return (CPSR); //had be tested in old skyeye with gdb5.0-5.3 129 return (CPSR); //had be tested in old skyeye with gdb5.0-5.3
129} 130}
130 131
131/* This routine sets the value of the CPSR. */ 132/* This routine sets the value of the CPSR. */
@@ -133,8 +134,8 @@ ARMul_GetCPSR (ARMul_State * state)
133void 134void
134ARMul_SetCPSR (ARMul_State * state, ARMword value) 135ARMul_SetCPSR (ARMul_State * state, ARMword value)
135{ 136{
136 state->Cpsr = value; 137 state->Cpsr = value;
137 ARMul_CPSRAltered (state); 138 ARMul_CPSRAltered (state);
138} 139}
139 140
140/* This routine does all the nasty bits involved in a write to the CPSR, 141/* This routine does all the nasty bits involved in a write to the CPSR,
@@ -143,20 +144,20 @@ ARMul_SetCPSR (ARMul_State * state, ARMword value)
143void 144void
144ARMul_FixCPSR (ARMul_State * state, ARMword instr, ARMword rhs) 145ARMul_FixCPSR (ARMul_State * state, ARMword instr, ARMword rhs)
145{ 146{
146 state->Cpsr = ARMul_GetCPSR (state); 147 state->Cpsr = ARMul_GetCPSR (state);
147 //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode 148 //chy 2006-02-16 , should not consider system mode, don't conside 26bit mode
148 if (state->Mode != USER26MODE && state->Mode != USER32MODE ) { 149 if (state->Mode != USER26MODE && state->Mode != USER32MODE ) {
149 /* In user mode, only write flags. */ 150 /* In user mode, only write flags. */
150 if (BIT (16)) 151 if (BIT (16))
151 SETPSR_C (state->Cpsr, rhs); 152 SETPSR_C (state->Cpsr, rhs);
152 if (BIT (17)) 153 if (BIT (17))
153 SETPSR_X (state->Cpsr, rhs); 154 SETPSR_X (state->Cpsr, rhs);
154 if (BIT (18)) 155 if (BIT (18))
155 SETPSR_S (state->Cpsr, rhs); 156 SETPSR_S (state->Cpsr, rhs);
156 } 157 }
157 if (BIT (19)) 158 if (BIT (19))
158 SETPSR_F (state->Cpsr, rhs); 159 SETPSR_F (state->Cpsr, rhs);
159 ARMul_CPSRAltered (state); 160 ARMul_CPSRAltered (state);
160} 161}
161 162
162/* Get an SPSR from the specified mode. */ 163/* Get an SPSR from the specified mode. */
@@ -164,12 +165,12 @@ ARMul_FixCPSR (ARMul_State * state, ARMword instr, ARMword rhs)
164ARMword 165ARMword
165ARMul_GetSPSR (ARMul_State * state, ARMword mode) 166ARMul_GetSPSR (ARMul_State * state, ARMword mode)
166{ 167{
167 ARMword bank = ModeToBank (mode & MODEBITS); 168 ARMword bank = ModeToBank (mode & MODEBITS);
168 169
169 if (!BANK_CAN_ACCESS_SPSR (bank)) 170 if (!BANK_CAN_ACCESS_SPSR (bank))
170 return ARMul_GetCPSR (state); 171 return ARMul_GetCPSR (state);
171 172
172 return state->Spsr[bank]; 173 return state->Spsr[bank];
173} 174}
174 175
175/* This routine does a write to an SPSR. */ 176/* This routine does a write to an SPSR. */
@@ -177,10 +178,10 @@ ARMul_GetSPSR (ARMul_State * state, ARMword mode)
177void 178void
178ARMul_SetSPSR (ARMul_State * state, ARMword mode, ARMword value) 179ARMul_SetSPSR (ARMul_State * state, ARMword mode, ARMword value)
179{ 180{
180 ARMword bank = ModeToBank (mode & MODEBITS); 181 ARMword bank = ModeToBank (mode & MODEBITS);
181 182
182 if (BANK_CAN_ACCESS_SPSR (bank)) 183 if (BANK_CAN_ACCESS_SPSR (bank))
183 state->Spsr[bank] = value; 184 state->Spsr[bank] = value;
184} 185}
185 186
186/* This routine does a write to the current SPSR, given an MSR instruction. */ 187/* This routine does a write to the current SPSR, given an MSR instruction. */
@@ -188,16 +189,16 @@ ARMul_SetSPSR (ARMul_State * state, ARMword mode, ARMword value)
188void 189void
189ARMul_FixSPSR (ARMul_State * state, ARMword instr, ARMword rhs) 190ARMul_FixSPSR (ARMul_State * state, ARMword instr, ARMword rhs)
190{ 191{
191 if (BANK_CAN_ACCESS_SPSR (state->Bank)) { 192 if (BANK_CAN_ACCESS_SPSR (state->Bank)) {
192 if (BIT (16)) 193 if (BIT (16))
193 SETPSR_C (state->Spsr[state->Bank], rhs); 194 SETPSR_C (state->Spsr[state->Bank], rhs);
194 if (BIT (17)) 195 if (BIT (17))
195 SETPSR_X (state->Spsr[state->Bank], rhs); 196 SETPSR_X (state->Spsr[state->Bank], rhs);
196 if (BIT (18)) 197 if (BIT (18))
197 SETPSR_S (state->Spsr[state->Bank], rhs); 198 SETPSR_S (state->Spsr[state->Bank], rhs);
198 if (BIT (19)) 199 if (BIT (19))
199 SETPSR_F (state->Spsr[state->Bank], rhs); 200 SETPSR_F (state->Spsr[state->Bank], rhs);
200 } 201 }
201} 202}
202 203
203/* This routine updates the state of the emulator after the Cpsr has been 204/* This routine updates the state of the emulator after the Cpsr has been
@@ -206,53 +207,51 @@ ARMul_FixSPSR (ARMul_State * state, ARMword instr, ARMword rhs)
206void 207void
207ARMul_CPSRAltered (ARMul_State * state) 208ARMul_CPSRAltered (ARMul_State * state)
208{ 209{
209 ARMword oldmode; 210 ARMword oldmode;
210 211
211 if (state->prog32Sig == LOW) 212 if (state->prog32Sig == LOW)
212 state->Cpsr &= (CCBITS | INTBITS | R15MODEBITS); 213 state->Cpsr &= (CCBITS | INTBITS | R15MODEBITS);
213 214
214 oldmode = state->Mode; 215 oldmode = state->Mode;
215 216
216 if (state->Mode != (state->Cpsr & MODEBITS)) { 217 /*if (state->Mode != (state->Cpsr & MODEBITS)) {
217 state->Mode = 218 state->Mode =
218 ARMul_SwitchMode (state, state->Mode, 219 ARMul_SwitchMode (state, state->Mode,
219 state->Cpsr & MODEBITS); 220 state->Cpsr & MODEBITS);
220 221
221 state->NtransSig = (state->Mode & 3) ? HIGH : LOW; 222 state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
222 } 223 }*/
223 //state->Cpsr &= ~MODEBITS; 224 //state->Cpsr &= ~MODEBITS;
224 225
225 ASSIGNINT (state->Cpsr & INTBITS); 226 ASSIGNINT (state->Cpsr & INTBITS);
226 //state->Cpsr &= ~INTBITS; 227 //state->Cpsr &= ~INTBITS;
227 ASSIGNN ((state->Cpsr & NBIT) != 0); 228 ASSIGNN ((state->Cpsr & NBIT) != 0);
228 //state->Cpsr &= ~NBIT; 229 //state->Cpsr &= ~NBIT;
229 ASSIGNZ ((state->Cpsr & ZBIT) != 0); 230 ASSIGNZ ((state->Cpsr & ZBIT) != 0);
230 //state->Cpsr &= ~ZBIT; 231 //state->Cpsr &= ~ZBIT;
231 ASSIGNC ((state->Cpsr & CBIT) != 0); 232 ASSIGNC ((state->Cpsr & CBIT) != 0);
232 //state->Cpsr &= ~CBIT; 233 //state->Cpsr &= ~CBIT;
233 ASSIGNV ((state->Cpsr & VBIT) != 0); 234 ASSIGNV ((state->Cpsr & VBIT) != 0);
234 //state->Cpsr &= ~VBIT; 235 //state->Cpsr &= ~VBIT;
235 ASSIGNS ((state->Cpsr & SBIT) != 0); 236 ASSIGNS ((state->Cpsr & SBIT) != 0);
236 //state->Cpsr &= ~SBIT; 237 //state->Cpsr &= ~SBIT;
237#ifdef MODET 238#ifdef MODET
238 ASSIGNT ((state->Cpsr & TBIT) != 0); 239 ASSIGNT ((state->Cpsr & TBIT) != 0);
239 //state->Cpsr &= ~TBIT; 240 //state->Cpsr &= ~TBIT;
240#endif 241#endif
241 242
242 if (oldmode > SVC26MODE) { 243 if (oldmode > SVC26MODE) {
243 if (state->Mode <= SVC26MODE) { 244 if (state->Mode <= SVC26MODE) {
244 state->Emulate = CHANGEMODE; 245 state->Emulate = CHANGEMODE;
245 state->Reg[15] = ECC | ER15INT | EMODE | R15PC; 246 state->Reg[15] = ECC | ER15INT | EMODE | R15PC;
246 } 247 }
247 } 248 } else {
248 else { 249 if (state->Mode > SVC26MODE) {
249 if (state->Mode > SVC26MODE) { 250 state->Emulate = CHANGEMODE;
250 state->Emulate = CHANGEMODE; 251 state->Reg[15] = R15PC;
251 state->Reg[15] = R15PC; 252 } else
252 } 253 state->Reg[15] = ECC | ER15INT | EMODE | R15PC;
253 else 254 }
254 state->Reg[15] = ECC | ER15INT | EMODE | R15PC;
255 }
256} 255}
257 256
258/* This routine updates the state of the emulator after register 15 has 257/* This routine updates the state of the emulator after register 15 has
@@ -262,20 +261,20 @@ ARMul_CPSRAltered (ARMul_State * state)
262void 261void
263ARMul_R15Altered (ARMul_State * state) 262ARMul_R15Altered (ARMul_State * state)
264{ 263{
265 if (state->Mode != R15MODE) { 264 if (state->Mode != R15MODE) {
266 state->Mode = ARMul_SwitchMode (state, state->Mode, R15MODE); 265 state->Mode = ARMul_SwitchMode (state, state->Mode, R15MODE);
267 state->NtransSig = (state->Mode & 3) ? HIGH : LOW; 266 state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
268 } 267 }
269 268
270 if (state->Mode > SVC26MODE) 269 if (state->Mode > SVC26MODE)
271 state->Emulate = CHANGEMODE; 270 state->Emulate = CHANGEMODE;
272 271
273 ASSIGNR15INT (R15INT); 272 ASSIGNR15INT (R15INT);
274 273
275 ASSIGNN ((state->Reg[15] & NBIT) != 0); 274 ASSIGNN ((state->Reg[15] & NBIT) != 0);
276 ASSIGNZ ((state->Reg[15] & ZBIT) != 0); 275 ASSIGNZ ((state->Reg[15] & ZBIT) != 0);
277 ASSIGNC ((state->Reg[15] & CBIT) != 0); 276 ASSIGNC ((state->Reg[15] & CBIT) != 0);
278 ASSIGNV ((state->Reg[15] & VBIT) != 0); 277 ASSIGNV ((state->Reg[15] & VBIT) != 0);
279} 278}
280 279
281/* This routine controls the saving and restoring of registers across mode 280/* This routine controls the saving and restoring of registers across mode
@@ -287,78 +286,78 @@ ARMul_R15Altered (ARMul_State * state)
287ARMword 286ARMword
288ARMul_SwitchMode (ARMul_State * state, ARMword oldmode, ARMword newmode) 287ARMul_SwitchMode (ARMul_State * state, ARMword oldmode, ARMword newmode)
289{ 288{
290 unsigned i; 289 unsigned i;
291 ARMword oldbank; 290 ARMword oldbank;
292 ARMword newbank; 291 ARMword newbank;
293 static int revision_value = 53; 292 static int revision_value = 53;
294 293
295 oldbank = ModeToBank (oldmode); 294 oldbank = ModeToBank (oldmode);
296 newbank = state->Bank = ModeToBank (newmode); 295 newbank = state->Bank = ModeToBank (newmode);
297 296
298 /* Do we really need to do it? */ 297 /* Do we really need to do it? */
299 if (oldbank != newbank) { 298 if (oldbank != newbank) {
300 if (oldbank == 3 && newbank == 2) { 299 if (oldbank == 3 && newbank == 2) {
301 //printf("icounter is %d PC is %x MODE CHANGED : %d --> %d\n", state->NumInstrs, state->pc, oldbank, newbank); 300 //printf("icounter is %d PC is %x MODE CHANGED : %d --> %d\n", state->NumInstrs, state->pc, oldbank, newbank);
302 if (state->NumInstrs >= 5832487) { 301 if (state->NumInstrs >= 5832487) {
303// printf("%d, ", state->NumInstrs + revision_value); 302// printf("%d, ", state->NumInstrs + revision_value);
304// printf("revision_value : %d\n", revision_value); 303// printf("revision_value : %d\n", revision_value);
305 revision_value ++; 304 revision_value ++;
306 } 305 }
307 } 306 }
308 /* Save away the old registers. */ 307 /* Save away the old registers. */
309 switch (oldbank) { 308 switch (oldbank) {
310 case USERBANK: 309 case USERBANK:
311 case IRQBANK: 310 case IRQBANK:
312 case SVCBANK: 311 case SVCBANK:
313 case ABORTBANK: 312 case ABORTBANK:
314 case UNDEFBANK: 313 case UNDEFBANK:
315 if (newbank == FIQBANK) 314 if (newbank == FIQBANK)
316 for (i = 8; i < 13; i++) 315 for (i = 8; i < 13; i++)
317 state->RegBank[USERBANK][i] = 316 state->RegBank[USERBANK][i] =
318 state->Reg[i]; 317 state->Reg[i];
319 state->RegBank[oldbank][13] = state->Reg[13]; 318 state->RegBank[oldbank][13] = state->Reg[13];
320 state->RegBank[oldbank][14] = state->Reg[14]; 319 state->RegBank[oldbank][14] = state->Reg[14];
321 break; 320 break;
322 case FIQBANK: 321 case FIQBANK:
323 for (i = 8; i < 15; i++) 322 for (i = 8; i < 15; i++)
324 state->RegBank[FIQBANK][i] = state->Reg[i]; 323 state->RegBank[FIQBANK][i] = state->Reg[i];
325 break; 324 break;
326 case DUMMYBANK: 325 case DUMMYBANK:
327 for (i = 8; i < 15; i++) 326 for (i = 8; i < 15; i++)
328 state->RegBank[DUMMYBANK][i] = 0; 327 state->RegBank[DUMMYBANK][i] = 0;
329 break; 328 break;
330 default: 329 default:
331 abort (); 330 abort ();
332 } 331 }
333 332
334 /* Restore the new registers. */ 333 /* Restore the new registers. */
335 switch (newbank) { 334 switch (newbank) {
336 case USERBANK: 335 case USERBANK:
337 case IRQBANK: 336 case IRQBANK:
338 case SVCBANK: 337 case SVCBANK:
339 case ABORTBANK: 338 case ABORTBANK:
340 case UNDEFBANK: 339 case UNDEFBANK:
341 if (oldbank == FIQBANK) 340 if (oldbank == FIQBANK)
342 for (i = 8; i < 13; i++) 341 for (i = 8; i < 13; i++)
343 state->Reg[i] = 342 state->Reg[i] =
344 state->RegBank[USERBANK][i]; 343 state->RegBank[USERBANK][i];
345 state->Reg[13] = state->RegBank[newbank][13]; 344 state->Reg[13] = state->RegBank[newbank][13];
346 state->Reg[14] = state->RegBank[newbank][14]; 345 state->Reg[14] = state->RegBank[newbank][14];
347 break; 346 break;
348 case FIQBANK: 347 case FIQBANK:
349 for (i = 8; i < 15; i++) 348 for (i = 8; i < 15; i++)
350 state->Reg[i] = state->RegBank[FIQBANK][i]; 349 state->Reg[i] = state->RegBank[FIQBANK][i];
351 break; 350 break;
352 case DUMMYBANK: 351 case DUMMYBANK:
353 for (i = 8; i < 15; i++) 352 for (i = 8; i < 15; i++)
354 state->Reg[i] = 0; 353 state->Reg[i] = 0;
355 break; 354 break;
356 default: 355 default:
357 abort (); 356 abort ();
358 } 357 }
359 } 358 }
360 359
361 return newmode; 360 return newmode;
362} 361}
363 362
364/* Given a processor mode, this routine returns the 363/* Given a processor mode, this routine returns the
@@ -367,21 +366,21 @@ ARMul_SwitchMode (ARMul_State * state, ARMword oldmode, ARMword newmode)
367static ARMword 366static ARMword
368ModeToBank (ARMword mode) 367ModeToBank (ARMword mode)
369{ 368{
370 static ARMword bankofmode[] = { 369 static ARMword bankofmode[] = {
371 USERBANK, FIQBANK, IRQBANK, SVCBANK, 370 USERBANK, FIQBANK, IRQBANK, SVCBANK,
372 DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK, 371 DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK,
373 DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK, 372 DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK,
374 DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK, 373 DUMMYBANK, DUMMYBANK, DUMMYBANK, DUMMYBANK,
375 USERBANK, FIQBANK, IRQBANK, SVCBANK, 374 USERBANK, FIQBANK, IRQBANK, SVCBANK,
376 DUMMYBANK, DUMMYBANK, DUMMYBANK, ABORTBANK, 375 DUMMYBANK, DUMMYBANK, DUMMYBANK, ABORTBANK,
377 DUMMYBANK, DUMMYBANK, DUMMYBANK, UNDEFBANK, 376 DUMMYBANK, DUMMYBANK, DUMMYBANK, UNDEFBANK,
378 DUMMYBANK, DUMMYBANK, DUMMYBANK, SYSTEMBANK 377 DUMMYBANK, DUMMYBANK, DUMMYBANK, SYSTEMBANK
379 }; 378 };
380 379
381 if (mode >= (sizeof (bankofmode) / sizeof (bankofmode[0]))) 380 if (mode >= (sizeof (bankofmode) / sizeof (bankofmode[0])))
382 return DUMMYBANK; 381 return DUMMYBANK;
383 382
384 return bankofmode[mode]; 383 return bankofmode[mode];
385} 384}
386 385
387/* Returns the register number of the nth register in a reg list. */ 386/* Returns the register number of the nth register in a reg list. */
@@ -389,13 +388,13 @@ ModeToBank (ARMword mode)
389unsigned 388unsigned
390ARMul_NthReg (ARMword instr, unsigned number) 389ARMul_NthReg (ARMword instr, unsigned number)
391{ 390{
392 unsigned bit, upto; 391 unsigned bit, upto;
393 392
394 for (bit = 0, upto = 0; upto <= number; bit++) 393 for (bit = 0, upto = 0; upto <= number; bit++)
395 if (BIT (bit)) 394 if (BIT (bit))
396 upto++; 395 upto++;
397 396
398 return (bit - 1); 397 return (bit - 1);
399} 398}
400 399
401/* Assigns the N and Z flags depending on the value of result. */ 400/* Assigns the N and Z flags depending on the value of result. */
@@ -403,18 +402,16 @@ ARMul_NthReg (ARMword instr, unsigned number)
403void 402void
404ARMul_NegZero (ARMul_State * state, ARMword result) 403ARMul_NegZero (ARMul_State * state, ARMword result)
405{ 404{
406 if (NEG (result)) { 405 if (NEG (result)) {
407 SETN; 406 SETN;
408 CLEARZ; 407 CLEARZ;
409 } 408 } else if (result == 0) {
410 else if (result == 0) { 409 CLEARN;
411 CLEARN; 410 SETZ;
412 SETZ; 411 } else {
413 } 412 CLEARN;
414 else { 413 CLEARZ;
415 CLEARN; 414 }
416 CLEARZ;
417 }
418} 415}
419 416
420/* Compute whether an addition of A and B, giving RESULT, overflowed. */ 417/* Compute whether an addition of A and B, giving RESULT, overflowed. */
@@ -422,8 +419,8 @@ ARMul_NegZero (ARMul_State * state, ARMword result)
422int 419int
423AddOverflow (ARMword a, ARMword b, ARMword result) 420AddOverflow (ARMword a, ARMword b, ARMword result)
424{ 421{
425 return ((NEG (a) && NEG (b) && POS (result)) 422 return ((NEG (a) && NEG (b) && POS (result))
426 || (POS (a) && POS (b) && NEG (result))); 423 || (POS (a) && POS (b) && NEG (result)));
427} 424}
428 425
429/* Compute whether a subtraction of A and B, giving RESULT, overflowed. */ 426/* Compute whether a subtraction of A and B, giving RESULT, overflowed. */
@@ -431,8 +428,8 @@ AddOverflow (ARMword a, ARMword b, ARMword result)
431int 428int
432SubOverflow (ARMword a, ARMword b, ARMword result) 429SubOverflow (ARMword a, ARMword b, ARMword result)
433{ 430{
434 return ((NEG (a) && POS (b) && POS (result)) 431 return ((NEG (a) && POS (b) && POS (result))
435 || (POS (a) && NEG (b) && NEG (result))); 432 || (POS (a) && NEG (b) && NEG (result)));
436} 433}
437 434
438/* Assigns the C flag after an addition of a and b to give result. */ 435/* Assigns the C flag after an addition of a and b to give result. */
@@ -440,8 +437,8 @@ SubOverflow (ARMword a, ARMword b, ARMword result)
440void 437void
441ARMul_AddCarry (ARMul_State * state, ARMword a, ARMword b, ARMword result) 438ARMul_AddCarry (ARMul_State * state, ARMword a, ARMword b, ARMword result)
442{ 439{
443 ASSIGNC ((NEG (a) && NEG (b)) || 440 ASSIGNC ((NEG (a) && NEG (b)) ||
444 (NEG (a) && POS (result)) || (NEG (b) && POS (result))); 441 (NEG (a) && POS (result)) || (NEG (b) && POS (result)));
445} 442}
446 443
447/* Assigns the V flag after an addition of a and b to give result. */ 444/* Assigns the V flag after an addition of a and b to give result. */
@@ -449,7 +446,7 @@ ARMul_AddCarry (ARMul_State * state, ARMword a, ARMword b, ARMword result)
449void 446void
450ARMul_AddOverflow (ARMul_State * state, ARMword a, ARMword b, ARMword result) 447ARMul_AddOverflow (ARMul_State * state, ARMword a, ARMword b, ARMword result)
451{ 448{
452 ASSIGNV (AddOverflow (a, b, result)); 449 ASSIGNV (AddOverflow (a, b, result));
453} 450}
454 451
455/* Assigns the C flag after an subtraction of a and b to give result. */ 452/* Assigns the C flag after an subtraction of a and b to give result. */
@@ -457,8 +454,8 @@ ARMul_AddOverflow (ARMul_State * state, ARMword a, ARMword b, ARMword result)
457void 454void
458ARMul_SubCarry (ARMul_State * state, ARMword a, ARMword b, ARMword result) 455ARMul_SubCarry (ARMul_State * state, ARMword a, ARMword b, ARMword result)
459{ 456{
460 ASSIGNC ((NEG (a) && POS (b)) || 457 ASSIGNC ((NEG (a) && POS (b)) ||
461 (NEG (a) && POS (result)) || (POS (b) && POS (result))); 458 (NEG (a) && POS (result)) || (POS (b) && POS (result)));
462} 459}
463 460
464/* Assigns the V flag after an subtraction of a and b to give result. */ 461/* Assigns the V flag after an subtraction of a and b to give result. */
@@ -466,7 +463,7 @@ ARMul_SubCarry (ARMul_State * state, ARMword a, ARMword b, ARMword result)
466void 463void
467ARMul_SubOverflow (ARMul_State * state, ARMword a, ARMword b, ARMword result) 464ARMul_SubOverflow (ARMul_State * state, ARMword a, ARMword b, ARMword result)
468{ 465{
469 ASSIGNV (SubOverflow (a, b, result)); 466 ASSIGNV (SubOverflow (a, b, result));
470} 467}
471 468
472/* This function does the work of generating the addresses used in an 469/* This function does the work of generating the addresses used in an
@@ -477,88 +474,88 @@ ARMul_SubOverflow (ARMul_State * state, ARMword a, ARMword b, ARMword result)
477void 474void
478ARMul_LDC (ARMul_State * state, ARMword instr, ARMword address) 475ARMul_LDC (ARMul_State * state, ARMword instr, ARMword address)
479{ 476{
480 unsigned cpab; 477 unsigned cpab;
481 ARMword data; 478 ARMword data;
482 479
483 UNDEF_LSCPCBaseWb; 480 UNDEF_LSCPCBaseWb;
484 //printf("SKYEYE ARMul_LDC, CPnum is %x, instr %x, addr %x\n",CPNum, instr, address); 481 //printf("SKYEYE ARMul_LDC, CPnum is %x, instr %x, addr %x\n",CPNum, instr, address);
485/*chy 2004-05-23 should update this function in the future,should concern dataabort*/ 482 /*chy 2004-05-23 should update this function in the future,should concern dataabort*/
486// chy 2004-05-25 , fix it now,so needn't printf 483// chy 2004-05-25 , fix it now,so needn't printf
487// printf("SKYEYE ARMul_LDC, should update this function!!!!!\n"); 484// printf("SKYEYE ARMul_LDC, should update this function!!!!!\n");
488 //exit(-1); 485 //exit(-1);
489 486
490 if (!CP_ACCESS_ALLOWED (state, CPNum)) { 487 //if (!CP_ACCESS_ALLOWED (state, CPNum)) {
491 /* 488 if (!state->LDC[CPNum]) {
492 printf 489 /*
493 ("SKYEYE ARMul_LDC,NOT ALLOW, underinstr, CPnum is %x, instr %x, addr %x\n", 490 printf
494 CPNum, instr, address); 491 ("SKYEYE ARMul_LDC,NOT ALLOW, underinstr, CPnum is %x, instr %x, addr %x\n",
495 */ 492 CPNum, instr, address);
496 ARMul_UndefInstr (state, instr); 493 */
497 return; 494 ARMul_UndefInstr (state, instr);
498 } 495 return;
499 496 }
500 //if (ADDREXCEPT (address)) 497
501 // INTERNALABORT (address); 498 /*if (ADDREXCEPT (address))
502 499 INTERNALABORT (address);*/
503 cpab = (state->LDC[CPNum]) (state, ARMul_FIRST, instr, 0); 500
504 while (cpab == ARMul_BUSY) { 501 cpab = (state->LDC[CPNum]) (state, ARMul_FIRST, instr, 0);
505 ARMul_Icycles (state, 1, 0); 502 while (cpab == ARMul_BUSY) {
506 503 ARMul_Icycles (state, 1, 0);
507 if (IntPending (state)) { 504
508 cpab = (state->LDC[CPNum]) (state, ARMul_INTERRUPT, 505 if (IntPending (state)) {
509 instr, 0); 506 cpab = (state->LDC[CPNum]) (state, ARMul_INTERRUPT,
510 return; 507 instr, 0);
511 } 508 return;
512 else 509 } else
513 cpab = (state->LDC[CPNum]) (state, ARMul_BUSY, instr, 510 cpab = (state->LDC[CPNum]) (state, ARMul_BUSY, instr,
514 0); 511 0);
515 } 512 }
516 if (cpab == ARMul_CANT) { 513 if (cpab == ARMul_CANT) {
517 /* 514 /*
518 printf 515 printf
519 ("SKYEYE ARMul_LDC,NOT CAN, underinstr, CPnum is %x, instr %x, addr %x\n", 516 ("SKYEYE ARMul_LDC,NOT CAN, underinstr, CPnum is %x, instr %x, addr %x\n",
520 CPNum, instr, address); 517 CPNum, instr, address);
521 */ 518 */
522 CPTAKEABORT; 519 CPTAKEABORT;
523 return; 520 return;
524 } 521 }
525 522
526 cpab = (state->LDC[CPNum]) (state, ARMul_TRANSFER, instr, 0); 523 cpab = (state->LDC[CPNum]) (state, ARMul_TRANSFER, instr, 0);
527 data = ARMul_LoadWordN (state, address); 524 data = ARMul_LoadWordN (state, address);
528 //chy 2004-05-25 525 //chy 2004-05-25
529 if (state->abortSig || state->Aborted) 526 if (state->abortSig || state->Aborted)
530 goto L_ldc_takeabort; 527 goto L_ldc_takeabort;
531 528
532 BUSUSEDINCPCN; 529 BUSUSEDINCPCN;
533//chy 2004-05-25 530//chy 2004-05-25
534/* 531 /*
535 if (BIT (21)) 532 if (BIT (21))
536 LSBase = state->Base; 533 LSBase = state->Base;
537*/ 534 */
538 535
539 cpab = (state->LDC[CPNum]) (state, ARMul_DATA, instr, data); 536 cpab = (state->LDC[CPNum]) (state, ARMul_DATA, instr, data);
540 537
541 while (cpab == ARMul_INC) { 538 while (cpab == ARMul_INC) {
542 address += 4; 539 address += 4;
543 data = ARMul_LoadWordN (state, address); 540 data = ARMul_LoadWordN (state, address);
544 //chy 2004-05-25 541 //chy 2004-05-25
545 if (state->abortSig || state->Aborted) 542 if (state->abortSig || state->Aborted)
546 goto L_ldc_takeabort; 543 goto L_ldc_takeabort;
547 544
548 cpab = (state->LDC[CPNum]) (state, ARMul_DATA, instr, data); 545 cpab = (state->LDC[CPNum]) (state, ARMul_DATA, instr, data);
549 } 546 }
550 547
551//chy 2004-05-25 548//chy 2004-05-25
552 L_ldc_takeabort: 549L_ldc_takeabort:
553 if (BIT (21)) { 550 if (BIT (21)) {
554 if (! 551 if (!
555 ((state->abortSig || state->Aborted) 552 ((state->abortSig || state->Aborted)
556 && state->lateabtSig == LOW)) 553 && state->lateabtSig == LOW))
557 LSBase = state->Base; 554 LSBase = state->Base;
558 } 555 }
559 556
560 if (state->abortSig || state->Aborted) 557 if (state->abortSig || state->Aborted)
561 TAKEABORT; 558 TAKEABORT;
562} 559}
563 560
564/* This function does the work of generating the addresses used in an 561/* This function does the work of generating the addresses used in an
@@ -569,88 +566,88 @@ ARMul_LDC (ARMul_State * state, ARMword instr, ARMword address)
569void 566void
570ARMul_STC (ARMul_State * state, ARMword instr, ARMword address) 567ARMul_STC (ARMul_State * state, ARMword instr, ARMword address)
571{ 568{
572 unsigned cpab; 569 unsigned cpab;
573 ARMword data; 570 ARMword data;
574 571
575 UNDEF_LSCPCBaseWb; 572 UNDEF_LSCPCBaseWb;
576 573
577 //printf("SKYEYE ARMul_STC, CPnum is %x, instr %x, addr %x\n",CPNum, instr, address); 574 //printf("SKYEYE ARMul_STC, CPnum is %x, instr %x, addr %x\n",CPNum, instr, address);
578 /*chy 2004-05-23 should update this function in the future,should concern dataabort */ 575 /*chy 2004-05-23 should update this function in the future,should concern dataabort */
579// skyeye_instr_debug=0;printf("SKYEYE debug end!!!!\n"); 576// skyeye_instr_debug=0;printf("SKYEYE debug end!!!!\n");
580// chy 2004-05-25 , fix it now,so needn't printf 577// chy 2004-05-25 , fix it now,so needn't printf
581// printf("SKYEYE ARMul_STC, should update this function!!!!!\n"); 578// printf("SKYEYE ARMul_STC, should update this function!!!!!\n");
582 579
583 //exit(-1); 580 //exit(-1);
584 if (!CP_ACCESS_ALLOWED (state, CPNum)) { 581 //if (!CP_ACCESS_ALLOWED (state, CPNum)) {
585 /* 582 if (!state->STC[CPNum]) {
586 printf 583 /*
587 ("SKYEYE ARMul_STC,NOT ALLOW, undefinstr, CPnum is %x, instr %x, addr %x\n", 584 printf
588 CPNum, instr, address); 585 ("SKYEYE ARMul_STC,NOT ALLOW, undefinstr, CPnum is %x, instr %x, addr %x\n",
589 */ 586 CPNum, instr, address);
590 ARMul_UndefInstr (state, instr); 587 */
591 return; 588 ARMul_UndefInstr (state, instr);
592 } 589 return;
593 590 }
594 //if (ADDREXCEPT (address) || VECTORACCESS (address)) 591
595 // INTERNALABORT (address); 592 /*if (ADDREXCEPT (address) || VECTORACCESS (address))
596 593 INTERNALABORT (address);*/
597 cpab = (state->STC[CPNum]) (state, ARMul_FIRST, instr, &data); 594
598 while (cpab == ARMul_BUSY) { 595 cpab = (state->STC[CPNum]) (state, ARMul_FIRST, instr, &data);
599 ARMul_Icycles (state, 1, 0); 596 while (cpab == ARMul_BUSY) {
600 if (IntPending (state)) { 597 ARMul_Icycles (state, 1, 0);
601 cpab = (state->STC[CPNum]) (state, ARMul_INTERRUPT, 598 if (IntPending (state)) {
602 instr, 0); 599 cpab = (state->STC[CPNum]) (state, ARMul_INTERRUPT,
603 return; 600 instr, 0);
604 } 601 return;
605 else 602 } else
606 cpab = (state->STC[CPNum]) (state, ARMul_BUSY, instr, 603 cpab = (state->STC[CPNum]) (state, ARMul_BUSY, instr,
607 &data); 604 &data);
608 } 605 }
609 606
610 if (cpab == ARMul_CANT) { 607 if (cpab == ARMul_CANT) {
611 /* 608 /*
612 printf 609 printf
613 ("SKYEYE ARMul_STC,CANT, undefinstr, CPnum is %x, instr %x, addr %x\n", 610 ("SKYEYE ARMul_STC,CANT, undefinstr, CPnum is %x, instr %x, addr %x\n",
614 CPNum, instr, address); 611 CPNum, instr, address);
615 */ 612 */
616 CPTAKEABORT; 613 CPTAKEABORT;
617 return; 614 return;
618 } 615 }
619#ifndef MODE32 616 /*#ifndef MODE32
620 if (ADDREXCEPT (address) || VECTORACCESS (address)) 617 if (ADDREXCEPT (address) || VECTORACCESS (address))
621 INTERNALABORT (address); 618 INTERNALABORT (address);
622#endif 619 #endif*/
623 BUSUSEDINCPCN; 620 BUSUSEDINCPCN;
624//chy 2004-05-25 621//chy 2004-05-25
625/* 622 /*
626 if (BIT (21)) 623 if (BIT (21))
627 LSBase = state->Base; 624 LSBase = state->Base;
628*/ 625 */
629 cpab = (state->STC[CPNum]) (state, ARMul_DATA, instr, &data); 626 cpab = (state->STC[CPNum]) (state, ARMul_DATA, instr, &data);
630 ARMul_StoreWordN (state, address, data); 627 ARMul_StoreWordN (state, address, data);
631 //chy 2004-05-25 628 //chy 2004-05-25
632 if (state->abortSig || state->Aborted) 629 if (state->abortSig || state->Aborted)
633 goto L_stc_takeabort; 630 goto L_stc_takeabort;
634 631
635 while (cpab == ARMul_INC) { 632 while (cpab == ARMul_INC) {
636 address += 4; 633 address += 4;
637 cpab = (state->STC[CPNum]) (state, ARMul_DATA, instr, &data); 634 cpab = (state->STC[CPNum]) (state, ARMul_DATA, instr, &data);
638 ARMul_StoreWordN (state, address, data); 635 ARMul_StoreWordN (state, address, data);
639 //chy 2004-05-25 636 //chy 2004-05-25
640 if (state->abortSig || state->Aborted) 637 if (state->abortSig || state->Aborted)
641 goto L_stc_takeabort; 638 goto L_stc_takeabort;
642 } 639 }
643//chy 2004-05-25 640//chy 2004-05-25
644 L_stc_takeabort: 641L_stc_takeabort:
645 if (BIT (21)) { 642 if (BIT (21)) {
646 if (! 643 if (!
647 ((state->abortSig || state->Aborted) 644 ((state->abortSig || state->Aborted)
648 && state->lateabtSig == LOW)) 645 && state->lateabtSig == LOW))
649 LSBase = state->Base; 646 LSBase = state->Base;
650 } 647 }
651 648
652 if (state->abortSig || state->Aborted) 649 if (state->abortSig || state->Aborted)
653 TAKEABORT; 650 TAKEABORT;
654} 651}
655 652
656/* This function does the Busy-Waiting for an MCR instruction. */ 653/* This function does the Busy-Waiting for an MCR instruction. */
@@ -658,39 +655,53 @@ ARMul_STC (ARMul_State * state, ARMword instr, ARMword address)
658void 655void
659ARMul_MCR (ARMul_State * state, ARMword instr, ARMword source) 656ARMul_MCR (ARMul_State * state, ARMword instr, ARMword source)
660{ 657{
661 unsigned cpab; 658 unsigned cpab;
662 659 int cm = BITS(0, 3) & 0xf;
663 //printf("SKYEYE ARMul_MCR, CPnum is %x, source %x\n",CPNum, source); 660 int cp = BITS(5, 7) & 0x7;
664 if (!CP_ACCESS_ALLOWED (state, CPNum)) { 661 int rd = BITS(12, 15) & 0xf;
665 //chy 2004-07-19 should fix in the future ????!!!! 662 int cn = BITS(16, 19) & 0xf;
666 //printf("SKYEYE ARMul_MCR, ACCESS_not ALLOWed, UndefinedInstr CPnum is %x, source %x\n",CPNum, source); 663 int cpopc = BITS(21, 23) & 0x7;
667 ARMul_UndefInstr (state, instr); 664
668 return; 665 if (CPNum == 15 && source == 0) //Cache flush
669 } 666 {
670 667 return;
671 cpab = (state->MCR[CPNum]) (state, ARMul_FIRST, instr, source); 668 }
672 669
673 while (cpab == ARMul_BUSY) { 670 //printf("SKYEYE ARMul_MCR, CPnum is %x, source %x\n",CPNum, source);
674 ARMul_Icycles (state, 1, 0); 671 //if (!CP_ACCESS_ALLOWED (state, CPNum)) {
675 672 if (!state->MCR[CPNum]) {
676 if (IntPending (state)) { 673 //chy 2004-07-19 should fix in the future ????!!!!
677 cpab = (state->MCR[CPNum]) (state, ARMul_INTERRUPT, 674 DEBUG("SKYEYE ARMul_MCR, ACCESS_not ALLOWed, UndefinedInstr CPnum is %x, source %x\n",CPNum, source);
678 instr, 0); 675 ARMul_UndefInstr (state, instr);
679 return; 676 return;
680 } 677 }
681 else 678
682 cpab = (state->MCR[CPNum]) (state, ARMul_BUSY, instr, 679 //DEBUG("SKYEYE ARMul_MCR p%d, %d, r%d, c%d, c%d, %d\n", CPNum, cpopc, rd, cn, cm, cp);
683 source); 680 //DEBUG("plutoo: MCR not implemented\n");
684 } 681 //exit(1);
685 682 //return;
686 if (cpab == ARMul_CANT) { 683
687 printf ("SKYEYE ARMul_MCR, CANT, UndefinedInstr %x CPnum is %x, source %x\n", instr, CPNum, source); 684 cpab = (state->MCR[CPNum]) (state, ARMul_FIRST, instr, source);
688 ARMul_Abort (state, ARMul_UndefinedInstrV); 685
689 } 686 while (cpab == ARMul_BUSY) {
690 else { 687 ARMul_Icycles (state, 1, 0);
691 BUSUSEDINCPCN; 688
692 ARMul_Ccycles (state, 1, 0); 689 if (IntPending (state)) {
693 } 690 cpab = (state->MCR[CPNum]) (state, ARMul_INTERRUPT,
691 instr, 0);
692 return;
693 } else
694 cpab = (state->MCR[CPNum]) (state, ARMul_BUSY, instr,
695 source);
696 }
697
698 if (cpab == ARMul_CANT) {
699 DEBUG("SKYEYE ARMul_MCR, CANT, UndefinedInstr %x CPnum is %x, source %x\n", instr, CPNum, source); //ichfly todo
700 //ARMul_Abort (state, ARMul_UndefinedInstrV);
701 } else {
702 BUSUSEDINCPCN;
703 ARMul_Ccycles (state, 1, 0);
704 }
694} 705}
695 706
696/* This function does the Busy-Waiting for an MCRR instruction. */ 707/* This function does the Busy-Waiting for an MCRR instruction. */
@@ -698,83 +709,93 @@ ARMul_MCR (ARMul_State * state, ARMword instr, ARMword source)
698void 709void
699ARMul_MCRR (ARMul_State * state, ARMword instr, ARMword source1, ARMword source2) 710ARMul_MCRR (ARMul_State * state, ARMword instr, ARMword source1, ARMword source2)
700{ 711{
701 unsigned cpab; 712 unsigned cpab;
702 713
703 if (!CP_ACCESS_ALLOWED (state, CPNum)) { 714 //if (!CP_ACCESS_ALLOWED (state, CPNum)) {
704 ARMul_UndefInstr (state, instr); 715 if (!state->MCRR[CPNum]) {
705 return; 716 ARMul_UndefInstr (state, instr);
706 } 717 return;
718 }
707 719
708 cpab = (state->MCRR[CPNum]) (state, ARMul_FIRST, instr, source1, source2); 720 cpab = (state->MCRR[CPNum]) (state, ARMul_FIRST, instr, source1, source2);
709 721
710 while (cpab == ARMul_BUSY) { 722 while (cpab == ARMul_BUSY) {
711 ARMul_Icycles (state, 1, 0); 723 ARMul_Icycles (state, 1, 0);
712 724
713 if (IntPending (state)) { 725 if (IntPending (state)) {
714 cpab = (state->MCRR[CPNum]) (state, ARMul_INTERRUPT, 726 cpab = (state->MCRR[CPNum]) (state, ARMul_INTERRUPT,
715 instr, 0, 0); 727 instr, 0, 0);
716 return; 728 return;
717 } 729 } else
718 else 730 cpab = (state->MCRR[CPNum]) (state, ARMul_BUSY, instr,
719 cpab = (state->MCRR[CPNum]) (state, ARMul_BUSY, instr, 731 source1, source2);
720 source1, source2); 732 }
721 } 733 if (cpab == ARMul_CANT) {
722 if (cpab == ARMul_CANT) { 734 printf ("In %s, CoProcesscor returned CANT, CPnum is %x, instr %x, source %x %x\n", __FUNCTION__, CPNum, instr, source1, source2);
723 printf ("In %s, CoProcesscor returned CANT, CPnum is %x, instr %x, source %x %x\n", __FUNCTION__, CPNum, instr, source1, source2); 735 ARMul_Abort (state, ARMul_UndefinedInstrV);
724 ARMul_Abort (state, ARMul_UndefinedInstrV); 736 } else {
725 } 737 BUSUSEDINCPCN;
726 else { 738 ARMul_Ccycles (state, 1, 0);
727 BUSUSEDINCPCN; 739 }
728 ARMul_Ccycles (state, 1, 0);
729 }
730} 740}
731 741
732/* This function does the Busy-Waiting for an MRC instruction. */ 742/* This function does the Busy-Waiting for an MRC instruction. */
733 743
734ARMword 744ARMword ARMul_MRC (ARMul_State * state, ARMword instr)
735ARMul_MRC (ARMul_State * state, ARMword instr)
736{ 745{
737 unsigned cpab; 746 int cm = BITS(0, 3) & 0xf;
747 int cp = BITS(5, 7) & 0x7;
748 int rd = BITS(12, 15) & 0xf;
749 int cn = BITS(16, 19) & 0xf;
750 int cpopc = BITS(21, 23) & 0x7;
738 751
752 if (cn == 13 && cm == 0 && cp == 3) { //c13,c0,3; returns CPU svc buffer
739 ARMword result = HLE::CallMRC(instr); 753 ARMword result = HLE::CallMRC(instr);
740 754
741 if (result != -1) { 755 if (result != -1) {
742 return result; 756 return result;
743 } 757 }
744 758 }
745 //printf("SKYEYE ARMul_MRC, CPnum is %x, instr %x\n",CPNum, instr); 759
746 if (!CP_ACCESS_ALLOWED (state, CPNum)) { 760 //DEBUG("SKYEYE ARMul_MRC p%d, %d, r%d, c%d, c%d, %d\n", CPNum, cpopc, rd, cn, cm, cp);
747 //chy 2004-07-19 should fix in the future????!!!! 761 //DEBUG("plutoo: MRC not implemented\n");
748 //printf("SKYEYE ARMul_MRC,NOT ALLOWed UndefInstr CPnum is %x, instr %x\n",CPNum, instr); 762 //return;
749 ARMul_UndefInstr (state, instr); 763
750 return -1; 764 unsigned cpab;
751 } 765 ARMword result = 0;
752 766
753 cpab = (state->MRC[CPNum]) (state, ARMul_FIRST, instr, &result); 767 //printf("SKYEYE ARMul_MRC, CPnum is %x, instr %x\n",CPNum, instr);
754 while (cpab == ARMul_BUSY) { 768 //if (!CP_ACCESS_ALLOWED (state, CPNum)) {
755 ARMul_Icycles (state, 1, 0); 769 if (!state->MRC[CPNum]) {
756 if (IntPending (state)) { 770 //chy 2004-07-19 should fix in the future????!!!!
757 cpab = (state->MRC[CPNum]) (state, ARMul_INTERRUPT, 771 DEBUG("SKYEYE ARMul_MRC,NOT ALLOWed UndefInstr CPnum is %x, instr %x\n", CPNum, instr);
758 instr, 0); 772 ARMul_UndefInstr (state, instr);
759 return (0); 773 return -1;
760 } 774 }
761 else 775
762 cpab = (state->MRC[CPNum]) (state, ARMul_BUSY, instr, 776 cpab = (state->MRC[CPNum]) (state, ARMul_FIRST, instr, &result);
763 &result); 777 while (cpab == ARMul_BUSY) {
764 } 778 ARMul_Icycles (state, 1, 0);
765 if (cpab == ARMul_CANT) { 779 if (IntPending (state)) {
766 printf ("SKYEYE ARMul_MRC,CANT UndefInstr CPnum is %x, instr %x\n", CPNum, instr); 780 cpab = (state->MRC[CPNum]) (state, ARMul_INTERRUPT,
767 ARMul_Abort (state, ARMul_UndefinedInstrV); 781 instr, 0);
768 /* Parent will destroy the flags otherwise. */ 782 return (0);
769 result = ECC; 783 } else
770 } 784 cpab = (state->MRC[CPNum]) (state, ARMul_BUSY, instr,
771 else { 785 &result);
772 BUSUSEDINCPCN; 786 }
773 ARMul_Ccycles (state, 1, 0); 787 if (cpab == ARMul_CANT) {
774 ARMul_Icycles (state, 1, 0); 788 printf ("SKYEYE ARMul_MRC,CANT UndefInstr CPnum is %x, instr %x\n", CPNum, instr);
775 } 789 ARMul_Abort (state, ARMul_UndefinedInstrV);
776 790 /* Parent will destroy the flags otherwise. */
777 return result; 791 result = ECC;
792 } else {
793 BUSUSEDINCPCN;
794 ARMul_Ccycles (state, 1, 0);
795 ARMul_Icycles (state, 1, 0);
796 }
797
798 return result;
778} 799}
779 800
780/* This function does the Busy-Waiting for an MRRC instruction. (to verify) */ 801/* This function does the Busy-Waiting for an MRRC instruction. (to verify) */
@@ -782,39 +803,38 @@ ARMul_MRC (ARMul_State * state, ARMword instr)
782void 803void
783ARMul_MRRC (ARMul_State * state, ARMword instr, ARMword * dest1, ARMword * dest2) 804ARMul_MRRC (ARMul_State * state, ARMword instr, ARMword * dest1, ARMword * dest2)
784{ 805{
785 unsigned cpab; 806 unsigned cpab;
786 ARMword result1 = 0; 807 ARMword result1 = 0;
787 ARMword result2 = 0; 808 ARMword result2 = 0;
788 809
789 if (!CP_ACCESS_ALLOWED (state, CPNum)) { 810 //if (!CP_ACCESS_ALLOWED (state, CPNum)) {
790 ARMul_UndefInstr (state, instr); 811 if (!state->MRRC[CPNum]) {
791 return; 812 ARMul_UndefInstr (state, instr);
792 } 813 return;
793 814 }
794 cpab = (state->MRRC[CPNum]) (state, ARMul_FIRST, instr, &result1, &result2); 815
795 while (cpab == ARMul_BUSY) { 816 cpab = (state->MRRC[CPNum]) (state, ARMul_FIRST, instr, &result1, &result2);
796 ARMul_Icycles (state, 1, 0); 817 while (cpab == ARMul_BUSY) {
797 if (IntPending (state)) { 818 ARMul_Icycles (state, 1, 0);
798 cpab = (state->MRRC[CPNum]) (state, ARMul_INTERRUPT, 819 if (IntPending (state)) {
799 instr, 0, 0); 820 cpab = (state->MRRC[CPNum]) (state, ARMul_INTERRUPT,
800 return; 821 instr, 0, 0);
801 } 822 return;
802 else 823 } else
803 cpab = (state->MRRC[CPNum]) (state, ARMul_BUSY, instr, 824 cpab = (state->MRRC[CPNum]) (state, ARMul_BUSY, instr,
804 &result1, &result2); 825 &result1, &result2);
805 } 826 }
806 if (cpab == ARMul_CANT) { 827 if (cpab == ARMul_CANT) {
807 printf ("In %s, CoProcesscor returned CANT, CPnum is %x, instr %x\n", __FUNCTION__, CPNum, instr); 828 printf ("In %s, CoProcesscor returned CANT, CPnum is %x, instr %x\n", __FUNCTION__, CPNum, instr);
808 ARMul_Abort (state, ARMul_UndefinedInstrV); 829 ARMul_Abort (state, ARMul_UndefinedInstrV);
809 } 830 } else {
810 else { 831 BUSUSEDINCPCN;
811 BUSUSEDINCPCN; 832 ARMul_Ccycles (state, 1, 0);
812 ARMul_Ccycles (state, 1, 0); 833 ARMul_Icycles (state, 1, 0);
813 ARMul_Icycles (state, 1, 0); 834 }
814 } 835
815 836 *dest1 = result1;
816 *dest1 = result1; 837 *dest2 = result2;
817 *dest2 = result2;
818} 838}
819 839
820/* This function does the Busy-Waiting for an CDP instruction. */ 840/* This function does the Busy-Waiting for an CDP instruction. */
@@ -822,27 +842,27 @@ ARMul_MRRC (ARMul_State * state, ARMword instr, ARMword * dest1, ARMword * dest2
822void 842void
823ARMul_CDP (ARMul_State * state, ARMword instr) 843ARMul_CDP (ARMul_State * state, ARMword instr)
824{ 844{
825 unsigned cpab; 845 unsigned cpab;
826 846
827 if (!CP_ACCESS_ALLOWED (state, CPNum)) { 847 //if (!CP_ACCESS_ALLOWED (state, CPNum)) {
828 ARMul_UndefInstr (state, instr); 848 if (!state->CDP[CPNum]) {
829 return; 849 ARMul_UndefInstr (state, instr);
830 } 850 return;
831 cpab = (state->CDP[CPNum]) (state, ARMul_FIRST, instr); 851 }
832 while (cpab == ARMul_BUSY) { 852 cpab = (state->CDP[CPNum]) (state, ARMul_FIRST, instr);
833 ARMul_Icycles (state, 1, 0); 853 while (cpab == ARMul_BUSY) {
834 if (IntPending (state)) { 854 ARMul_Icycles (state, 1, 0);
835 cpab = (state->CDP[CPNum]) (state, ARMul_INTERRUPT, 855 if (IntPending (state)) {
836 instr); 856 cpab = (state->CDP[CPNum]) (state, ARMul_INTERRUPT,
837 return; 857 instr);
838 } 858 return;
839 else 859 } else
840 cpab = (state->CDP[CPNum]) (state, ARMul_BUSY, instr); 860 cpab = (state->CDP[CPNum]) (state, ARMul_BUSY, instr);
841 } 861 }
842 if (cpab == ARMul_CANT) 862 if (cpab == ARMul_CANT)
843 ARMul_Abort (state, ARMul_UndefinedInstrV); 863 ARMul_Abort (state, ARMul_UndefinedInstrV);
844 else 864 else
845 BUSUSEDN; 865 BUSUSEDN;
846} 866}
847 867
848/* This function handles Undefined instructions, as CP isntruction. */ 868/* This function handles Undefined instructions, as CP isntruction. */
@@ -850,11 +870,13 @@ ARMul_CDP (ARMul_State * state, ARMword instr)
850void 870void
851ARMul_UndefInstr (ARMul_State * state, ARMword instr) 871ARMul_UndefInstr (ARMul_State * state, ARMword instr)
852{ 872{
853 char buff[512]; 873 /*SKYEYE_LOG_IN_CLR(RED, "In %s, line = %d, undef instr: 0x%x\n",
854 ARM_Disasm disasm = ARM_Disasm(); 874 __func__, __LINE__, instr);*/
855 disasm.disasm(state->pc, instr, buff); 875 char buff[512];
856 ERROR_LOG(ARM11, "Undefined instruction!! Disasm: %s Opcode: 0x%x", buff, instr); 876 ARM_Disasm disasm = ARM_Disasm();
857 ARMul_Abort (state, ARMul_UndefinedInstrV); 877 disasm.disasm(state->pc, instr, buff);
878 ERROR_LOG(ARM11, "Undefined instruction!! Disasm: %s Opcode: 0x%x", buff, instr);
879 ARMul_Abort (state, ARMul_UndefinedInstrV);
858} 880}
859 881
860/* Return TRUE if an interrupt is pending, FALSE otherwise. */ 882/* Return TRUE if an interrupt is pending, FALSE otherwise. */
@@ -862,33 +884,31 @@ ARMul_UndefInstr (ARMul_State * state, ARMword instr)
862unsigned 884unsigned
863IntPending (ARMul_State * state) 885IntPending (ARMul_State * state)
864{ 886{
865 /* Any exceptions. */ 887 /* Any exceptions. */
866 if (state->NresetSig == LOW) { 888 if (state->NresetSig == LOW) {
867 ARMul_Abort (state, ARMul_ResetV); 889 ARMul_Abort (state, ARMul_ResetV);
868 return TRUE; 890 return TRUE;
869 } 891 } else if (!state->NfiqSig && !FFLAG) {
870 else if (!state->NfiqSig && !FFLAG) { 892 ARMul_Abort (state, ARMul_FIQV);
871 ARMul_Abort (state, ARMul_FIQV); 893 return TRUE;
872 return TRUE; 894 } else if (!state->NirqSig && !IFLAG) {
873 } 895 ARMul_Abort (state, ARMul_IRQV);
874 else if (!state->NirqSig && !IFLAG) { 896 return TRUE;
875 ARMul_Abort (state, ARMul_IRQV); 897 }
876 return TRUE;
877 }
878 898
879 return FALSE; 899 return FALSE;
880} 900}
881 901
882/* Align a word access to a non word boundary. */ 902/* Align a word access to a non word boundary. */
883 903
884ARMword 904ARMword
885ARMul_Align (ARMul_State *state, ARMword address, ARMword data) 905ARMul_Align (ARMul_State* state, ARMword address, ARMword data)
886{ 906{
887 /* This code assumes the address is really unaligned, 907 /* This code assumes the address is really unaligned,
888 as a shift by 32 is undefined in C. */ 908 as a shift by 32 is undefined in C. */
889 909
890 address = (address & 3) << 3; /* Get the word address. */ 910 address = (address & 3) << 3; /* Get the word address. */
891 return ((data >> address) | (data << (32 - address))); /* rot right */ 911 return ((data >> address) | (data << (32 - address))); /* rot right */
892} 912}
893 913
894/* This routine is used to call another routine after a certain number of 914/* This routine is used to call another routine after a certain number of
@@ -898,19 +918,23 @@ ARMul_Align (ARMul_State *state, ARMword address, ARMword data)
898 918
899void 919void
900ARMul_ScheduleEvent (ARMul_State * state, unsigned int delay, 920ARMul_ScheduleEvent (ARMul_State * state, unsigned int delay,
901 unsigned (*what) (ARMul_State *)) 921 unsigned (*what) (ARMul_State *))
902{ 922{
903 unsigned int when; 923 unsigned int when;
904 struct EventNode *event; 924 struct EventNode *event;
905 925
906 if (state->EventSet++ == 0) 926 if (state->EventSet++ == 0)
907 state->Now = ARMul_Time (state); 927 state->Now = ARMul_Time (state);
908 when = (state->Now + delay) % EVENTLISTSIZE; 928 when = (state->Now + delay) % EVENTLISTSIZE;
909 event = (struct EventNode *) malloc (sizeof (struct EventNode)); 929 event = (struct EventNode *) malloc (sizeof (struct EventNode));
910 _dbg_assert_msg_(ARM11, event, "SKYEYE:ARMul_ScheduleEvent: malloc event error\n"); 930 if (!event) {
911 event->func = what; 931 printf ("SKYEYE:ARMul_ScheduleEvent: malloc event error\n");
912 event->next = *(state->EventPtr + when); 932 exit(-1);
913 *(state->EventPtr + when) = event; 933 //skyeye_exit (-1);
934 }
935 event->func = what;
936 event->next = *(state->EventPtr + when);
937 *(state->EventPtr + when) = event;
914} 938}
915 939
916/* This routine is called at the beginning of 940/* This routine is called at the beginning of
@@ -919,18 +943,18 @@ ARMul_ScheduleEvent (ARMul_State * state, unsigned int delay,
919void 943void
920ARMul_EnvokeEvent (ARMul_State * state) 944ARMul_EnvokeEvent (ARMul_State * state)
921{ 945{
922 static unsigned int then; 946 static unsigned int then;
923 947
924 then = state->Now; 948 then = state->Now;
925 state->Now = ARMul_Time (state) % EVENTLISTSIZE; 949 state->Now = ARMul_Time (state) % EVENTLISTSIZE;
926 if (then < state->Now) 950 if (then < state->Now)
927 /* Schedule events. */ 951 /* Schedule events. */
928 EnvokeList (state, then, state->Now); 952 EnvokeList (state, then, state->Now);
929 else if (then > state->Now) { 953 else if (then > state->Now) {
930 /* Need to wrap around the list. */ 954 /* Need to wrap around the list. */
931 EnvokeList (state, then, EVENTLISTSIZE - 1L); 955 EnvokeList (state, then, EVENTLISTSIZE - 1L);
932 EnvokeList (state, 0L, state->Now); 956 EnvokeList (state, 0L, state->Now);
933 } 957 }
934} 958}
935 959
936/* Envokes all the entries in a range. */ 960/* Envokes all the entries in a range. */
@@ -938,17 +962,17 @@ ARMul_EnvokeEvent (ARMul_State * state)
938static void 962static void
939EnvokeList (ARMul_State * state, unsigned int from, unsigned int to) 963EnvokeList (ARMul_State * state, unsigned int from, unsigned int to)
940{ 964{
941 for (; from <= to; from++) { 965 for (; from <= to; from++) {
942 struct EventNode *anevent; 966 struct EventNode *anevent;
943 967
944 anevent = *(state->EventPtr + from); 968 anevent = *(state->EventPtr + from);
945 while (anevent) { 969 while (anevent) {
946 (anevent->func) (state); 970 (anevent->func) (state);
947 state->EventSet--; 971 state->EventSet--;
948 anevent = anevent->next; 972 anevent = anevent->next;
949 } 973 }
950 *(state->EventPtr + from) = NULL; 974 *(state->EventPtr + from) = NULL;
951 } 975 }
952} 976}
953 977
954/* This routine is returns the number of clock ticks since the last reset. */ 978/* This routine is returns the number of clock ticks since the last reset. */
@@ -956,6 +980,6 @@ EnvokeList (ARMul_State * state, unsigned int from, unsigned int to)
956unsigned int 980unsigned int
957ARMul_Time (ARMul_State * state) 981ARMul_Time (ARMul_State * state)
958{ 982{
959 return (state->NumScycles + state->NumNcycles + 983 return (state->NumScycles + state->NumNcycles +
960 state->NumIcycles + state->NumCcycles + state->NumFcycles); 984 state->NumIcycles + state->NumCcycles + state->NumFcycles);
961} 985}
HIC SVNT DRACONES