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-rw-r--r--src/core/arm/interpreter/armemu.cpp925
-rw-r--r--src/core/arm/interpreter/arminit.cpp288
-rw-r--r--src/core/arm/interpreter/armsupp.cpp80
-rw-r--r--src/core/arm/skyeye_common/armdefs.h455
-rw-r--r--src/core/arm/skyeye_common/armemu.h5
-rw-r--r--src/core/arm/skyeye_common/skyeye_defs.h82
6 files changed, 168 insertions, 1667 deletions
diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp
index adc5c3a05..7114313d6 100644
--- a/src/core/arm/interpreter/armemu.cpp
+++ b/src/core/arm/interpreter/armemu.cpp
@@ -16,31 +16,11 @@
16 along with this program; if not, write to the Free Software 16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
18 18
19//#include <util.h> // DEBUG()
20
21#include "core/arm/skyeye_common/arm_regformat.h" 19#include "core/arm/skyeye_common/arm_regformat.h"
22#include "core/arm/skyeye_common/armdefs.h" 20#include "core/arm/skyeye_common/armdefs.h"
23#include "core/arm/skyeye_common/armemu.h" 21#include "core/arm/skyeye_common/armemu.h"
24#include "core/hle/hle.h" 22#include "core/hle/hle.h"
25 23
26//#include "svc.h"
27
28//ichfly
29//#define callstacker 1
30
31//#include "skyeye_callback.h"
32//#include "skyeye_bus.h"
33//#include "sim_control.h"
34//#include "skyeye_pref.h"
35//#include "skyeye.h"
36//#include "skyeye2gdb.h"
37//#include "code_cov.h"
38
39//#include "iwmmxt.h"
40//chy 2003-07-11: for debug instrs
41//extern int skyeye_instr_debug;
42extern FILE *skyeye_logfd;
43
44static ARMword GetDPRegRHS (ARMul_State *, ARMword); 24static ARMword GetDPRegRHS (ARMul_State *, ARMword);
45static ARMword GetDPSRegRHS (ARMul_State *, ARMword); 25static ARMword GetDPSRegRHS (ARMul_State *, ARMword);
46static void WriteR15 (ARMul_State *, ARMword); 26static void WriteR15 (ARMul_State *, ARMword);
@@ -63,25 +43,13 @@ static unsigned MultiplyAdd64 (ARMul_State *, ARMword, int, int);
63static void Handle_Load_Double (ARMul_State *, ARMword); 43static void Handle_Load_Double (ARMul_State *, ARMword);
64static void Handle_Store_Double (ARMul_State *, ARMword); 44static void Handle_Store_Double (ARMul_State *, ARMword);
65 45
66static int 46static int handle_v6_insn (ARMul_State * state, ARMword instr);
67handle_v6_insn (ARMul_State * state, ARMword instr);
68 47
69#define LUNSIGNED (0) /* unsigned operation */ 48#define LUNSIGNED (0) /* unsigned operation */
70#define LSIGNED (1) /* signed operation */ 49#define LSIGNED (1) /* signed operation */
71#define LDEFAULT (0) /* default : do nothing */ 50#define LDEFAULT (0) /* default : do nothing */
72#define LSCC (1) /* set condition codes on result */ 51#define LSCC (1) /* set condition codes on result */
73 52
74#ifdef NEED_UI_LOOP_HOOK
75/* How often to run the ui_loop update, when in use. */
76#define UI_LOOP_POLL_INTERVAL 0x32000
77
78/* Counter for the ui_loop_hook update. */
79static int ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL;
80
81/* Actual hook to call to run through gdb's gui event loop. */
82extern int (*ui_loop_hook) (int);
83#endif /* NEED_UI_LOOP_HOOK */
84
85/* Short-hand macros for LDR/STR. */ 53/* Short-hand macros for LDR/STR. */
86 54
87/* Store post decrement writeback. */ 55/* Store post decrement writeback. */
@@ -290,20 +258,8 @@ extern int (*ui_loop_hook) (int);
290 break; \ 258 break; \
291} 259}
292 260
293/*ywc 2005-03-31*/
294//teawater add for arm2x86 2005.02.17-------------------------------------------
295#ifdef DBCT
296#include "dbct/tb.h"
297#include "dbct/arm2x86_self.h"
298#endif
299//AJ2D--------------------------------------------------------------------------
300
301//Diff register
302unsigned int mirror_register_file[39];
303
304/* EMULATION of ARM6. */ 261/* EMULATION of ARM6. */
305 262
306extern int debugmode;
307int ARMul_ICE_debug(ARMul_State *state,ARMword instr,ARMword addr); 263int ARMul_ICE_debug(ARMul_State *state,ARMword instr,ARMword addr);
308#ifdef MODE32 264#ifdef MODE32
309//chy 2006-04-12, for ICE debug 265//chy 2006-04-12, for ICE debug
@@ -312,59 +268,14 @@ int ARMul_ICE_debug(ARMul_State *state,ARMword instr,ARMword addr)
312 return 0; 268 return 0;
313} 269}
314 270
315static int dump = 0;
316ARMword ARMul_Debug(ARMul_State * state, ARMword pc, ARMword instr) 271ARMword ARMul_Debug(ARMul_State * state, ARMword pc, ARMword instr)
317{ 272{
318 /*printf("[%08x] ", pc);
319 arm11_Disasm32(pc);*/
320
321 /*if (pc >= 0x0010303C && pc <= 0x00103050)
322 {
323 printf("[%08x] = %08X = ", pc, instr);
324 arm11_Disasm32(pc);
325 arm11_Dump();
326 }*/
327
328 //fprintf(stderr,"[%08x]\n", pc);
329
330 //if (pc == 0x00240C88)
331 // arm11_Dump();
332
333 /*if (pc == 0x188e04)
334 {
335 DEBUG("read %08X %08X %016X %08X %08X from %08X", state->Reg[0], state->Reg[1], state->Reg[2] | state->Reg[3] << 32, mem_Read32(state->Reg[13]), mem_Read32(state->Reg[13] + 4), state->Reg[14]);
336 }
337 if (pc == 0x21222c)
338 {
339 arm11_Dump();
340 mem_Dbugdump();
341 }*/
342
343 /*if (pc == 0x0022D168)
344 {
345 int j = 0;
346 }*/
347
348 /*if (state->Reg[4] == 0x00105734)
349 {
350 printf("[%08x] ", pc);
351 arm11_Disasm32(pc);
352 }*/
353
354 return 0; 273 return 0;
355} 274}
356 275
357/* 276ARMword ARMul_Emulate32(ARMul_State* state)
358void chy_debug()
359{
360 printf("SkyEye chy_deubeg begin\n");
361}
362*/
363ARMword
364ARMul_Emulate32 (ARMul_State * state)
365#else 277#else
366ARMword 278ARMword ARMul_Emulate26(ARMul_State* state)
367ARMul_Emulate26 (ARMul_State * state)
368#endif 279#endif
369{ 280{
370 /* The PC pipeline value depends on whether ARM 281 /* The PC pipeline value depends on whether ARM
@@ -383,39 +294,6 @@ ARMul_Emulate26 (ARMul_State * state)
383 ARMword loaded_addr=0; 294 ARMword loaded_addr=0;
384 ARMword have_bp=0; 295 ARMword have_bp=0;
385 296
386#ifdef callstacker
387 char a[256];
388#endif
389 /* shenoubang */
390 static int instr_sum = 0;
391 int reg_index = 0;
392#if DIFF_STATE
393//initialize all mirror register for follow mode
394 for (reg_index = 0; reg_index < 16; reg_index ++) {
395 mirror_register_file[reg_index] = state->Reg[reg_index];
396 }
397 mirror_register_file[CPSR_REG] = state->Cpsr;
398 mirror_register_file[R13_SVC] = state->RegBank[SVCBANK][13];
399 mirror_register_file[R14_SVC] = state->RegBank[SVCBANK][14];
400 mirror_register_file[R13_ABORT] = state->RegBank[ABORTBANK][13];
401 mirror_register_file[R14_ABORT] = state->RegBank[ABORTBANK][14];
402 mirror_register_file[R13_UNDEF] = state->RegBank[UNDEFBANK][13];
403 mirror_register_file[R14_UNDEF] = state->RegBank[UNDEFBANK][14];
404 mirror_register_file[R13_IRQ] = state->RegBank[IRQBANK][13];
405 mirror_register_file[R14_IRQ] = state->RegBank[IRQBANK][14];
406 mirror_register_file[R8_FIRQ] = state->RegBank[FIQBANK][8];
407 mirror_register_file[R9_FIRQ] = state->RegBank[FIQBANK][9];
408 mirror_register_file[R10_FIRQ] = state->RegBank[FIQBANK][10];
409 mirror_register_file[R11_FIRQ] = state->RegBank[FIQBANK][11];
410 mirror_register_file[R12_FIRQ] = state->RegBank[FIQBANK][12];
411 mirror_register_file[R13_FIRQ] = state->RegBank[FIQBANK][13];
412 mirror_register_file[R14_FIRQ] = state->RegBank[FIQBANK][14];
413 mirror_register_file[SPSR_SVC] = state->Spsr[SVCBANK];
414 mirror_register_file[SPSR_ABORT] = state->Spsr[ABORTBANK];
415 mirror_register_file[SPSR_UNDEF] = state->Spsr[UNDEFBANK];
416 mirror_register_file[SPSR_IRQ] = state->Spsr[IRQBANK];
417 mirror_register_file[SPSR_FIRQ] = state->Spsr[FIQBANK];
418#endif
419 /* Execute the next instruction. */ 297 /* Execute the next instruction. */
420 if (state->NextInstr < PRIMEPIPE) { 298 if (state->NextInstr < PRIMEPIPE) {
421 decoded = state->decoded; 299 decoded = state->decoded;
@@ -533,392 +411,38 @@ ARMul_Emulate26 (ARMul_State * state)
533 411
534 //chy 2006-04-12, for ICE debug 412 //chy 2006-04-12, for ICE debug
535 have_bp=ARMul_ICE_debug(state,instr,pc); 413 have_bp=ARMul_ICE_debug(state,instr,pc);
536#if 0 414
537 decoded =
538 ARMul_LoadInstrS (state, pc + (isize), isize);
539#endif
540 decoded_addr=pc+isize; 415 decoded_addr=pc+isize;
541#if 0 416
542 loaded = ARMul_LoadInstrS (state, pc + (isize * 2),
543 isize);
544#endif
545 loaded_addr=pc + isize * 2; 417 loaded_addr=pc + isize * 2;
546 NORMALCYCLE; 418 NORMALCYCLE;
547 if (have_bp) goto TEST_EMULATE; 419 if (have_bp) goto TEST_EMULATE;
548 break; 420 break;
549 } 421 }
550#if 0
551 int idx = 0;
552 printf("pc:%x\n", pc);
553 for (; idx < 17; idx ++) {
554 printf("R%d:%x\t", idx, state->Reg[idx]);
555 }
556 printf("\n");
557#endif
558 422
559 instr = ARMul_LoadInstrN (state, pc, isize); 423 instr = ARMul_LoadInstrN (state, pc, isize);
560 state->last_instr = state->CurrInstr; 424 state->last_instr = state->CurrInstr;
561 state->CurrInstr = instr; 425 state->CurrInstr = instr;
562 ARMul_Debug(state, pc, instr); 426 ARMul_Debug(state, pc, instr);
563#if 0
564 if((state->NumInstrs % 10000000) == 0)
565 printf("---|%p|--- %lld\n", pc, state->NumInstrs);
566 if(state->NumInstrs > (3000000000)) {
567 static int flag = 0;
568 if(pc == 0x8032ccc4) {
569 flag = 300;
570 }
571 if(flag) {
572 int idx = 0;
573 printf("------------------------------------\n");
574 printf("pc:%x\n", pc);
575 for (; idx < 17; idx ++) {
576 printf("R%d:%x\t", idx, state->Reg[idx]);
577 }
578 printf("\nN:%d\t Z:%d\t C:%d\t V:%d\n", state->NFlag, state->ZFlag, state->CFlag, state->VFlag);
579 printf("\n");
580 printf("------------------------------------\n");
581 flag--;
582 }
583 }
584#endif
585#if DIFF_STATE
586 fprintf(state->state_log, "PC:0x%x\n", pc);
587 if (pc && (pc + 8) != state->Reg[15]) {
588 printf("lucky dog\n");
589 printf("pc is %x, R15 is %x\n", pc, state->Reg[15]);
590 //exit(-1);
591 }
592 for (reg_index = 0; reg_index < 16; reg_index ++) {
593 if (state->Reg[reg_index] != mirror_register_file[reg_index]) {
594 fprintf(state->state_log, "R%d:0x%x\n", reg_index, state->Reg[reg_index]);
595 mirror_register_file[reg_index] = state->Reg[reg_index];
596 }
597 }
598 if (state->Cpsr != mirror_register_file[CPSR_REG]) {
599 fprintf(state->state_log, "Cpsr:0x%x\n", state->Cpsr);
600 mirror_register_file[CPSR_REG] = state->Cpsr;
601 }
602 if (state->RegBank[SVCBANK][13] != mirror_register_file[R13_SVC]) {
603 fprintf(state->state_log, "R13_SVC:0x%x\n", state->RegBank[SVCBANK][13]);
604 mirror_register_file[R13_SVC] = state->RegBank[SVCBANK][13];
605 }
606 if (state->RegBank[SVCBANK][14] != mirror_register_file[R14_SVC]) {
607 fprintf(state->state_log, "R14_SVC:0x%x\n", state->RegBank[SVCBANK][14]);
608 mirror_register_file[R14_SVC] = state->RegBank[SVCBANK][14];
609 }
610 if (state->RegBank[ABORTBANK][13] != mirror_register_file[R13_ABORT]) {
611 fprintf(state->state_log, "R13_ABORT:0x%x\n", state->RegBank[ABORTBANK][13]);
612 mirror_register_file[R13_ABORT] = state->RegBank[ABORTBANK][13];
613 }
614 if (state->RegBank[ABORTBANK][14] != mirror_register_file[R14_ABORT]) {
615 fprintf(state->state_log, "R14_ABORT:0x%x\n", state->RegBank[ABORTBANK][14]);
616 mirror_register_file[R14_ABORT] = state->RegBank[ABORTBANK][14];
617 }
618 if (state->RegBank[UNDEFBANK][13] != mirror_register_file[R13_UNDEF]) {
619 fprintf(state->state_log, "R13_UNDEF:0x%x\n", state->RegBank[UNDEFBANK][13]);
620 mirror_register_file[R13_UNDEF] = state->RegBank[UNDEFBANK][13];
621 }
622 if (state->RegBank[UNDEFBANK][14] != mirror_register_file[R14_UNDEF]) {
623 fprintf(state->state_log, "R14_UNDEF:0x%x\n", state->RegBank[UNDEFBANK][14]);
624 mirror_register_file[R14_UNDEF] = state->RegBank[UNDEFBANK][14];
625 }
626 if (state->RegBank[IRQBANK][13] != mirror_register_file[R13_IRQ]) {
627 fprintf(state->state_log, "R13_IRQ:0x%x\n", state->RegBank[IRQBANK][13]);
628 mirror_register_file[R13_IRQ] = state->RegBank[IRQBANK][13];
629 }
630 if (state->RegBank[IRQBANK][14] != mirror_register_file[R14_IRQ]) {
631 fprintf(state->state_log, "R14_IRQ:0x%x\n", state->RegBank[IRQBANK][14]);
632 mirror_register_file[R14_IRQ] = state->RegBank[IRQBANK][14];
633 }
634 if (state->RegBank[FIQBANK][8] != mirror_register_file[R8_FIRQ]) {
635 fprintf(state->state_log, "R8_FIRQ:0x%x\n", state->RegBank[FIQBANK][8]);
636 mirror_register_file[R8_FIRQ] = state->RegBank[FIQBANK][8];
637 }
638 if (state->RegBank[FIQBANK][9] != mirror_register_file[R9_FIRQ]) {
639 fprintf(state->state_log, "R9_FIRQ:0x%x\n", state->RegBank[FIQBANK][9]);
640 mirror_register_file[R9_FIRQ] = state->RegBank[FIQBANK][9];
641 }
642 if (state->RegBank[FIQBANK][10] != mirror_register_file[R10_FIRQ]) {
643 fprintf(state->state_log, "R10_FIRQ:0x%x\n", state->RegBank[FIQBANK][10]);
644 mirror_register_file[R10_FIRQ] = state->RegBank[FIQBANK][10];
645 }
646 if (state->RegBank[FIQBANK][11] != mirror_register_file[R11_FIRQ]) {
647 fprintf(state->state_log, "R11_FIRQ:0x%x\n", state->RegBank[FIQBANK][11]);
648 mirror_register_file[R11_FIRQ] = state->RegBank[FIQBANK][11];
649 }
650 if (state->RegBank[FIQBANK][12] != mirror_register_file[R12_FIRQ]) {
651 fprintf(state->state_log, "R12_FIRQ:0x%x\n", state->RegBank[FIQBANK][12]);
652 mirror_register_file[R12_FIRQ] = state->RegBank[FIQBANK][12];
653 }
654 if (state->RegBank[FIQBANK][13] != mirror_register_file[R13_FIRQ]) {
655 fprintf(state->state_log, "R13_FIRQ:0x%x\n", state->RegBank[FIQBANK][13]);
656 mirror_register_file[R13_FIRQ] = state->RegBank[FIQBANK][13];
657 }
658 if (state->RegBank[FIQBANK][14] != mirror_register_file[R14_FIRQ]) {
659 fprintf(state->state_log, "R14_FIRQ:0x%x\n", state->RegBank[FIQBANK][14]);
660 mirror_register_file[R14_FIRQ] = state->RegBank[FIQBANK][14];
661 }
662 if (state->Spsr[SVCBANK] != mirror_register_file[SPSR_SVC]) {
663 fprintf(state->state_log, "SPSR_SVC:0x%x\n", state->Spsr[SVCBANK]);
664 mirror_register_file[SPSR_SVC] = state->RegBank[SVCBANK];
665 }
666 if (state->Spsr[ABORTBANK] != mirror_register_file[SPSR_ABORT]) {
667 fprintf(state->state_log, "SPSR_ABORT:0x%x\n", state->Spsr[ABORTBANK]);
668 mirror_register_file[SPSR_ABORT] = state->RegBank[ABORTBANK];
669 }
670 if (state->Spsr[UNDEFBANK] != mirror_register_file[SPSR_UNDEF]) {
671 fprintf(state->state_log, "SPSR_UNDEF:0x%x\n", state->Spsr[UNDEFBANK]);
672 mirror_register_file[SPSR_UNDEF] = state->RegBank[UNDEFBANK];
673 }
674 if (state->Spsr[IRQBANK] != mirror_register_file[SPSR_IRQ]) {
675 fprintf(state->state_log, "SPSR_IRQ:0x%x\n", state->Spsr[IRQBANK]);
676 mirror_register_file[SPSR_IRQ] = state->RegBank[IRQBANK];
677 }
678 if (state->Spsr[FIQBANK] != mirror_register_file[SPSR_FIRQ]) {
679 fprintf(state->state_log, "SPSR_FIRQ:0x%x\n", state->Spsr[FIQBANK]);
680 mirror_register_file[SPSR_FIRQ] = state->RegBank[FIQBANK];
681 }
682#endif
683
684#if 0
685 uint32_t alex = 0;
686 static int flagged = 0;
687 if ((flagged == 0) && (pc == 0xb224)) {
688 flagged++;
689 }
690 if ((flagged == 1) && (pc == 0x1a800)) {
691 flagged++;
692 }
693 if (flagged == 3) {
694 printf("---|%p|--- %x\n", pc, state->NumInstrs);
695 for (alex = 0; alex < 15; alex++) {
696 printf("R%02d % 8x\n", alex, state->Reg[alex]);
697 }
698 printf("R%02d % 8x\n", alex, state->Reg[alex] - 8);
699 printf("CPS %x%07x\n", (state->NFlag<<3 | state->ZFlag<<2 | state->CFlag<<1 | state->VFlag), state->Cpsr & 0xfffffff);
700 } else {
701 if (state->NumInstrs < 0x400000) {
702 //exit(-1);
703 }
704 }
705#endif
706
707 /*if (state->EventSet)
708 ARMul_EnvokeEvent (state);*/
709
710#if 0
711 /* do profiling for code coverage */
712 if (skyeye_config.code_cov.prof_on)
713 cov_prof(EXEC_FLAG, pc);
714#endif
715//2003-07-11 chy: for test
716#if 0
717 if (skyeye_config.log.logon >= 1) {
718 if (state->NumInstrs >= skyeye_config.log.start &&
719 state->NumInstrs <= skyeye_config.log.end) {
720 static int mybegin = 0;
721 static int myinstrnum = 0;
722 if (mybegin == 0)
723 mybegin = 1;
724#if 0
725 if (state->NumInstrs == 3695) {
726 printf ("***********SKYEYE: numinstr = 3695\n");
727 }
728 static int mybeg2 = 0;
729 static int mybeg3 = 0;
730 static int mybeg4 = 0;
731 static int mybeg5 = 0;
732
733 if (pc == 0xa0008000) {
734 //mybegin=1;
735 printf ("************SKYEYE: real vmlinux begin now numinstr is %llu ****************\n", state->NumInstrs);
736 }
737 427
738 //chy 2003-09-02 test fiq
739 if (state->NumInstrs == 67347000) {
740 printf ("***********SKYEYE: numinstr = 67347000, begin log\n");
741 mybegin = 1;
742 }
743 if (pc == 0xc00087b4) { //numinstr=67348714
744 mybegin = 1;
745 printf ("************SKYEYE: test irq now numinstr is %llu ****************\n", state->NumInstrs);
746 }
747 if (pc == 0xc00087b8) { //in start_kernel::sti()
748 mybeg4 = 1;
749 printf ("************SKYEYE: startkerenl: sti now numinstr is %llu ********\n", state->NumInstrs);
750 }
751 /*if (pc==0xc001e4f4||pc==0xc001e4f8||pc==0xc001e4fc||pc==0xc001e500||pc==0xffff0004) { //MRA instr */
752 if (pc == 0xc001e500) { //MRA instr
753 mybeg5 = 1;
754 printf ("************SKYEYE: MRA instr now numinstr is %llu ********\n", state->NumInstrs);
755 }
756 if (pc >= 0xc0000000 && mybeg2 == 0) {
757 mybeg2 = 1;
758 printf ("************SKYEYE: enable mmu&cache, now numinstr is %llu **************\n", state->NumInstrs);
759 SKYEYE_OUTREGS (stderr);
760 printf ("************************************************************************\n");
761 }
762 //chy 2003-09-01 test after tlb-flush
763 if (pc == 0xc00261ac) {
764 //sleep(2);
765 mybeg3 = 1;
766 printf ("************SKYEYE: after tlb-flush numinstr is %llu ****************\n", state->NumInstrs);
767 }
768 if (mybeg3 == 1) {
769 SKYEYE_OUTREGS (skyeye_logfd);
770 SKYEYE_OUTMOREREGS (skyeye_logfd);
771 fprintf (skyeye_logfd, "\n");
772 }
773#endif
774 if (mybegin == 1) {
775 //fprintf(skyeye_logfd,"p %x,i %x,d %x,l %x,",pc,instr,decoded,loaded);
776 //chy for test 20050729
777 /*if (state->NumInstrs>=3302294) {
778 if (pc==0x100c9d4 && instr==0xe1b0f00e){
779 chy_debug();
780 printf("*********************************************\n");
781 printf("******SKYEYE N %llx :p %x,i %x\n SKYEYE******\n",state->NumInstrs,pc,instr);
782 printf("*********************************************\n");
783 }
784 */
785 if (skyeye_config.log.logon >= 1)
786 /*
787 fprintf (skyeye_logfd,
788 "N %llx :p %x,i %x,",
789 state->NumInstrs, pc,
790 #ifdef MODET
791 TFLAG ? instr & 0xffff : instr
792 #else
793 instr
794 #endif
795 );
796 */
797 fprintf(skyeye_logfd, "pc=0x%x,r3=0x%x\n", pc, state->Reg[3]);
798 if (skyeye_config.log.logon >= 2)
799 SKYEYE_OUTREGS (skyeye_logfd);
800 if (skyeye_config.log.logon >= 3)
801 SKYEYE_OUTMOREREGS
802 (skyeye_logfd);
803 //fprintf (skyeye_logfd, "\n");
804 if (skyeye_config.log.length > 0) {
805 myinstrnum++;
806 if (myinstrnum >=
807 skyeye_config.log.
808 length) {
809 myinstrnum = 0;
810 fflush (skyeye_logfd);
811 fseek (skyeye_logfd,
812 0L, SEEK_SET);
813 }
814 }
815 }
816 //SKYEYE_OUTREGS(skyeye_logfd);
817 //SKYEYE_OUTMOREREGS(skyeye_logfd);
818 }
819 }
820#endif
821#if 0 /* Enable this for a helpful bit of debugging when tracing is needed. */
822 fprintf (stderr, "pc: %x, instr: %x\n", pc & ~1, instr);
823 if (instr == 0)
824 abort ();
825#endif
826#if 0 /* Enable this code to help track down stack alignment bugs. */
827 {
828 static ARMword old_sp = -1;
829
830 if (old_sp != state->Reg[13]) {
831 old_sp = state->Reg[13];
832 fprintf (stderr,
833 "pc: %08x: SP set to %08x%s\n",
834 pc & ~1, old_sp,
835 (old_sp % 8) ? " [UNALIGNED!]" : "");
836 }
837 }
838#endif
839 /* Any exceptions ? */ 428 /* Any exceptions ? */
840 if (state->NresetSig == LOW) { 429 if (state->NresetSig == LOW) {
841 ARMul_Abort (state, ARMul_ResetV); 430 ARMul_Abort (state, ARMul_ResetV);
842
843 /*added energy_prof statement by ksh in 2004-11-26 */
844 //chy 2005-07-28 for standalone
845 //ARMul_do_energy(state,instr,pc);
846 break; 431 break;
847 } else if (!state->NfiqSig && !FFLAG) { 432 } else if (!state->NfiqSig && !FFLAG) {
848 ARMul_Abort (state, ARMul_FIQV); 433 ARMul_Abort (state, ARMul_FIQV);
849 /*added energy_prof statement by ksh in 2004-11-26 */
850 //chy 2005-07-28 for standalone
851 //ARMul_do_energy(state,instr,pc);
852 break; 434 break;
853 } else if (!state->NirqSig && !IFLAG) { 435 } else if (!state->NirqSig && !IFLAG) {
854 ARMul_Abort (state, ARMul_IRQV); 436 ARMul_Abort (state, ARMul_IRQV);
855 /*added energy_prof statement by ksh in 2004-11-26 */
856 //chy 2005-07-28 for standalone
857 //ARMul_do_energy(state,instr,pc);
858 break; 437 break;
859 } 438 }
860 439
861//teawater add for arm2x86 2005.04.26-------------------------------------------
862#if 0
863// if (state->pc == 0xc011a868 || state->pc == 0xc011a86c) {
864 if (state->NumInstrs == 1671574 || state->NumInstrs == 1671573 || state->NumInstrs == 1671572
865 || state->NumInstrs == 1671575) {
866 for (reg_index = 0; reg_index < 16; reg_index ++) {
867 printf("R%d:%x\t", reg_index, state->Reg[reg_index]);
868 }
869 printf("\n");
870 }
871#endif
872 if (state->tea_pc) {
873 int i;
874
875 if (state->tea_reg_fd) {
876 fprintf (state->tea_reg_fd, "\n");
877 for (i = 0; i < 15; i++) {
878 fprintf (state->tea_reg_fd, "%x,",
879 state->Reg[i]);
880 }
881 fprintf (state->tea_reg_fd, "%x,", pc);
882 state->Cpsr = ARMul_GetCPSR (state);
883 fprintf (state->tea_reg_fd, "%x\n",
884 state->Cpsr);
885 } else {
886 printf ("\n");
887 for (i = 0; i < 15; i++) {
888 printf ("%x,", state->Reg[i]);
889 }
890 printf ("%x,", pc);
891 state->Cpsr = ARMul_GetCPSR (state);
892 printf ("%x\n", state->Cpsr);
893 }
894 }
895//AJ2D--------------------------------------------------------------------------
896
897 /*if (state->CallDebug > 0) {
898 instr = ARMul_Debug (state, pc, instr);
899 if (state->Emulate < ONCE) {
900 state->NextInstr = RESUME;
901 break;
902 }
903 if (state->Debug) {
904 fprintf (stderr,
905 "sim: At %08lx Instr %08lx Mode %02lx\n",
906 pc, instr, state->Mode);
907 (void) fgetc (stdin);
908 }
909 }
910 else*/
911 if (state->Emulate < ONCE) { 440 if (state->Emulate < ONCE) {
912 state->NextInstr = RESUME; 441 state->NextInstr = RESUME;
913 break; 442 break;
914 } 443 }
915 //io_do_cycle (state); 444
916 state->NumInstrs++; 445 state->NumInstrs++;
917#if 0
918 if (state->NumInstrs % 10000000 == 0) {
919 printf("10 MIPS instr have been executed\n");
920 }
921#endif
922 446
923#ifdef MODET 447#ifdef MODET
924 /* Provide Thumb instruction decoding. If the processor is in Thumb 448 /* Provide Thumb instruction decoding. If the processor is in Thumb
@@ -990,12 +514,6 @@ ARMul_Emulate26 (ARMul_State * state)
990 /* clrex do nothing here temporary */ 514 /* clrex do nothing here temporary */
991 if (instr == 0xf57ff01f) { 515 if (instr == 0xf57ff01f) {
992 //printf("clrex \n"); 516 //printf("clrex \n");
993#if 0
994 int i;
995 for(i = 0; i < 128; i++) {
996 state->exclusive_tag_array[i] = 0xffffffff;
997 }
998#endif
999 /* shenoubang 2012-3-14 refer the dyncom_interpreter */ 517 /* shenoubang 2012-3-14 refer the dyncom_interpreter */
1000 state->exclusive_tag_array[0] = 0xFFFFFFFF; 518 state->exclusive_tag_array[0] = 0xFFFFFFFF;
1001 state->exclusive_access_state = 0; 519 state->exclusive_access_state = 0;
@@ -1169,9 +687,9 @@ mainswitch:
1169 Rn = BITS(0, 3); 687 Rn = BITS(0, 3);
1170 lsb = BITS(7, 11); 688 lsb = BITS(7, 11);
1171 msb = BITS(16, 20); //-V519 689 msb = BITS(16, 20); //-V519
1172 if ((Rd == 15)) { 690 if (Rd == 15) {
1173 ARMul_UndefInstr (state, instr); 691 ARMul_UndefInstr (state, instr);
1174 } else if ((Rn == 15)) { 692 } else if (Rn == 15) {
1175 data = state->Reg[Rd]; 693 data = state->Reg[Rd];
1176 tmp_rd = ((ARMword)(data << (31 - lsb)) >> (31 - lsb)); 694 tmp_rd = ((ARMword)(data << (31 - lsb)) >> (31 - lsb));
1177 dst = ((data >> msb) << (msb - lsb)); 695 dst = ((data >> msb) << (msb - lsb));
@@ -3209,16 +2727,6 @@ mainswitch:
3209 break; 2727 break;
3210 2728
3211 case 0x6e: /* Store Byte, WriteBack, Post Inc, Reg. */ 2729 case 0x6e: /* Store Byte, WriteBack, Post Inc, Reg. */
3212#if 0
3213 if (state->is_v6) {
3214 int Rm = 0;
3215 /* utxb */
3216 if (BITS(15, 19) == 0xf && BITS(4, 7) == 0x7) {
3217 Rm = (RHS >> (8 * BITS(10, 11))) & 0xff;
3218 DEST = Rm;
3219 }
3220 }
3221#endif
3222 if (BIT (4)) { 2730 if (BIT (4)) {
3223#ifdef MODE32 2731#ifdef MODE32
3224 if (state->is_v6 2732 if (state->is_v6
@@ -3656,13 +3164,6 @@ mainswitch:
3656#endif 3164#endif
3657 state->Reg[15] = pc + 8 + POSBRANCH; 3165 state->Reg[15] = pc + 8 + POSBRANCH;
3658 FLUSHPIPE; 3166 FLUSHPIPE;
3659
3660#ifdef callstacker
3661 memset(a, 0, 256);
3662 aufloeser(a, state->Reg[15]);
3663 printf("call %08X %08X %s(%08X %08X %08X %08X %08X %08X %08X)\n", state->Reg[14], state->Reg[15], a, state->Reg[0], state->Reg[1], state->Reg[2], state->Reg[3], mem_Read32(state->Reg[13]), mem_Read32(state->Reg[13] - 4),mem_Read32(state->Reg[13] - 8));
3664#endif
3665
3666 break; 3167 break;
3667 3168
3668 /* Branch and Link backward. */ 3169 /* Branch and Link backward. */
@@ -3682,13 +3183,6 @@ mainswitch:
3682#endif 3183#endif
3683 state->Reg[15] = pc + 8 + NEGBRANCH; 3184 state->Reg[15] = pc + 8 + NEGBRANCH;
3684 FLUSHPIPE; 3185 FLUSHPIPE;
3685
3686#ifdef callstacker
3687 memset(a, 0, 256);
3688 aufloeser(a, state->Reg[15]);
3689 printf("call %08X %08X %s(%08X %08X %08X %08X %08X %08X %08X)\n", state->Reg[14], state->Reg[15], a, state->Reg[0], state->Reg[1], state->Reg[2], state->Reg[3], mem_Read32(state->Reg[13]), mem_Read32(state->Reg[13] - 4),mem_Read32(state->Reg[13] - 8));
3690#endif
3691
3692 break; 3186 break;
3693 3187
3694 /* Co-Processor Data Transfers. */ 3188 /* Co-Processor Data Transfers. */
@@ -3909,165 +3403,6 @@ mainswitch:
3909donext: 3403donext:
3910#endif 3404#endif
3911 state->pc = pc; 3405 state->pc = pc;
3912#if 0
3913 /* shenoubang */
3914 instr_sum++;
3915 int i, j;
3916 i = j = 0;
3917 if (instr_sum >= 7388648) {
3918 //if (pc == 0xc0008ab4) {
3919 // printf("instr_sum: %d\n", instr_sum);
3920 // start_kernel : 0xc000895c
3921 printf("--------------------------------------------------\n");
3922 for (i = 0; i < 16; i++) {
3923 printf("[R%02d]:[0x%08x]\t", i, state->Reg[i]);
3924 if ((i % 3) == 2) {
3925 printf("\n");
3926 }
3927 }
3928 printf("[cpr]:[0x%08x]\t[spr0]:[0x%08x]\n", state->Cpsr, state->Spsr[0]);
3929 for (j = 1; j < 7; j++) {
3930 printf("[spr%d]:[0x%08x]\t", j, state->Spsr[j]);
3931 if ((j % 4) == 3) {
3932 printf("\n");
3933 }
3934 }
3935 printf("\n[PC]:[0x%08x]\t[INST]:[0x%08x]\t[COUNT]:[%d]\n", pc, instr, instr_sum);
3936 printf("--------------------------------------------------\n");
3937 }
3938#endif
3939
3940#if 0
3941 fprintf(state->state_log, "PC:0x%x\n", pc);
3942 for (reg_index = 0; reg_index < 16; reg_index ++) {
3943 if (state->Reg[reg_index] != mirror_register_file[reg_index]) {
3944 fprintf(state->state_log, "R%d:0x%x\n", reg_index, state->Reg[reg_index]);
3945 mirror_register_file[reg_index] = state->Reg[reg_index];
3946 }
3947 }
3948 if (state->Cpsr != mirror_register_file[CPSR_REG]) {
3949 fprintf(state->state_log, "Cpsr:0x%x\n", state->Cpsr);
3950 mirror_register_file[CPSR_REG] = state->Cpsr;
3951 }
3952 if (state->RegBank[SVCBANK][13] != mirror_register_file[R13_SVC]) {
3953 fprintf(state->state_log, "R13_SVC:0x%x\n", state->RegBank[SVCBANK][13]);
3954 mirror_register_file[R13_SVC] = state->RegBank[SVCBANK][13];
3955 }
3956 if (state->RegBank[SVCBANK][14] != mirror_register_file[R14_SVC]) {
3957 fprintf(state->state_log, "R14_SVC:0x%x\n", state->RegBank[SVCBANK][14]);
3958 mirror_register_file[R14_SVC] = state->RegBank[SVCBANK][14];
3959 }
3960 if (state->RegBank[ABORTBANK][13] != mirror_register_file[R13_ABORT]) {
3961 fprintf(state->state_log, "R13_ABORT:0x%x\n", state->RegBank[ABORTBANK][13]);
3962 mirror_register_file[R13_ABORT] = state->RegBank[ABORTBANK][13];
3963 }
3964 if (state->RegBank[ABORTBANK][14] != mirror_register_file[R14_ABORT]) {
3965 fprintf(state->state_log, "R14_ABORT:0x%x\n", state->RegBank[ABORTBANK][14]);
3966 mirror_register_file[R14_ABORT] = state->RegBank[ABORTBANK][14];
3967 }
3968 if (state->RegBank[UNDEFBANK][13] != mirror_register_file[R13_UNDEF]) {
3969 fprintf(state->state_log, "R13_UNDEF:0x%x\n", state->RegBank[UNDEFBANK][13]);
3970 mirror_register_file[R13_UNDEF] = state->RegBank[UNDEFBANK][13];
3971 }
3972 if (state->RegBank[UNDEFBANK][14] != mirror_register_file[R14_UNDEF]) {
3973 fprintf(state->state_log, "R14_UNDEF:0x%x\n", state->RegBank[UNDEFBANK][14]);
3974 mirror_register_file[R14_UNDEF] = state->RegBank[UNDEFBANK][14];
3975 }
3976 if (state->RegBank[IRQBANK][13] != mirror_register_file[R13_IRQ]) {
3977 fprintf(state->state_log, "R13_IRQ:0x%x\n", state->RegBank[IRQBANK][13]);
3978 mirror_register_file[R13_IRQ] = state->RegBank[IRQBANK][13];
3979 }
3980 if (state->RegBank[IRQBANK][14] != mirror_register_file[R14_IRQ]) {
3981 fprintf(state->state_log, "R14_IRQ:0x%x\n", state->RegBank[IRQBANK][14]);
3982 mirror_register_file[R14_IRQ] = state->RegBank[IRQBANK][14];
3983 }
3984 if (state->RegBank[FIQBANK][8] != mirror_register_file[R8_FIRQ]) {
3985 fprintf(state->state_log, "R8_FIRQ:0x%x\n", state->RegBank[FIQBANK][8]);
3986 mirror_register_file[R8_FIRQ] = state->RegBank[FIQBANK][8];
3987 }
3988 if (state->RegBank[FIQBANK][9] != mirror_register_file[R9_FIRQ]) {
3989 fprintf(state->state_log, "R9_FIRQ:0x%x\n", state->RegBank[FIQBANK][9]);
3990 mirror_register_file[R9_FIRQ] = state->RegBank[FIQBANK][9];
3991 }
3992 if (state->RegBank[FIQBANK][10] != mirror_register_file[R10_FIRQ]) {
3993 fprintf(state->state_log, "R10_FIRQ:0x%x\n", state->RegBank[FIQBANK][10]);
3994 mirror_register_file[R10_FIRQ] = state->RegBank[FIQBANK][10];
3995 }
3996 if (state->RegBank[FIQBANK][11] != mirror_register_file[R11_FIRQ]) {
3997 fprintf(state->state_log, "R11_FIRQ:0x%x\n", state->RegBank[FIQBANK][11]);
3998 mirror_register_file[R11_FIRQ] = state->RegBank[FIQBANK][11];
3999 }
4000 if (state->RegBank[FIQBANK][12] != mirror_register_file[R12_FIRQ]) {
4001 fprintf(state->state_log, "R12_FIRQ:0x%x\n", state->RegBank[FIQBANK][12]);
4002 mirror_register_file[R12_FIRQ] = state->RegBank[FIQBANK][12];
4003 }
4004 if (state->RegBank[FIQBANK][13] != mirror_register_file[R13_FIRQ]) {
4005 fprintf(state->state_log, "R13_FIRQ:0x%x\n", state->RegBank[FIQBANK][13]);
4006 mirror_register_file[R13_FIRQ] = state->RegBank[FIQBANK][13];
4007 }
4008 if (state->RegBank[FIQBANK][14] != mirror_register_file[R14_FIRQ]) {
4009 fprintf(state->state_log, "R14_FIRQ:0x%x\n", state->RegBank[FIQBANK][14]);
4010 mirror_register_file[R14_FIRQ] = state->RegBank[FIQBANK][14];
4011 }
4012 if (state->Spsr[SVCBANK] != mirror_register_file[SPSR_SVC]) {
4013 fprintf(state->state_log, "SPSR_SVC:0x%x\n", state->Spsr[SVCBANK]);
4014 mirror_register_file[SPSR_SVC] = state->RegBank[SVCBANK];
4015 }
4016 if (state->Spsr[ABORTBANK] != mirror_register_file[SPSR_ABORT]) {
4017 fprintf(state->state_log, "SPSR_ABORT:0x%x\n", state->Spsr[ABORTBANK]);
4018 mirror_register_file[SPSR_ABORT] = state->RegBank[ABORTBANK];
4019 }
4020 if (state->Spsr[UNDEFBANK] != mirror_register_file[SPSR_UNDEF]) {
4021 fprintf(state->state_log, "SPSR_UNDEF:0x%x\n", state->Spsr[UNDEFBANK]);
4022 mirror_register_file[SPSR_UNDEF] = state->RegBank[UNDEFBANK];
4023 }
4024 if (state->Spsr[IRQBANK] != mirror_register_file[SPSR_IRQ]) {
4025 fprintf(state->state_log, "SPSR_IRQ:0x%x\n", state->Spsr[IRQBANK]);
4026 mirror_register_file[SPSR_IRQ] = state->RegBank[IRQBANK];
4027 }
4028 if (state->Spsr[FIQBANK] != mirror_register_file[SPSR_FIRQ]) {
4029 fprintf(state->state_log, "SPSR_FIRQ:0x%x\n", state->Spsr[FIQBANK]);
4030 mirror_register_file[SPSR_FIRQ] = state->RegBank[FIQBANK];
4031 }
4032
4033#endif
4034
4035#ifdef NEED_UI_LOOP_HOOK
4036 if (ui_loop_hook != NULL && ui_loop_hook_counter-- < 0) {
4037 ui_loop_hook_counter = UI_LOOP_POLL_INTERVAL;
4038 ui_loop_hook (0);
4039 }
4040#endif /* NEED_UI_LOOP_HOOK */
4041
4042 /*added energy_prof statement by ksh in 2004-11-26 */
4043 //chy 2005-07-28 for standalone
4044 //ARMul_do_energy(state,instr,pc);
4045//teawater add for record reg value to ./reg.txt 2005.07.10---------------------
4046 if (state->tea_break_ok && pc == state->tea_break_addr) {
4047 //ARMul_Debug (state, 0, 0);
4048 state->tea_break_ok = 0;
4049 } else {
4050 state->tea_break_ok = 1;
4051 }
4052//AJ2D--------------------------------------------------------------------------
4053//chy 2006-04-14 for ctrl-c debug
4054#if 0
4055 if (debugmode) {
4056 if (instr != ARMul_ABORTWORD) {
4057 remote_interrupt_test_time++;
4058 //chy 2006-04-14 2000 should be changed in skyeye_conf ???!!!
4059 if (remote_interrupt_test_time >= 2000) {
4060 remote_interrupt_test_time=0;
4061 if (remote_interrupt()) {
4062 //for test
4063 //printf("SKYEYE: ICE_debug recv Ctrl_C\n");
4064 state->EndCondition = 0;
4065 state->Emulate = STOP;
4066 }
4067 }
4068 }
4069 }
4070#endif
4071 3406
4072 /* jump out every time */ 3407 /* jump out every time */
4073 //state->EndCondition = 0; 3408 //state->EndCondition = 0;
@@ -4076,10 +3411,6 @@ donext:
4076TEST_EMULATE: 3411TEST_EMULATE:
4077 if (state->Emulate == ONCE) 3412 if (state->Emulate == ONCE)
4078 state->Emulate = STOP; 3413 state->Emulate = STOP;
4079 //chy: 2003-08-23: should not use CHANGEMODE !!!!
4080 /* If we have changed mode, allow the PC to advance before stopping. */
4081 // else if (state->Emulate == CHANGEMODE)
4082 // continue;
4083 else if (state->Emulate != RUN) 3414 else if (state->Emulate != RUN)
4084 break; 3415 break;
4085 } 3416 }
@@ -4096,225 +3427,14 @@ exit:
4096 return pc; 3427 return pc;
4097 } 3428 }
4098 3429
4099//teawater add for arm2x86 2005.02.17-------------------------------------------
4100 /*ywc 2005-04-01*/
4101//#include "tb.h"
4102//#include "arm2x86_self.h"
4103
4104 static volatile void (*gen_func) (void); 3430 static volatile void (*gen_func) (void);
4105//static volatile ARMul_State *tmp_st; 3431
4106//static volatile ARMul_State *save_st;
4107 static volatile uint32_t tmp_st; 3432 static volatile uint32_t tmp_st;
4108 static volatile uint32_t save_st; 3433 static volatile uint32_t save_st;
4109 static volatile uint32_t save_T0; 3434 static volatile uint32_t save_T0;
4110 static volatile uint32_t save_T1; 3435 static volatile uint32_t save_T1;
4111 static volatile uint32_t save_T2; 3436 static volatile uint32_t save_T2;
4112 3437
4113#ifdef MODE32
4114#ifdef DBCT
4115//teawater change for debug function 2005.07.09---------------------------------
4116 ARMword
4117 ARMul_Emulate32_dbct (ARMul_State * state) {
4118 static int init = 0;
4119 static FILE *fd;
4120
4121 /*if (!init) {
4122 fd = fopen("./pc.txt", "w");
4123 if (!fd) {
4124 exit(-1);
4125 }
4126 init = 1;
4127 } */
4128
4129 state->Reg[15] += INSN_SIZE;
4130 do {
4131 /*if (skyeye_config.log.logon>=1) {
4132 if (state->NumInstrs>=skyeye_config.log.start && state->NumInstrs<=skyeye_config.log.end) {
4133 static int mybegin=0;
4134 static int myinstrnum=0;
4135
4136 if (mybegin==0) mybegin=1;
4137 if (mybegin==1) {
4138 state->Reg[15] -= INSN_SIZE;
4139 if (skyeye_config.log.logon>=1) fprintf(skyeye_logfd,"N %llx :p %x,i %x,",state->NumInstrs, (state->Reg[15] - INSN_SIZE), instr);
4140 if (skyeye_config.log.logon>=2) SKYEYE_OUTREGS(skyeye_logfd);
4141 if (skyeye_config.log.logon>=3) SKYEYE_OUTMOREREGS(skyeye_logfd);
4142 fprintf(skyeye_logfd,"\n");
4143 if (skyeye_config.log.length>0) {
4144 myinstrnum++;
4145 if (myinstrnum>=skyeye_config.log.length) {
4146 myinstrnum=0;
4147 fflush(skyeye_logfd);
4148 fseek(skyeye_logfd,0L,SEEK_SET);
4149 }
4150 }
4151 state->Reg[15] += INSN_SIZE;
4152 }
4153 }
4154 } */
4155 state->trap = 0;
4156 gen_func =
4157 (void *) tb_find (state, state->Reg[15] - INSN_SIZE);
4158 if (!gen_func) {
4159 //fprintf(stderr, "SKYEYE: tb_find: Error in find the translate block.\n");
4160 //exit(-1);
4161 //TRAP_INSN_ABORT
4162 //TEA_OUT(printf("\n------------\npc:%x\n", state->Reg[15] - INSN_SIZE));
4163 //TEA_OUT(printf("TRAP_INSN_ABORT\n"));
4164//teawater add for xscale(arm v5) 2005.09.01------------------------------------
4165 /*XScale_set_fsr_far(state, ARMul_CP15_R5_MMU_EXCPT, state->Reg[15] - INSN_SIZE);
4166 state->Reg[15] += INSN_SIZE;
4167 ARMul_Abort(state, ARMul_PrefetchAbortV);
4168 state->Reg[15] += INSN_SIZE;
4169 goto next; */
4170 state->trap = TRAP_INSN_ABORT;
4171 goto check;
4172//AJ2D--------------------------------------------------------------------------
4173 }
4174
4175 save_st = (uint32_t) st;
4176 save_T0 = T0;
4177 save_T1 = T1;
4178 save_T2 = T2;
4179 tmp_st = (uint32_t) state;
4180 wmb ();
4181 st = (ARMul_State *) tmp_st;
4182 gen_func ();
4183 st = (ARMul_State *) save_st;
4184 T0 = save_T0;
4185 T1 = save_T1;
4186 T2 = save_T2;
4187
4188 /*if (state->trap != TRAP_OUT) {
4189 state->tea_break_ok = 1;
4190 }
4191 if (state->trap <= TRAP_SET_R15) {
4192 goto next;
4193 } */
4194 //TEA_OUT(printf("\n------------\npc:%x\n", state->Reg[15] - INSN_SIZE));
4195//teawater add check thumb 2005.07.21-------------------------------------------
4196 /*if (TFLAG) {
4197 state->Reg[15] -= 2;
4198 return(state->Reg[15]);
4199 } */
4200//AJ2D--------------------------------------------------------------------------
4201
4202//teawater add for xscale(arm v5) 2005.09.01------------------------------------
4203check:
4204//AJ2D--------------------------------------------------------------------------
4205 switch (state->trap) {
4206 case TRAP_RESET: {
4207 //TEA_OUT(printf("TRAP_RESET\n"));
4208 ARMul_Abort (state, ARMul_ResetV);
4209 state->Reg[15] += INSN_SIZE;
4210 }
4211 break;
4212 case TRAP_UNPREDICTABLE: {
4213 //ARMul_Debug (state, 0, 0);
4214 }
4215 break;
4216 case TRAP_INSN_UNDEF: {
4217 //TEA_OUT(printf("TRAP_INSN_UNDEF\n"));
4218 state->Reg[15] += INSN_SIZE;
4219 ARMul_UndefInstr (state, 0);
4220 state->Reg[15] += INSN_SIZE;
4221 }
4222 break;
4223 case TRAP_SWI: {
4224 //TEA_OUT(printf("TRAP_SWI\n"));
4225 state->Reg[15] += INSN_SIZE;
4226 ARMul_Abort (state, ARMul_SWIV);
4227 state->Reg[15] += INSN_SIZE;
4228 }
4229 break;
4230//teawater add for xscale(arm v5) 2005.09.01------------------------------------
4231 case TRAP_INSN_ABORT: {
4232 /*XScale_set_fsr_far (state,
4233 ARMul_CP15_R5_MMU_EXCPT,
4234 state->Reg[15] -
4235 INSN_SIZE);*/
4236 state->Reg[15] += INSN_SIZE;
4237 ARMul_Abort (state, ARMul_PrefetchAbortV);
4238 state->Reg[15] += INSN_SIZE;
4239 }
4240 break;
4241//AJ2D--------------------------------------------------------------------------
4242 case TRAP_DATA_ABORT: {
4243 //TEA_OUT(printf("TRAP_DATA_ABORT\n"));
4244 state->Reg[15] += INSN_SIZE;
4245 ARMul_Abort (state, ARMul_DataAbortV);
4246 state->Reg[15] += INSN_SIZE;
4247 }
4248 break;
4249 case TRAP_IRQ: {
4250 //TEA_OUT(printf("TRAP_IRQ\n"));
4251 state->Reg[15] += INSN_SIZE;
4252 ARMul_Abort (state, ARMul_IRQV);
4253 state->Reg[15] += INSN_SIZE;
4254 }
4255 break;
4256 case TRAP_FIQ: {
4257 //TEA_OUT(printf("TRAP_FIQ\n"));
4258 state->Reg[15] += INSN_SIZE;
4259 ARMul_Abort (state, ARMul_FIQV);
4260 state->Reg[15] += INSN_SIZE;
4261 }
4262 break;
4263 case TRAP_SETS_R15: {
4264 //TEA_OUT(printf("TRAP_SETS_R15\n"));
4265 /*if (state->Bank > 0) {
4266 state->Cpsr = state->Spsr[state->Bank];
4267 ARMul_CPSRAltered (state);
4268 } */
4269 WriteSR15 (state, state->Reg[15]);
4270 }
4271 break;
4272 case TRAP_SET_CPSR: {
4273 //TEA_OUT(printf("TRAP_SET_CPSR\n"));
4274 //chy 2006-02-15 USERBANK=SYSTEMBANK=0
4275 //chy 2006-02-16 should use Mode to test
4276 //if (state->Bank > 0) {
4277 if (state->Mode != USER26MODE && state->Mode != USER32MODE) {
4278 //ARMul_CPSRAltered (state);
4279 }
4280 state->Reg[15] += INSN_SIZE;
4281 }
4282 break;
4283 case TRAP_OUT: {
4284 //TEA_OUT(printf("TRAP_OUT\n"));
4285 goto out;
4286 }
4287 break;
4288 case TRAP_BREAKPOINT: {
4289 //TEA_OUT(printf("TRAP_BREAKPOINT\n"));
4290 state->Reg[15] -= INSN_SIZE;
4291 if (!ARMul_OSHandleSWI
4292 (state, SWI_Breakpoint)) {
4293 ARMul_Abort (state, ARMul_SWIV);
4294 }
4295 state->Reg[15] += INSN_SIZE;
4296 }
4297 break;
4298 }
4299
4300next:
4301 if (state->Emulate == ONCE) {
4302 state->Emulate = STOP;
4303 break;
4304 } else if (state->Emulate != RUN) {
4305 break;
4306 }
4307 } while (!state->stop_simulator);
4308
4309out:
4310 state->Reg[15] -= INSN_SIZE;
4311 return (state->Reg[15]);
4312 }
4313#endif
4314//AJ2D--------------------------------------------------------------------------
4315#endif
4316//AJ2D--------------------------------------------------------------------------
4317
4318 /* This routine evaluates most Data Processing register RHS's with the S 3438 /* This routine evaluates most Data Processing register RHS's with the S
4319 bit clear. It is intended to be called from the macro DPRegRHS, which 3439 bit clear. It is intended to be called from the macro DPRegRHS, which
4320 filters the common case of an unshifted register with in line code. */ 3440 filters the common case of an unshifted register with in line code. */
@@ -4672,21 +3792,6 @@ out:
4672 return BITS (0, 3) | (BITS (8, 11) << 4); 3792 return BITS (0, 3) | (BITS (8, 11) << 4);
4673 } 3793 }
4674 3794
4675 /* This function does the work of loading a word for a LDR instruction. */
4676#define MEM_LOAD_LOG(description) if (skyeye_config.log.memlogon >= 1) { \
4677 fprintf(skyeye_logfd, \
4678 "m LOAD %s: N %llx :p %x :i %x :a %x :d %x\n", \
4679 description, state->NumInstrs, state->pc, instr, \
4680 address, dest); \
4681 }
4682
4683#define MEM_STORE_LOG(description) if (skyeye_config.log.memlogon >= 1) { \
4684 fprintf(skyeye_logfd, \
4685 "m STORE %s: N %llx :p %x :i %x :a %x :d %x\n", \
4686 description, state->NumInstrs, state->pc, instr, \
4687 address, DEST); \
4688 }
4689
4690 static unsigned 3795 static unsigned
4691 LoadWord (ARMul_State * state, ARMword instr, ARMword address) { 3796 LoadWord (ARMul_State * state, ARMword instr, ARMword address) {
4692 ARMword dest; 3797 ARMword dest;
@@ -4708,8 +3813,6 @@ out:
4708 WRITEDESTB (dest); 3813 WRITEDESTB (dest);
4709 ARMul_Icycles (state, 1, 0L); 3814 ARMul_Icycles (state, 1, 0L);
4710 3815
4711 //MEM_LOAD_LOG("WORD");
4712
4713 return (DESTReg != LHSReg); 3816 return (DESTReg != LHSReg);
4714 } 3817 }
4715 3818
@@ -4739,8 +3842,6 @@ out:
4739 WRITEDEST (dest); 3842 WRITEDEST (dest);
4740 ARMul_Icycles (state, 1, 0L); 3843 ARMul_Icycles (state, 1, 0L);
4741 3844
4742 //MEM_LOAD_LOG("HALFWORD");
4743
4744 return (DESTReg != LHSReg); 3845 return (DESTReg != LHSReg);
4745 } 3846 }
4746 3847
@@ -4770,8 +3871,6 @@ out:
4770 WRITEDEST (dest); 3871 WRITEDEST (dest);
4771 ARMul_Icycles (state, 1, 0L); 3872 ARMul_Icycles (state, 1, 0L);
4772 3873
4773 //MEM_LOAD_LOG("BYTE");
4774
4775 return (DESTReg != LHSReg); 3874 return (DESTReg != LHSReg);
4776 } 3875 }
4777 3876
@@ -4980,8 +4079,6 @@ out:
4980 4079
4981 static unsigned 4080 static unsigned
4982 StoreWord (ARMul_State * state, ARMword instr, ARMword address) { 4081 StoreWord (ARMul_State * state, ARMword instr, ARMword address) {
4983 //MEM_STORE_LOG("WORD");
4984
4985 BUSUSEDINCPCN; 4082 BUSUSEDINCPCN;
4986#ifndef MODE32 4083#ifndef MODE32
4987 if (DESTReg == 15) 4084 if (DESTReg == 15)
@@ -5009,8 +4106,6 @@ out:
5009 4106
5010 static unsigned 4107 static unsigned
5011 StoreHalfWord (ARMul_State * state, ARMword instr, ARMword address) { 4108 StoreHalfWord (ARMul_State * state, ARMword instr, ARMword address) {
5012 //MEM_STORE_LOG("HALFWORD");
5013
5014 BUSUSEDINCPCN; 4109 BUSUSEDINCPCN;
5015 4110
5016#ifndef MODE32 4111#ifndef MODE32
@@ -5041,8 +4136,6 @@ out:
5041 4136
5042 static unsigned 4137 static unsigned
5043 StoreByte (ARMul_State * state, ARMword instr, ARMword address) { 4138 StoreByte (ARMul_State * state, ARMword instr, ARMword address) {
5044 //MEM_STORE_LOG("BYTE");
5045
5046 BUSUSEDINCPCN; 4139 BUSUSEDINCPCN;
5047#ifndef MODE32 4140#ifndef MODE32
5048 if (DESTReg == 15) 4141 if (DESTReg == 15)
diff --git a/src/core/arm/interpreter/arminit.cpp b/src/core/arm/interpreter/arminit.cpp
index 03bca2870..8ab5ef160 100644
--- a/src/core/arm/interpreter/arminit.cpp
+++ b/src/core/arm/interpreter/arminit.cpp
@@ -15,8 +15,6 @@
15 along with this program; if not, write to the Free Software 15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
17 17
18//#include <unistd.h>
19
20#include "core/arm/skyeye_common/armdefs.h" 18#include "core/arm/skyeye_common/armdefs.h"
21#include "core/arm/skyeye_common/armemu.h" 19#include "core/arm/skyeye_common/armemu.h"
22 20
@@ -24,26 +22,21 @@
24* Definitions for the emulator architecture * 22* Definitions for the emulator architecture *
25\***************************************************************************/ 23\***************************************************************************/
26 24
27void ARMul_EmulateInit (void); 25void ARMul_EmulateInit();
28ARMul_State *ARMul_NewState (ARMul_State * state); 26ARMul_State* ARMul_NewState(ARMul_State* state);
29void ARMul_Reset (ARMul_State * state); 27void ARMul_Reset (ARMul_State* state);
30ARMword ARMul_DoCycle (ARMul_State * state); 28ARMword ARMul_DoCycle(ARMul_State* state);
31unsigned ARMul_DoCoPro (ARMul_State * state); 29unsigned ARMul_DoCoPro(ARMul_State* state);
32ARMword ARMul_DoProg (ARMul_State * state); 30ARMword ARMul_DoProg(ARMul_State* state);
33ARMword ARMul_DoInstr (ARMul_State * state); 31ARMword ARMul_DoInstr(ARMul_State* state);
34void ARMul_Abort (ARMul_State * state, ARMword address); 32void ARMul_Abort(ARMul_State* state, ARMword address);
35 33
36unsigned ARMul_MultTable[32] = { 34unsigned ARMul_MultTable[32] = {
37 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 35 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9,
38 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 16, 16, 16 36 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 16, 16, 16
39}; 37};
40ARMword ARMul_ImmedTable[4096]; /* immediate DP LHS values */ 38ARMword ARMul_ImmedTable[4096]; /* immediate DP LHS values */
41char ARMul_BitList[256]; /* number of bits in a byte table */ 39char ARMul_BitList[256]; /* number of bits in a byte table */
42
43//chy 2006-02-22 add test debugmode
44extern int debugmode;
45extern int remote_interrupt( void );
46
47 40
48void arm_dyncom_Abort(ARMul_State * state, ARMword vector) 41void arm_dyncom_Abort(ARMul_State * state, ARMword vector)
49{ 42{
@@ -51,36 +44,10 @@ void arm_dyncom_Abort(ARMul_State * state, ARMword vector)
51} 44}
52 45
53 46
54/* ahe-ykl : the following code to initialize user mode
55 code is architecture dependent and probably model dependant. */
56
57/*#include "skyeye_arch.h"
58#include "skyeye_pref.h"
59#include "skyeye_exec_info.h"
60#include "bank_defs.h"*/
61//#include "armcpu.h"
62//#include "skyeye_callback.h"
63
64/*
65 ARM_CPU_State* cpu = get_current_cpu();
66 arm_core_t* core = &cpu->core[0];
67
68 uint32_t sp = info->initial_sp;
69
70 core->Cpsr = 0x10; // User mode
71// FIXME: may need to add thumb
72core->Reg[13] = sp;
73core->Reg[10] = info->start_data;
74core->Reg[0] = 0;
75bus_read(32, sp + 4, &(core->Reg[1]));
76bus_read(32, sp + 8, &(core->Reg[2]));
77*/
78/***************************************************************************\ 47/***************************************************************************\
79* Call this routine once to set up the emulator's tables. * 48* Call this routine once to set up the emulator's tables. *
80\***************************************************************************/ 49\***************************************************************************/
81 50void ARMul_EmulateInit()
82void
83ARMul_EmulateInit (void)
84{ 51{
85 unsigned int i, j; 52 unsigned int i, j;
86 53
@@ -102,9 +69,7 @@ ARMul_EmulateInit (void)
102/***************************************************************************\ 69/***************************************************************************\
103* Returns a new instantiation of the ARMulator's state * 70* Returns a new instantiation of the ARMulator's state *
104\***************************************************************************/ 71\***************************************************************************/
105 72ARMul_State* ARMul_NewState(ARMul_State* state)
106ARMul_State *
107ARMul_NewState (ARMul_State *state)
108{ 73{
109 unsigned i, j; 74 unsigned i, j;
110 75
@@ -120,7 +85,6 @@ ARMul_NewState (ARMul_State *state)
120 state->Spsr[i] = 0; 85 state->Spsr[i] = 0;
121 state->Mode = 0; 86 state->Mode = 0;
122 87
123 state->CallDebug = FALSE;
124 state->Debug = FALSE; 88 state->Debug = FALSE;
125 state->VectorCatch = 0; 89 state->VectorCatch = 0;
126 state->Aborted = FALSE; 90 state->Aborted = FALSE;
@@ -128,34 +92,6 @@ ARMul_NewState (ARMul_State *state)
128 state->Inted = 3; 92 state->Inted = 3;
129 state->LastInted = 3; 93 state->LastInted = 3;
130 94
131 state->CommandLine = NULL;
132
133 state->EventSet = 0;
134 state->Now = 0;
135 state->EventPtr =
136 (struct EventNode **) malloc ((unsigned) EVENTLISTSIZE *
137 sizeof (struct EventNode *));
138#if DIFF_STATE
139 state->state_log = fopen("/data/state.log", "w");
140 printf("create pc log file.\n");
141#endif
142 if (state->EventPtr == NULL) {
143 printf ("SKYEYE: ARMul_NewState malloc state->EventPtr error\n");
144 exit(-1);
145 //skyeye_exit (-1);
146 }
147 for (i = 0; i < EVENTLISTSIZE; i++)
148 *(state->EventPtr + i) = NULL;
149#if SAVE_LOG
150 state->state_log = fopen("/tmp/state.log", "w");
151 printf("create pc log file.\n");
152#else
153#if DIFF_LOG
154 state->state_log = fopen("/tmp/state.log", "r");
155 printf("loaded pc log file.\n");
156#endif
157#endif
158
159#ifdef ARM61 95#ifdef ARM61
160 state->prog32Sig = LOW; 96 state->prog32Sig = LOW;
161 state->data32Sig = LOW; 97 state->data32Sig = LOW;
@@ -168,28 +104,19 @@ ARMul_NewState (ARMul_State *state)
168 state->bigendSig = LOW; 104 state->bigendSig = LOW;
169 105
170 //chy:2003-08-19 106 //chy:2003-08-19
171 state->LastTime = 0;
172 state->CP14R0_CCD = -1; 107 state->CP14R0_CCD = -1;
173 108
174 /* ahe-ykl: common function for interpret and dyncom */
175 /*sky_pref_t *pref = get_skyeye_pref();
176 if (pref->user_mode_sim)
177 register_callback(arm_user_mode_init, Bootmach_callback);
178 */
179
180 memset(&state->exclusive_tag_array[0], 0xFF, sizeof(state->exclusive_tag_array[0]) * 128); 109 memset(&state->exclusive_tag_array[0], 0xFF, sizeof(state->exclusive_tag_array[0]) * 128);
181 state->exclusive_access_state = 0; 110 state->exclusive_access_state = 0;
182 //state->cpu = (cpu_config_t *) malloc (sizeof (cpu_config_t)); 111
183 //state->mem_bank = (mem_config_t *) malloc (sizeof (mem_config_t)); 112 return state;
184 return (state);
185} 113}
186 114
187/***************************************************************************\ 115/***************************************************************************\
188* Call this routine to set ARMulator to model a certain processor * 116* Call this routine to set ARMulator to model a certain processor *
189\***************************************************************************/ 117\***************************************************************************/
190 118
191void 119void ARMul_SelectProcessor(ARMul_State* state, unsigned properties)
192ARMul_SelectProcessor (ARMul_State * state, unsigned properties)
193{ 120{
194 if (properties & ARM_Fix26_Prop) { 121 if (properties & ARM_Fix26_Prop) {
195 state->prog32Sig = LOW; 122 state->prog32Sig = LOW;
@@ -198,27 +125,16 @@ ARMul_SelectProcessor (ARMul_State * state, unsigned properties)
198 state->prog32Sig = HIGH; 125 state->prog32Sig = HIGH;
199 state->data32Sig = HIGH; 126 state->data32Sig = HIGH;
200 } 127 }
201 /* 2004-05-09 chy
202 below line sould be in skyeye_mach_XXX.c 's XXX_mach_init function
203 */
204 // state->lateabtSig = HIGH;
205 128
206 129 state->is_v4 = (properties & (ARM_v4_Prop | ARM_v5_Prop)) ? HIGH : LOW;
207 state->is_v4 = 130 state->is_v5 = (properties & ARM_v5_Prop) ? HIGH : LOW;
208 (properties & (ARM_v4_Prop | ARM_v5_Prop)) ? HIGH : LOW; 131 state->is_v5e = (properties & ARM_v5e_Prop) ? HIGH : LOW;
209 state->is_v5 = (properties & ARM_v5_Prop) ? HIGH : LOW;
210 state->is_v5e = (properties & ARM_v5e_Prop) ? HIGH : LOW;
211 state->is_XScale = (properties & ARM_XScale_Prop) ? HIGH : LOW; 132 state->is_XScale = (properties & ARM_XScale_Prop) ? HIGH : LOW;
212 state->is_iWMMXt = (properties & ARM_iWMMXt_Prop) ? HIGH : LOW; 133 state->is_iWMMXt = (properties & ARM_iWMMXt_Prop) ? HIGH : LOW;
213 /* state->is_v6 = LOW */; 134 state->is_v6 = (properties & ARM_v6_Prop) ? HIGH : LOW;
214 /* jeff.du 2010-08-05 */
215 state->is_v6 = (properties & ARM_v6_Prop) ? HIGH : LOW;
216 state->is_ep9312 = (properties & ARM_ep9312_Prop) ? HIGH : LOW; 135 state->is_ep9312 = (properties & ARM_ep9312_Prop) ? HIGH : LOW;
217 //chy 2005-09-19
218 state->is_pxa27x = (properties & ARM_PXA27X_Prop) ? HIGH : LOW; 136 state->is_pxa27x = (properties & ARM_PXA27X_Prop) ? HIGH : LOW;
219 137 state->is_v7 = (properties & ARM_v7_Prop) ? HIGH : LOW;
220 /* shenoubang 2012-3-11 */
221 state->is_v7 = (properties & ARM_v7_Prop) ? HIGH : LOW;
222 138
223 /* Only initialse the coprocessor support once we 139 /* Only initialse the coprocessor support once we
224 know what kind of chip we are dealing with. */ 140 know what kind of chip we are dealing with. */
@@ -229,11 +145,8 @@ ARMul_SelectProcessor (ARMul_State * state, unsigned properties)
229/***************************************************************************\ 145/***************************************************************************\
230* Call this routine to set up the initial machine state (or perform a RESET * 146* Call this routine to set up the initial machine state (or perform a RESET *
231\***************************************************************************/ 147\***************************************************************************/
232 148void ARMul_Reset(ARMul_State* state)
233void
234ARMul_Reset (ARMul_State * state)
235{ 149{
236 //fprintf(stderr,"armul_reset 0: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode);
237 state->NextInstr = 0; 150 state->NextInstr = 0;
238 if (state->prog32Sig) { 151 if (state->prog32Sig) {
239 state->Reg[15] = 0; 152 state->Reg[15] = 0;
@@ -244,15 +157,13 @@ ARMul_Reset (ARMul_State * state)
244 state->Cpsr = INTBITS | SVC26MODE; 157 state->Cpsr = INTBITS | SVC26MODE;
245 state->Mode = SVC26MODE; 158 state->Mode = SVC26MODE;
246 } 159 }
247 //fprintf(stderr,"armul_reset 1: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode); 160
248 //ARMul_CPSRAltered (state);
249 state->Bank = SVCBANK; 161 state->Bank = SVCBANK;
250 FLUSHPIPE; 162 FLUSHPIPE;
251 163
252 state->EndCondition = 0; 164 state->EndCondition = 0;
253 state->ErrorCode = 0; 165 state->ErrorCode = 0;
254 166
255 //fprintf(stderr,"armul_reset 2: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode);
256 state->NresetSig = HIGH; 167 state->NresetSig = HIGH;
257 state->NfiqSig = HIGH; 168 state->NfiqSig = HIGH;
258 state->NirqSig = HIGH; 169 state->NirqSig = HIGH;
@@ -266,33 +177,6 @@ ARMul_Reset (ARMul_State * state)
266 state->NumIcycles = 0; 177 state->NumIcycles = 0;
267 state->NumCcycles = 0; 178 state->NumCcycles = 0;
268 state->NumFcycles = 0; 179 state->NumFcycles = 0;
269
270 //fprintf(stderr,"armul_reset 3: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode);
271 //mmu_reset (state);
272 //fprintf(stderr,"armul_reset 4: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode);
273
274 //mem_reset (state); /* move to memory/ram.c */
275
276 //fprintf(stderr,"armul_reset 5: state-> Cpsr 0x%x, Mode %d\n",state->Cpsr,state->Mode);
277 /*remove later. walimis 03.7.17 */
278 //io_reset(state);
279 //lcd_disable(state);
280
281 /*ywc 2005-04-07 move from ARMul_NewState , because skyeye_config.no_dbct will
282 *be configured in skyeye_option_init and it is called after ARMul_NewState*/
283 state->tea_break_ok = 0;
284 state->tea_break_addr = 0;
285 state->tea_pc = 0;
286#ifdef DBCT
287 if (!skyeye_config.no_dbct) {
288 //teawater add for arm2x86 2005.02.14-------------------------------------------
289 if (arm2x86_init (state)) {
290 printf ("SKYEYE: arm2x86_init error\n");
291 //skyeye_exit (-1);
292 }
293 //AJ2D--------------------------------------------------------------------------
294 }
295#endif
296} 180}
297 181
298 182
@@ -301,108 +185,23 @@ ARMul_Reset (ARMul_State * state)
301* (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the * 185* (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the *
302* address of the last instruction that is executed. * 186* address of the last instruction that is executed. *
303\***************************************************************************/ 187\***************************************************************************/
304 188ARMword ARMul_DoProg(ARMul_State* state)
305//teawater add DBCT_TEST_SPEED 2005.10.04---------------------------------------
306#ifdef DBCT_TEST_SPEED
307static ARMul_State *dbct_test_speed_state = NULL;
308static void
309dbct_test_speed_sig(int signo)
310{
311 printf("\n0x%llx %llu\n", dbct_test_speed_state->instr_count, dbct_test_speed_state->instr_count);
312 exit(0);
313 //skyeye_exit(0);
314}
315#endif //DBCT_TEST_SPEED
316//AJ2D--------------------------------------------------------------------------
317
318ARMword
319ARMul_DoProg (ARMul_State * state)
320{ 189{
321 ARMword pc = 0; 190 ARMword pc = 0;
322 191
323 /*
324 * 2007-01-24 removed the term-io functions by Anthony Lee,
325 * moved to "device/uart/skyeye_uart_stdio.c".
326 */
327
328//teawater add DBCT_TEST_SPEED 2005.10.04---------------------------------------
329#ifdef DBCT_TEST_SPEED
330 {
331 if (!dbct_test_speed_state) {
332 //init timer
333 struct itimerval value;
334 struct sigaction act;
335
336 dbct_test_speed_state = state;
337 state->instr_count = 0;
338 act.sa_handler = dbct_test_speed_sig;
339 act.sa_flags = SA_RESTART;
340 //cygwin don't support ITIMER_VIRTUAL or ITIMER_PROF
341#ifndef __CYGWIN__
342 if (sigaction(SIGVTALRM, &act, NULL) == -1) {
343#else
344 if (sigaction(SIGALRM, &act, NULL) == -1) {
345#endif //__CYGWIN__
346 fprintf(stderr, "init timer error.\n");
347 exit(-1);
348 //skyeye_exit(-1);
349 }
350 if (skyeye_config.dbct_test_speed_sec) {
351 value.it_value.tv_sec = skyeye_config.dbct_test_speed_sec;
352 } else {
353 value.it_value.tv_sec = DBCT_TEST_SPEED_SEC;
354 }
355 printf("dbct_test_speed_sec = %ld\n", value.it_value.tv_sec);
356 value.it_value.tv_usec = 0;
357 value.it_interval.tv_sec = 0;
358 value.it_interval.tv_usec = 0;
359#ifndef __CYGWIN__
360 if (setitimer(ITIMER_VIRTUAL, &value, NULL) == -1) {
361#else
362 if (setitimer(ITIMER_REAL, &value, NULL) == -1) {
363#endif //__CYGWIN__
364 fprintf(stderr, "init timer error.\n");
365 //skyeye_exit(-1);
366 }
367 }
368 }
369#endif //DBCT_TEST_SPEED
370//AJ2D--------------------------------------------------------------------------
371 state->Emulate = RUN; 192 state->Emulate = RUN;
372 while (state->Emulate != STOP) { 193 while (state->Emulate != STOP) {
373 state->Emulate = RUN; 194 state->Emulate = RUN;
374 195
375 /*ywc 2005-03-31 */
376 if (state->prog32Sig && ARMul_MODE32BIT) { 196 if (state->prog32Sig && ARMul_MODE32BIT) {
377#ifdef DBCT
378 if (skyeye_config.no_dbct) {
379 pc = ARMul_Emulate32 (state);
380 } else {
381 pc = ARMul_Emulate32_dbct (state);
382 }
383#else
384 pc = ARMul_Emulate32 (state); 197 pc = ARMul_Emulate32 (state);
385#endif
386 } 198 }
387
388 else { 199 else {
389 //pc = ARMul_Emulate26 (state); 200 //pc = ARMul_Emulate26 (state);
390 } 201 }
391 //chy 2006-02-22, should test debugmode first
392 //chy 2006-04-14, put below codes in ARMul_Emulate
393#if 0
394 if(debugmode)
395 if(remote_interrupt())
396 state->Emulate = STOP;
397#endif
398 } 202 }
399 203
400 /* 204 return pc;
401 * 2007-01-24 removed the term-io functions by Anthony Lee,
402 * moved to "device/uart/skyeye_uart_stdio.c".
403 */
404
405 return (pc);
406} 205}
407 206
408/***************************************************************************\ 207/***************************************************************************\
@@ -410,38 +209,17 @@ ARMul_DoProg (ARMul_State * state)
410* (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the * 209* (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the *
411* address of the instruction that is executed. * 210* address of the instruction that is executed. *
412\***************************************************************************/ 211\***************************************************************************/
413 212ARMword ARMul_DoInstr(ARMul_State* state)
414ARMword
415ARMul_DoInstr (ARMul_State * state)
416{ 213{
417 ARMword pc = 0; 214 ARMword pc = 0;
418 215
419 state->Emulate = ONCE; 216 state->Emulate = ONCE;
420 217
421 /*ywc 2005-03-31 */
422 if (state->prog32Sig && ARMul_MODE32BIT) { 218 if (state->prog32Sig && ARMul_MODE32BIT) {
423#ifdef DBCT
424 if (skyeye_config.no_dbct) {
425 pc = ARMul_Emulate32 (state);
426 } else {
427//teawater add compile switch for DBCT GDB RSP function 2005.10.21--------------
428#ifndef DBCT_GDBRSP
429 printf("DBCT GDBRSP function switch is off.\n");
430 printf("To use this function, open \"#define DBCT_GDBRSP\" in arch/arm/common/armdefs.h & recompile skyeye.\n");
431 skyeye_exit(-1);
432#endif //DBCT_GDBRSP
433//AJ2D--------------------------------------------------------------------------
434 pc = ARMul_Emulate32_dbct (state);
435 }
436#else
437 pc = ARMul_Emulate32 (state); 219 pc = ARMul_Emulate32 (state);
438#endif
439 } 220 }
440 221
441 //else 222 return pc;
442 //pc = ARMul_Emulate26 (state);
443
444 return (pc);
445} 223}
446 224
447/***************************************************************************\ 225/***************************************************************************\
@@ -449,9 +227,7 @@ ARMul_DoInstr (ARMul_State * state)
449* mode, register bank, and the saving of registers. Call with the * 227* mode, register bank, and the saving of registers. Call with the *
450* appropriate vector's memory address (0,4,8 ....) * 228* appropriate vector's memory address (0,4,8 ....) *
451\***************************************************************************/ 229\***************************************************************************/
452 230void ARMul_Abort(ARMul_State* state, ARMword vector)
453void
454ARMul_Abort (ARMul_State * state, ARMword vector)
455{ 231{
456 ARMword temp; 232 ARMword temp;
457 int isize = INSN_SIZE; 233 int isize = INSN_SIZE;
@@ -494,21 +270,11 @@ ARMul_Abort (ARMul_State * state, ARMword vector)
494 SETABORT (IBIT, SVC26MODE, isize); 270 SETABORT (IBIT, SVC26MODE, isize);
495 break; 271 break;
496 case ARMul_IRQV: /* IRQ */ 272 case ARMul_IRQV: /* IRQ */
497 //chy 2003-09-02 the if sentence seems no use
498#if 0
499 if (!state->is_XScale || !state->CPRead[13] (state, 0, &temp)
500 || (temp & ARMul_CP13_R0_IRQ))
501#endif
502 SETABORT (IBIT, 273 SETABORT (IBIT,
503 state->prog32Sig ? IRQ32MODE : IRQ26MODE, 274 state->prog32Sig ? IRQ32MODE : IRQ26MODE,
504 esize); 275 esize);
505 break; 276 break;
506 case ARMul_FIQV: /* FIQ */ 277 case ARMul_FIQV: /* FIQ */
507 //chy 2003-09-02 the if sentence seems no use
508#if 0
509 if (!state->is_XScale || !state->CPRead[13] (state, 0, &temp)
510 || (temp & ARMul_CP13_R0_FIQ))
511#endif
512 SETABORT (INTBITS, 278 SETABORT (INTBITS,
513 state->prog32Sig ? FIQ32MODE : FIQ26MODE, 279 state->prog32Sig ? FIQ32MODE : FIQ26MODE,
514 esize); 280 esize);
diff --git a/src/core/arm/interpreter/armsupp.cpp b/src/core/arm/interpreter/armsupp.cpp
index e2626eefb..5a8f09b22 100644
--- a/src/core/arm/interpreter/armsupp.cpp
+++ b/src/core/arm/interpreter/armsupp.cpp
@@ -22,13 +22,6 @@
22 22
23 23
24static ARMword ModeToBank (ARMword); 24static ARMword ModeToBank (ARMword);
25static void EnvokeList (ARMul_State *, unsigned int, unsigned int);
26
27struct EventNode {
28 /* An event list node. */
29 unsigned (*func) (ARMul_State *); /* The function to call. */
30 struct EventNode *next;
31};
32 25
33/* This routine returns the value of a register from a mode. */ 26/* This routine returns the value of a register from a mode. */
34 27
@@ -1068,76 +1061,3 @@ ARMul_Align (ARMul_State* state, ARMword address, ARMword data)
1068 address = (address & 3) << 3; /* Get the word address. */ 1061 address = (address & 3) << 3; /* Get the word address. */
1069 return ((data >> address) | (data << (32 - address))); /* rot right */ 1062 return ((data >> address) | (data << (32 - address))); /* rot right */
1070} 1063}
1071
1072/* This routine is used to call another routine after a certain number of
1073 cycles have been executed. The first parameter is the number of cycles
1074 delay before the function is called, the second argument is a pointer
1075 to the function. A delay of zero doesn't work, just call the function. */
1076
1077void
1078ARMul_ScheduleEvent (ARMul_State * state, unsigned int delay,
1079 unsigned (*what) (ARMul_State *))
1080{
1081 unsigned int when;
1082 struct EventNode *event;
1083
1084 if (state->EventSet++ == 0)
1085 state->Now = ARMul_Time (state);
1086 when = (state->Now + delay) % EVENTLISTSIZE;
1087 event = (struct EventNode *) malloc (sizeof (struct EventNode));
1088 if (!event) {
1089 printf ("SKYEYE:ARMul_ScheduleEvent: malloc event error\n");
1090 exit(-1);
1091 //skyeye_exit (-1);
1092 }
1093 event->func = what;
1094 event->next = *(state->EventPtr + when);
1095 *(state->EventPtr + when) = event;
1096}
1097
1098/* This routine is called at the beginning of
1099 every cycle, to envoke scheduled events. */
1100
1101void
1102ARMul_EnvokeEvent (ARMul_State * state)
1103{
1104 static unsigned int then;
1105
1106 then = state->Now;
1107 state->Now = ARMul_Time (state) % EVENTLISTSIZE;
1108 if (then < state->Now)
1109 /* Schedule events. */
1110 EnvokeList (state, then, state->Now);
1111 else if (then > state->Now) {
1112 /* Need to wrap around the list. */
1113 EnvokeList (state, then, EVENTLISTSIZE - 1L);
1114 EnvokeList (state, 0L, state->Now);
1115 }
1116}
1117
1118/* Envokes all the entries in a range. */
1119
1120static void
1121EnvokeList (ARMul_State * state, unsigned int from, unsigned int to)
1122{
1123 for (; from <= to; from++) {
1124 struct EventNode *anevent;
1125
1126 anevent = *(state->EventPtr + from);
1127 while (anevent) {
1128 (anevent->func) (state);
1129 state->EventSet--;
1130 anevent = anevent->next;
1131 }
1132 *(state->EventPtr + from) = NULL;
1133 }
1134}
1135
1136/* This routine is returns the number of clock ticks since the last reset. */
1137
1138unsigned int
1139ARMul_Time (ARMul_State * state)
1140{
1141 return (state->NumScycles + state->NumNcycles +
1142 state->NumIcycles + state->NumCcycles + state->NumFcycles);
1143}
diff --git a/src/core/arm/skyeye_common/armdefs.h b/src/core/arm/skyeye_common/armdefs.h
index 560b51a9f..a9c41ce5a 100644
--- a/src/core/arm/skyeye_common/armdefs.h
+++ b/src/core/arm/skyeye_common/armdefs.h
@@ -15,8 +15,7 @@
15 along with this program; if not, write to the Free Software 15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
17 17
18#ifndef _ARMDEFS_H_ 18#pragma once
19#define _ARMDEFS_H_
20 19
21#include <cerrno> 20#include <cerrno>
22#include <csignal> 21#include <csignal>
@@ -33,21 +32,6 @@
33#include "core/arm/skyeye_common/armmmu.h" 32#include "core/arm/skyeye_common/armmmu.h"
34#include "core/arm/skyeye_common/skyeye_defs.h" 33#include "core/arm/skyeye_common/skyeye_defs.h"
35 34
36#if EMU_PLATFORM == PLATFORM_LINUX
37#include <sys/time.h>
38#include <unistd.h>
39#endif
40
41#if 0
42#if 0
43#define DIFF_STATE 1
44#define __FOLLOW_MODE__ 0
45#else
46#define DIFF_STATE 0
47#define __FOLLOW_MODE__ 1
48#endif
49#endif
50
51#ifndef FALSE 35#ifndef FALSE
52#define FALSE 0 36#define FALSE 0
53#define TRUE 1 37#define TRUE 1
@@ -58,13 +42,6 @@
58#define LOWHIGH 1 42#define LOWHIGH 1
59#define HIGHLOW 2 43#define HIGHLOW 2
60 44
61//#define DBCT_TEST_SPEED
62#define DBCT_TEST_SPEED_SEC 10
63
64#define ARM_BYTE_TYPE 0
65#define ARM_HALFWORD_TYPE 1
66#define ARM_WORD_TYPE 2
67
68//the define of cachetype 45//the define of cachetype
69#define NONCACHE 0 46#define NONCACHE 0
70#define DATACACHE 1 47#define DATACACHE 1
@@ -73,18 +50,11 @@
73#define POS(i) ( (~(i)) >> 31 ) 50#define POS(i) ( (~(i)) >> 31 )
74#define NEG(i) ( (i) >> 31 ) 51#define NEG(i) ( (i) >> 31 )
75 52
76#ifndef __STDC__
77typedef char *VoidStar;
78#endif
79
80typedef u64 ARMdword; // must be 64 bits wide 53typedef u64 ARMdword; // must be 64 bits wide
81typedef u32 ARMword; // must be 32 bits wide 54typedef u32 ARMword; // must be 32 bits wide
82typedef u16 ARMhword; // must be 16 bits wide 55typedef u16 ARMhword; // must be 16 bits wide
83typedef u8 ARMbyte; // must be 8 bits wide 56typedef u8 ARMbyte; // must be 8 bits wide
84typedef struct ARMul_State ARMul_State; 57typedef struct ARMul_State ARMul_State;
85typedef struct ARMul_io ARMul_io;
86typedef struct ARMul_Energy ARMul_Energy;
87
88 58
89typedef unsigned ARMul_CPInits(ARMul_State* state); 59typedef unsigned ARMul_CPInits(ARMul_State* state);
90typedef unsigned ARMul_CPExits(ARMul_State* state); 60typedef unsigned ARMul_CPExits(ARMul_State* state);
@@ -98,65 +68,6 @@ typedef unsigned ARMul_CDPs(ARMul_State* state, unsigned type, ARMword instr);
98typedef unsigned ARMul_CPReads(ARMul_State* state, unsigned reg, ARMword* value); 68typedef unsigned ARMul_CPReads(ARMul_State* state, unsigned reg, ARMword* value);
99typedef unsigned ARMul_CPWrites(ARMul_State* state, unsigned reg, ARMword value); 69typedef unsigned ARMul_CPWrites(ARMul_State* state, unsigned reg, ARMword value);
100 70
101
102//added by ksh,2004-3-5
103struct ARMul_io
104{
105 ARMword *instr; // to display the current interrupt state
106 ARMword *net_flag; // to judge if network is enabled
107 ARMword *net_int; // netcard interrupt
108
109 //ywc,2004-04-01
110 ARMword *ts_int;
111 ARMword *ts_is_enable;
112 ARMword *ts_addr_begin;
113 ARMword *ts_addr_end;
114 ARMword *ts_buffer;
115};
116
117/* added by ksh,2004-11-26,some energy profiling */
118struct ARMul_Energy
119{
120 int energy_prof; /* <tktan> BUG200103282109 : for energy profiling */
121 int enable_func_energy; /* <tktan> BUG200105181702 */
122 char *func_energy;
123 int func_display; /* <tktan> BUG200103311509 : for function call display */
124 int func_disp_start; /* <tktan> BUG200104191428 : to start func profiling */
125 char *start_func; /* <tktan> BUG200104191428 */
126
127 FILE *outfile; /* <tktan> BUG200105201531 : direct console to file */
128 long long tcycle, pcycle;
129 float t_energy;
130 void *cur_task; /* <tktan> BUG200103291737 */
131 long long t_mem_cycle, t_idle_cycle, t_uart_cycle;
132 long long p_mem_cycle, p_idle_cycle, p_uart_cycle;
133 long long p_io_update_tcycle;
134 /*record CCCR,to get current core frequency */
135 ARMword cccr;
136};
137#if 0
138#define MAX_BANK 8
139#define MAX_STR 1024
140
141typedef struct mem_bank
142{
143 ARMword (*read_byte) (ARMul_State* state, ARMword addr);
144 void (*write_byte) (ARMul_State* state, ARMword addr, ARMword data);
145 ARMword (*read_halfword) (ARMul_State* state, ARMword addr);
146 void (*write_halfword) (ARMul_State* state, ARMword addr, ARMword data);
147 ARMword (*read_word) (ARMul_State* state, ARMword addr);
148 void (*write_word) (ARMul_State* state, ARMword addr, ARMword data);
149 unsigned int addr, len;
150 char filename[MAX_STR];
151 unsigned type; //chy 2003-09-21: maybe io,ram,rom
152} mem_bank_t;
153typedef struct
154{
155 int bank_num;
156 int current_num; /*current num of bank */
157 mem_bank_t mem_banks[MAX_BANK];
158} mem_config_t;
159#endif
160#define VFP_REG_NUM 64 71#define VFP_REG_NUM 64
161struct ARMul_State 72struct ARMul_State
162{ 73{
@@ -196,9 +107,8 @@ struct ARMul_State
196 ARMdword Accumulator; 107 ARMdword Accumulator;
197 108
198 ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags; /* dummy flags for speed */ 109 ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags; /* dummy flags for speed */
199 unsigned long long int icounter, debug_icounter, kernel_icounter; 110 unsigned long long int icounter, debug_icounter, kernel_icounter;
200 unsigned int shifter_carry_out; 111 unsigned int shifter_carry_out;
201 //ARMword translate_pc;
202 112
203 /* add armv6 flags dyf:2010-08-09 */ 113 /* add armv6 flags dyf:2010-08-09 */
204 ARMword GEFlag, EFlag, AFlag, QFlag; 114 ARMword GEFlag, EFlag, AFlag, QFlag;
@@ -226,9 +136,6 @@ struct ARMul_State
226 unsigned CanWatch; /* set by memory interface if its willing to suffer the 136 unsigned CanWatch; /* set by memory interface if its willing to suffer the
227 overhead of checking for watchpoints on each memory 137 overhead of checking for watchpoints on each memory
228 access */ 138 access */
229 unsigned int StopHandle;
230
231 char *CommandLine; /* Command Line from ARMsd */
232 139
233 ARMul_CPInits *CPInit[16]; /* coprocessor initialisers */ 140 ARMul_CPInits *CPInit[16]; /* coprocessor initialisers */
234 ARMul_CPExits *CPExit[16]; /* coprocessor finalisers */ 141 ARMul_CPExits *CPExit[16]; /* coprocessor finalisers */
@@ -244,10 +151,6 @@ struct ARMul_State
244 unsigned char *CPData[16]; /* Coprocessor data */ 151 unsigned char *CPData[16]; /* Coprocessor data */
245 unsigned char const *CPRegWords[16]; /* map of coprocessor register sizes */ 152 unsigned char const *CPRegWords[16]; /* map of coprocessor register sizes */
246 153
247 unsigned EventSet; /* the number of events in the queue */
248 unsigned int Now; /* time to the nearest cycle */
249 struct EventNode **EventPtr; /* the event list */
250
251 unsigned Debug; /* show instructions as they are executed */ 154 unsigned Debug; /* show instructions as they are executed */
252 unsigned NresetSig; /* reset the processor */ 155 unsigned NresetSig; /* reset the processor */
253 unsigned NfiqSig; 156 unsigned NfiqSig;
@@ -300,17 +203,9 @@ So, if lateabtSig=1, then it means Late Abort Model(Base Updated Abort Model)
300 ARMword Base; /* extra hand for base writeback */ 203 ARMword Base; /* extra hand for base writeback */
301 ARMword AbortAddr; /* to keep track of Prefetch aborts */ 204 ARMword AbortAddr; /* to keep track of Prefetch aborts */
302 205
303 const struct Dbg_HostosInterface *hostif;
304
305 int verbose; /* non-zero means print various messages like the banner */ 206 int verbose; /* non-zero means print various messages like the banner */
306 207
307 int mmu_inited; 208 int mmu_inited;
308 //mem_state_t mem;
309 /*remove io_state to skyeye_mach_*.c files */
310 //io_state_t io;
311 /* point to a interrupt pending register. now for skyeye-ne2k.c
312 * later should move somewhere. e.g machine_config_t*/
313
314 209
315 //chy: 2003-08-11, for different arm core type 210 //chy: 2003-08-11, for different arm core type
316 unsigned is_v4; /* Are we emulating a v4 architecture (or higher) ? */ 211 unsigned is_v4; /* Are we emulating a v4 architecture (or higher) ? */
@@ -321,44 +216,17 @@ So, if lateabtSig=1, then it means Late Abort Model(Base Updated Abort Model)
321 unsigned is_XScale; /* Are we emulating an XScale architecture ? */ 216 unsigned is_XScale; /* Are we emulating an XScale architecture ? */
322 unsigned is_iWMMXt; /* Are we emulating an iWMMXt co-processor ? */ 217 unsigned is_iWMMXt; /* Are we emulating an iWMMXt co-processor ? */
323 unsigned is_ep9312; /* Are we emulating a Cirrus Maverick co-processor ? */ 218 unsigned is_ep9312; /* Are we emulating a Cirrus Maverick co-processor ? */
324 //chy 2005-09-19
325 unsigned is_pxa27x; /* Are we emulating a Intel PXA27x co-processor ? */ 219 unsigned is_pxa27x; /* Are we emulating a Intel PXA27x co-processor ? */
220
326 //chy: seems only used in xscale's CP14 221 //chy: seems only used in xscale's CP14
327 unsigned int LastTime; /* Value of last call to ARMul_Time() */
328 ARMword CP14R0_CCD; /* used to count 64 clock cycles with CP14 R0 bit 3 set */ 222 ARMword CP14R0_CCD; /* used to count 64 clock cycles with CP14 R0 bit 3 set */
329 223
330
331 //added by ksh:for handle different machs io 2004-3-5
332 ARMul_io mach_io;
333
334 /*added by ksh,2004-11-26,some energy profiling*/
335 ARMul_Energy energy;
336
337 //teawater add for next_dis 2004.10.27-----------------------
338 int disassemble;
339
340
341 //teawater add for arm2x86 2005.02.15-------------------------------------------
342 u32 trap;
343 u32 tea_break_addr;
344 u32 tea_break_ok;
345 int tea_pc;
346
347 //teawater add for arm2x86 2005.07.05------------------------------------------- 224 //teawater add for arm2x86 2005.07.05-------------------------------------------
348 //arm_arm A2-18 225 //arm_arm A2-18
349 int abort_model; //0 Base Restored Abort Model, 1 the Early Abort Model, 2 Base Updated Abort Model 226 int abort_model; //0 Base Restored Abort Model, 1 the Early Abort Model, 2 Base Updated Abort Model
350
351 //teawater change for return if running tb dirty 2005.07.09---------------------
352 void *tb_now;
353
354
355 //teawater add for record reg value to ./reg.txt 2005.07.10---------------------
356 FILE *tea_reg_fd;
357
358 227
359 /*added by ksh in 2005-10-1*/ 228 /*added by ksh in 2005-10-1*/
360 cpu_config_t *cpu; 229 cpu_config_t *cpu;
361 //mem_config_t *mem_bank;
362 230
363 /* added LPC remap function */ 231 /* added LPC remap function */
364 int vector_remap_flag; 232 int vector_remap_flag;
@@ -367,23 +235,12 @@ So, if lateabtSig=1, then it means Late Abort Model(Base Updated Abort Model)
367 235
368 u32 step; 236 u32 step;
369 u32 cycle; 237 u32 cycle;
370 int stop_simulator; 238
371 conf_object_t *dyncom_cpu;
372//teawater add DBCT_TEST_SPEED 2005.10.04---------------------------------------
373#ifdef DBCT_TEST_SPEED
374 uint64_t instr_count;
375#endif //DBCT_TEST_SPEED
376// FILE * state_log;
377//diff log
378//#if DIFF_STATE
379 FILE * state_log;
380//#endif
381 /* monitored memory for exclusice access */ 239 /* monitored memory for exclusice access */
382 ARMword exclusive_tag_array[128]; 240 ARMword exclusive_tag_array[128];
383 /* 1 means exclusive access and 0 means open access */ 241 /* 1 means exclusive access and 0 means open access */
384 ARMword exclusive_access_state; 242 ARMword exclusive_access_state;
385 243
386 memory_space_intf space;
387 u32 CurrInstr; 244 u32 CurrInstr;
388 u32 last_pc; /* the last pc executed */ 245 u32 last_pc; /* the last pc executed */
389 u32 last_instr; /* the last inst executed */ 246 u32 last_instr; /* the last inst executed */
@@ -392,56 +249,43 @@ So, if lateabtSig=1, then it means Late Abort Model(Base Updated Abort Model)
392 u32 WritePc[17]; 249 u32 WritePc[17];
393 u32 CurrWrite; 250 u32 CurrWrite;
394}; 251};
395#define DIFF_WRITE 0
396 252
397typedef ARMul_State arm_core_t; 253typedef ARMul_State arm_core_t;
398#define ResetPin NresetSig
399#define FIQPin NfiqSig
400#define IRQPin NirqSig
401#define AbortPin abortSig
402#define TransPin NtransSig
403#define BigEndPin bigendSig
404#define Prog32Pin prog32Sig
405#define Data32Pin data32Sig
406#define LateAbortPin lateabtSig
407 254
408/***************************************************************************\ 255/***************************************************************************\
409* Types of ARM we know about * 256* Types of ARM we know about *
410\***************************************************************************/ 257\***************************************************************************/
411 258
412/* The bitflags */ 259enum {
413#define ARM_Fix26_Prop 0x01 260 ARM_Fix26_Prop = 0x01,
414#define ARM_Nexec_Prop 0x02 261 ARM_Nexec_Prop = 0x02,
415#define ARM_Debug_Prop 0x10 262 ARM_Debug_Prop = 0x10,
416#define ARM_Isync_Prop ARM_Debug_Prop 263 ARM_Isync_Prop = ARM_Debug_Prop,
417#define ARM_Lock_Prop 0x20 264 ARM_Lock_Prop = 0x20,
418#define ARM_v4_Prop 0x40 265 ARM_v4_Prop = 0x40,
419#define ARM_v5_Prop 0x80 266 ARM_v5_Prop = 0x80,
420#define ARM_v6_Prop 0xc0 267 ARM_v6_Prop = 0xc0,
421 268
422#define ARM_v5e_Prop 0x100 269 ARM_v5e_Prop = 0x100,
423#define ARM_XScale_Prop 0x200 270 ARM_XScale_Prop = 0x200,
424#define ARM_ep9312_Prop 0x400 271 ARM_ep9312_Prop = 0x400,
425#define ARM_iWMMXt_Prop 0x800 272 ARM_iWMMXt_Prop = 0x800,
426#define ARM_PXA27X_Prop 0x1000 273 ARM_PXA27X_Prop = 0x1000,
427#define ARM_v7_Prop 0x2000 274 ARM_v7_Prop = 0x2000,
428 275
429/* ARM2 family */ 276 // ARM2 family
430#define ARM2 (ARM_Fix26_Prop) 277 ARM2 = ARM_Fix26_Prop,
431#define ARM2as ARM2 278 ARM2as = ARM2,
432#define ARM61 ARM2 279 ARM61 = ARM2,
433#define ARM3 ARM2 280 ARM3 = ARM2,
434 281
435#ifdef ARM60 /* previous definition in armopts.h */ 282 // ARM6 family
436#undef ARM60 283 ARM6 = ARM_Lock_Prop,
437#endif 284 ARM60 = ARM6,
438 285 ARM600 = ARM6,
439/* ARM6 family */ 286 ARM610 = ARM6,
440#define ARM6 (ARM_Lock_Prop) 287 ARM620 = ARM6
441#define ARM60 ARM6 288};
442#define ARM600 ARM6
443#define ARM610 ARM6
444#define ARM620 ARM6
445 289
446 290
447/***************************************************************************\ 291/***************************************************************************\
@@ -456,41 +300,44 @@ typedef ARMul_State arm_core_t;
456* The hardware vector addresses * 300* The hardware vector addresses *
457\***************************************************************************/ 301\***************************************************************************/
458 302
459#define ARMResetV 0L 303enum {
460#define ARMUndefinedInstrV 4L 304 ARMResetV = 0,
461#define ARMSWIV 8L 305 ARMUndefinedInstrV = 4,
462#define ARMPrefetchAbortV 12L 306 ARMSWIV = 8,
463#define ARMDataAbortV 16L 307 ARMPrefetchAbortV = 12,
464#define ARMAddrExceptnV 20L 308 ARMDataAbortV = 16,
465#define ARMIRQV 24L 309 ARMAddrExceptnV = 20,
466#define ARMFIQV 28L 310 ARMIRQV = 24,
467#define ARMErrorV 32L /* This is an offset, not an address ! */ 311 ARMFIQV = 28,
468 312 ARMErrorV = 32, // This is an offset, not an address!
469#define ARMul_ResetV ARMResetV 313
470#define ARMul_UndefinedInstrV ARMUndefinedInstrV 314 ARMul_ResetV = ARMResetV,
471#define ARMul_SWIV ARMSWIV 315 ARMul_UndefinedInstrV = ARMUndefinedInstrV,
472#define ARMul_PrefetchAbortV ARMPrefetchAbortV 316 ARMul_SWIV = ARMSWIV,
473#define ARMul_DataAbortV ARMDataAbortV 317 ARMul_PrefetchAbortV = ARMPrefetchAbortV,
474#define ARMul_AddrExceptnV ARMAddrExceptnV 318 ARMul_DataAbortV = ARMDataAbortV,
475#define ARMul_IRQV ARMIRQV 319 ARMul_AddrExceptnV = ARMAddrExceptnV,
476#define ARMul_FIQV ARMFIQV 320 ARMul_IRQV = ARMIRQV,
321 ARMul_FIQV = ARMFIQV
322};
477 323
478/***************************************************************************\ 324/***************************************************************************\
479* Mode and Bank Constants * 325* Mode and Bank Constants *
480\***************************************************************************/ 326\***************************************************************************/
481 327
482#define USER26MODE 0L 328enum {
483#define FIQ26MODE 1L 329 USER26MODE = 0,
484#define IRQ26MODE 2L 330 FIQ26MODE = 1,
485#define SVC26MODE 3L 331 IRQ26MODE = 2,
486#define USER32MODE 16L 332 SVC26MODE = 3,
487#define FIQ32MODE 17L 333 USER32MODE = 16,
488#define IRQ32MODE 18L 334 FIQ32MODE = 17,
489#define SVC32MODE 19L 335 IRQ32MODE = 18,
490#define ABORT32MODE 23L 336 SVC32MODE = 19,
491#define UNDEF32MODE 27L 337 ABORT32MODE = 23,
492//chy 2006-02-15 add system32 mode 338 UNDEF32MODE = 27,
493#define SYSTEM32MODE 31L 339 SYSTEM32MODE = 31
340};
494 341
495#define ARM32BITMODE (state->Mode > 3) 342#define ARM32BITMODE (state->Mode > 3)
496#define ARM26BITMODE (state->Mode <= 3) 343#define ARM26BITMODE (state->Mode <= 3)
@@ -499,14 +346,17 @@ typedef ARMul_State arm_core_t;
499#define ARMul_MODE32BIT ARM32BITMODE 346#define ARMul_MODE32BIT ARM32BITMODE
500#define ARMul_MODE26BIT ARM26BITMODE 347#define ARMul_MODE26BIT ARM26BITMODE
501 348
502#define USERBANK 0 349enum {
503#define FIQBANK 1 350 USERBANK = 0,
504#define IRQBANK 2 351 FIQBANK = 1,
505#define SVCBANK 3 352 IRQBANK = 2,
506#define ABORTBANK 4 353 SVCBANK = 3,
507#define UNDEFBANK 5 354 ABORTBANK = 4,
508#define DUMMYBANK 6 355 UNDEFBANK = 5,
509#define SYSTEMBANK USERBANK 356 DUMMYBANK = 6,
357 SYSTEMBANK = USERBANK
358};
359
510#define BANK_CAN_ACCESS_SPSR(bank) \ 360#define BANK_CAN_ACCESS_SPSR(bank) \
511 ((bank) != USERBANK && (bank) != SYSTEMBANK && (bank) != DUMMYBANK) 361 ((bank) != USERBANK && (bank) != SYSTEMBANK && (bank) != DUMMYBANK)
512 362
@@ -525,13 +375,6 @@ extern void ARMul_Reset(ARMul_State* state);
525extern ARMul_State *ARMul_NewState(ARMul_State* state); 375extern ARMul_State *ARMul_NewState(ARMul_State* state);
526extern ARMword ARMul_DoProg(ARMul_State* state); 376extern ARMword ARMul_DoProg(ARMul_State* state);
527extern ARMword ARMul_DoInstr(ARMul_State* state); 377extern ARMword ARMul_DoInstr(ARMul_State* state);
528/***************************************************************************\
529* Definitons of things for event handling *
530\***************************************************************************/
531
532extern void ARMul_ScheduleEvent(ARMul_State* state, unsigned int delay, unsigned(*func) ());
533extern void ARMul_EnvokeEvent(ARMul_State* state);
534extern unsigned int ARMul_Time(ARMul_State* state);
535 378
536/***************************************************************************\ 379/***************************************************************************\
537* Useful support routines * 380* Useful support routines *
@@ -613,40 +456,44 @@ extern ARMword ARMul_MemAccess(ARMul_State* state, ARMword, ARMword,
613* Definitons of things in the co-processor interface * 456* Definitons of things in the co-processor interface *
614\***************************************************************************/ 457\***************************************************************************/
615 458
616#define ARMul_FIRST 0 459enum {
617#define ARMul_TRANSFER 1 460 ARMul_FIRST = 0,
618#define ARMul_BUSY 2 461 ARMul_TRANSFER = 1,
619#define ARMul_DATA 3 462 ARMul_BUSY = 2,
620#define ARMul_INTERRUPT 4 463 ARMul_DATA = 3,
621#define ARMul_DONE 0 464 ARMul_INTERRUPT = 4,
622#define ARMul_CANT 1 465 ARMul_DONE = 0,
623#define ARMul_INC 3 466 ARMul_CANT = 1,
624 467 ARMul_INC = 3
625#define ARMul_CP13_R0_FIQ 0x1 468};
626#define ARMul_CP13_R0_IRQ 0x2 469
627#define ARMul_CP13_R8_PMUS 0x1 470enum {
628 471 ARMul_CP13_R0_FIQ = 0x1,
629#define ARMul_CP14_R0_ENABLE 0x0001 472 ARMul_CP13_R0_IRQ = 0x2,
630#define ARMul_CP14_R0_CLKRST 0x0004 473 ARMul_CP13_R8_PMUS = 0x1,
631#define ARMul_CP14_R0_CCD 0x0008 474
632#define ARMul_CP14_R0_INTEN0 0x0010 475 ARMul_CP14_R0_ENABLE = 0x0001,
633#define ARMul_CP14_R0_INTEN1 0x0020 476 ARMul_CP14_R0_CLKRST = 0x0004,
634#define ARMul_CP14_R0_INTEN2 0x0040 477 ARMul_CP14_R0_CCD = 0x0008,
635#define ARMul_CP14_R0_FLAG0 0x0100 478 ARMul_CP14_R0_INTEN0 = 0x0010,
636#define ARMul_CP14_R0_FLAG1 0x0200 479 ARMul_CP14_R0_INTEN1 = 0x0020,
637#define ARMul_CP14_R0_FLAG2 0x0400 480 ARMul_CP14_R0_INTEN2 = 0x0040,
638#define ARMul_CP14_R10_MOE_IB 0x0004 481 ARMul_CP14_R0_FLAG0 = 0x0100,
639#define ARMul_CP14_R10_MOE_DB 0x0008 482 ARMul_CP14_R0_FLAG1 = 0x0200,
640#define ARMul_CP14_R10_MOE_BT 0x000c 483 ARMul_CP14_R0_FLAG2 = 0x0400,
641#define ARMul_CP15_R1_ENDIAN 0x0080 484 ARMul_CP14_R10_MOE_IB = 0x0004,
642#define ARMul_CP15_R1_ALIGN 0x0002 485 ARMul_CP14_R10_MOE_DB = 0x0008,
643#define ARMul_CP15_R5_X 0x0400 486 ARMul_CP14_R10_MOE_BT = 0x000c,
644#define ARMul_CP15_R5_ST_ALIGN 0x0001 487 ARMul_CP15_R1_ENDIAN = 0x0080,
645#define ARMul_CP15_R5_IMPRE 0x0406 488 ARMul_CP15_R1_ALIGN = 0x0002,
646#define ARMul_CP15_R5_MMU_EXCPT 0x0400 489 ARMul_CP15_R5_X = 0x0400,
647#define ARMul_CP15_DBCON_M 0x0100 490 ARMul_CP15_R5_ST_ALIGN = 0x0001,
648#define ARMul_CP15_DBCON_E1 0x000c 491 ARMul_CP15_R5_IMPRE = 0x0406,
649#define ARMul_CP15_DBCON_E0 0x0003 492 ARMul_CP15_R5_MMU_EXCPT = 0x0400,
493 ARMul_CP15_DBCON_M = 0x0100,
494 ARMul_CP15_DBCON_E1 = 0x000c,
495 ARMul_CP15_DBCON_E0 = 0x0003
496};
650 497
651extern unsigned ARMul_CoProInit(ARMul_State* state); 498extern unsigned ARMul_CoProInit(ARMul_State* state);
652extern void ARMul_CoProExit(ARMul_State* state); 499extern void ARMul_CoProExit(ARMul_State* state);
@@ -675,12 +522,9 @@ extern unsigned ARMul_OSHandleSWI(ARMul_State* state, ARMword number);
675} 522}
676#endif 523#endif
677 524
678
679extern ARMword ARMul_OSLastErrorP(ARMul_State* state); 525extern ARMword ARMul_OSLastErrorP(ARMul_State* state);
680
681extern ARMword ARMul_Debug(ARMul_State* state, ARMword pc, ARMword instr); 526extern ARMword ARMul_Debug(ARMul_State* state, ARMword pc, ARMword instr);
682extern unsigned ARMul_OSException(ARMul_State* state, ARMword vector, ARMword pc); 527extern unsigned ARMul_OSException(ARMul_State* state, ARMword vector, ARMword pc);
683extern int rdi_log;
684 528
685enum ConditionCode { 529enum ConditionCode {
686 EQ = 0, 530 EQ = 0,
@@ -729,70 +573,12 @@ enum ConditionCode {
729#define IFFLAGS state->IFFlags 573#define IFFLAGS state->IFFlags
730#endif //VFLAG 574#endif //VFLAG
731 575
732#define FLAG_MASK 0xf0000000
733#define NBIT_SHIFT 31
734#define ZBIT_SHIFT 30
735#define CBIT_SHIFT 29
736#define VBIT_SHIFT 28
737
738#define SKYEYE_OUTREGS(fd) { fprintf ((fd), "R %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,C %x,S %x,%x,%x,%x,%x,%x,%x,M %x,B %x,E %x,I %x,P %x,T %x,L %x,D %x,",\
739 state->Reg[0],state->Reg[1],state->Reg[2],state->Reg[3], \
740 state->Reg[4],state->Reg[5],state->Reg[6],state->Reg[7], \
741 state->Reg[8],state->Reg[9],state->Reg[10],state->Reg[11], \
742 state->Reg[12],state->Reg[13],state->Reg[14],state->Reg[15], \
743 state->Cpsr, state->Spsr[0], state->Spsr[1], state->Spsr[2],\
744 state->Spsr[3],state->Spsr[4], state->Spsr[5], state->Spsr[6],\
745 state->Mode,state->Bank,state->ErrorCode,state->instr,state->pc,\
746 state->temp,state->loaded,state->decoded);}
747
748#define SKYEYE_OUTMOREREGS(fd) { fprintf ((fd),"\
749RUs %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,\
750RF %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,\
751RI %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,\
752RS %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,\
753RA %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,\
754RUn %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x\n",\
755 state->RegBank[0][0],state->RegBank[0][1],state->RegBank[0][2],state->RegBank[0][3], \
756 state->RegBank[0][4],state->RegBank[0][5],state->RegBank[0][6],state->RegBank[0][7], \
757 state->RegBank[0][8],state->RegBank[0][9],state->RegBank[0][10],state->RegBank[0][11], \
758 state->RegBank[0][12],state->RegBank[0][13],state->RegBank[0][14],state->RegBank[0][15], \
759 state->RegBank[1][0],state->RegBank[1][1],state->RegBank[1][2],state->RegBank[1][3], \
760 state->RegBank[1][4],state->RegBank[1][5],state->RegBank[1][6],state->RegBank[1][7], \
761 state->RegBank[1][8],state->RegBank[1][9],state->RegBank[1][10],state->RegBank[1][11], \
762 state->RegBank[1][12],state->RegBank[1][13],state->RegBank[1][14],state->RegBank[1][15], \
763 state->RegBank[2][0],state->RegBank[2][1],state->RegBank[2][2],state->RegBank[2][3], \
764 state->RegBank[2][4],state->RegBank[2][5],state->RegBank[2][6],state->RegBank[2][7], \
765 state->RegBank[2][8],state->RegBank[2][9],state->RegBank[2][10],state->RegBank[2][11], \
766 state->RegBank[2][12],state->RegBank[2][13],state->RegBank[2][14],state->RegBank[2][15], \
767 state->RegBank[3][0],state->RegBank[3][1],state->RegBank[3][2],state->RegBank[3][3], \
768 state->RegBank[3][4],state->RegBank[3][5],state->RegBank[3][6],state->RegBank[3][7], \
769 state->RegBank[3][8],state->RegBank[3][9],state->RegBank[3][10],state->RegBank[3][11], \
770 state->RegBank[3][12],state->RegBank[3][13],state->RegBank[3][14],state->RegBank[3][15], \
771 state->RegBank[4][0],state->RegBank[4][1],state->RegBank[4][2],state->RegBank[4][3], \
772 state->RegBank[4][4],state->RegBank[4][5],state->RegBank[4][6],state->RegBank[4][7], \
773 state->RegBank[4][8],state->RegBank[4][9],state->RegBank[4][10],state->RegBank[4][11], \
774 state->RegBank[4][12],state->RegBank[4][13],state->RegBank[4][14],state->RegBank[4][15], \
775 state->RegBank[5][0],state->RegBank[5][1],state->RegBank[5][2],state->RegBank[5][3], \
776 state->RegBank[5][4],state->RegBank[5][5],state->RegBank[5][6],state->RegBank[5][7], \
777 state->RegBank[5][8],state->RegBank[5][9],state->RegBank[5][10],state->RegBank[5][11], \
778 state->RegBank[5][12],state->RegBank[5][13],state->RegBank[5][14],state->RegBank[5][15] \
779 );}
780
781
782#define SA1110 0x6901b110
783#define SA1100 0x4401a100
784#define PXA250 0x69052100
785#define PXA270 0x69054110
786//#define PXA250 0x69052903
787// 0x69052903; //PXA250 B1 from intel 278522-001.pdf
788
789extern bool AddOverflow(ARMword, ARMword, ARMword); 576extern bool AddOverflow(ARMword, ARMword, ARMword);
790extern bool SubOverflow(ARMword, ARMword, ARMword); 577extern bool SubOverflow(ARMword, ARMword, ARMword);
791 578
792extern void ARMul_UndefInstr(ARMul_State*, ARMword); 579extern void ARMul_UndefInstr(ARMul_State*, ARMword);
793extern void ARMul_FixCPSR(ARMul_State*, ARMword, ARMword); 580extern void ARMul_FixCPSR(ARMul_State*, ARMword, ARMword);
794extern void ARMul_FixSPSR(ARMul_State*, ARMword, ARMword); 581extern void ARMul_FixSPSR(ARMul_State*, ARMword, ARMword);
795extern void ARMul_ConsolePrint(ARMul_State*, const char*, ...);
796extern void ARMul_SelectProcessor(ARMul_State*, unsigned); 582extern void ARMul_SelectProcessor(ARMul_State*, unsigned);
797 583
798extern u32 AddWithCarry(u32, u32, u32, bool*, bool*); 584extern u32 AddWithCarry(u32, u32, u32, bool*, bool*);
@@ -810,8 +596,3 @@ extern u16 ARMul_UnsignedSaturatedSub16(u16, u16);
810extern u8 ARMul_UnsignedAbsoluteDifference(u8, u8); 596extern u8 ARMul_UnsignedAbsoluteDifference(u8, u8);
811extern u32 ARMul_SignedSatQ(s32, u8, bool*); 597extern u32 ARMul_SignedSatQ(s32, u8, bool*);
812extern u32 ARMul_UnsignedSatQ(s32, u8, bool*); 598extern u32 ARMul_UnsignedSatQ(s32, u8, bool*);
813
814#define DIFF_LOG 0
815#define SAVE_LOG 0
816
817#endif /* _ARMDEFS_H_ */
diff --git a/src/core/arm/skyeye_common/armemu.h b/src/core/arm/skyeye_common/armemu.h
index 1dfcc635a..686b2a3f6 100644
--- a/src/core/arm/skyeye_common/armemu.h
+++ b/src/core/arm/skyeye_common/armemu.h
@@ -575,8 +575,6 @@ extern ARMword ARMul_GetPC (ARMul_State *);
575extern ARMword ARMul_GetNextPC (ARMul_State *); 575extern ARMword ARMul_GetNextPC (ARMul_State *);
576extern ARMword ARMul_GetR15 (ARMul_State *); 576extern ARMword ARMul_GetR15 (ARMul_State *);
577extern ARMword ARMul_GetCPSR (ARMul_State *); 577extern ARMword ARMul_GetCPSR (ARMul_State *);
578extern void ARMul_EnvokeEvent (ARMul_State *);
579extern unsigned int ARMul_Time (ARMul_State *);
580extern void ARMul_NegZero (ARMul_State *, ARMword); 578extern void ARMul_NegZero (ARMul_State *, ARMword);
581extern void ARMul_SetPC (ARMul_State *, ARMword); 579extern void ARMul_SetPC (ARMul_State *, ARMword);
582extern void ARMul_SetR15 (ARMul_State *, ARMword); 580extern void ARMul_SetR15 (ARMul_State *, ARMword);
@@ -603,8 +601,7 @@ extern void ARMul_AddCarry (ARMul_State *, ARMword, ARMword, ARMword);
603extern tdstate ARMul_ThumbDecode (ARMul_State *, ARMword, ARMword, ARMword *); 601extern tdstate ARMul_ThumbDecode (ARMul_State *, ARMword, ARMword, ARMword *);
604extern ARMword ARMul_GetReg (ARMul_State *, unsigned, unsigned); 602extern ARMword ARMul_GetReg (ARMul_State *, unsigned, unsigned);
605extern void ARMul_SetReg (ARMul_State *, unsigned, unsigned, ARMword); 603extern void ARMul_SetReg (ARMul_State *, unsigned, unsigned, ARMword);
606extern void ARMul_ScheduleEvent (ARMul_State *, unsigned int, 604
607 unsigned (*)(ARMul_State *));
608/* Coprocessor support functions. */ 605/* Coprocessor support functions. */
609extern unsigned ARMul_CoProInit (ARMul_State *); 606extern unsigned ARMul_CoProInit (ARMul_State *);
610extern void ARMul_CoProExit (ARMul_State *); 607extern void ARMul_CoProExit (ARMul_State *);
diff --git a/src/core/arm/skyeye_common/skyeye_defs.h b/src/core/arm/skyeye_common/skyeye_defs.h
index d4088383f..6648e9d66 100644
--- a/src/core/arm/skyeye_common/skyeye_defs.h
+++ b/src/core/arm/skyeye_common/skyeye_defs.h
@@ -1,5 +1,4 @@
1#ifndef CORE_ARM_SKYEYE_DEFS_H_ 1#pragma once
2#define CORE_ARM_SKYEYE_DEFS_H_
3 2
4#include "common/common.h" 3#include "common/common.h"
5 4
@@ -8,21 +7,15 @@
8 7
9typedef struct 8typedef struct
10{ 9{
11 const char *cpu_arch_name; /*cpu architecture version name.e.g. armv4t */ 10 const char *cpu_arch_name; /* CPU architecture version name.e.g. armv4t */
12 const char *cpu_name; /*cpu name. e.g. arm7tdmi or arm720t */ 11 const char *cpu_name; /* CPU name. e.g. arm7tdmi or arm720t */
13 u32 cpu_val; /*CPU value; also call MMU ID or processor id;see 12 u32 cpu_val; /*CPU value; also call MMU ID or processor id;see
14 ARM Architecture Reference Manual B2-6 */ 13 ARM Architecture Reference Manual B2-6 */
15 u32 cpu_mask; /*cpu_val's mask. */ 14 u32 cpu_mask; /* cpu_val's mask. */
16 u32 cachetype; /*this cpu has what kind of cache */ 15 u32 cachetype; /* this CPU has what kind of cache */
17} cpu_config_t; 16} cpu_config_t;
18 17
19typedef struct conf_object_s{ 18typedef enum {
20 char* objname;
21 void* obj;
22 char* class_name;
23}conf_object_t;
24
25typedef enum{
26 /* No exception */ 19 /* No exception */
27 No_exp = 0, 20 No_exp = 0,
28 /* Memory allocation exception */ 21 /* Memory allocation exception */
@@ -44,70 +37,21 @@ typedef enum{
44 37
45 /* Unknown exception */ 38 /* Unknown exception */
46 Unknown_exp 39 Unknown_exp
47}exception_t; 40} exception_t;
48 41
49typedef enum { 42typedef enum {
50 Align = 0, 43 Align = 0,
51 UnAlign 44 UnAlign
52}align_t; 45} align_t;
53 46
54typedef enum { 47typedef enum {
55 Little_endian = 0, 48 Little_endian = 0,
56 Big_endian 49 Big_endian
57}endian_t; 50} endian_t;
58//typedef int exception_t;
59 51
60typedef enum{ 52typedef enum {
61 Phys_addr = 0, 53 Phys_addr = 0,
62 Virt_addr 54 Virt_addr
63}addr_type_t; 55} addr_type_t;
64
65typedef exception_t(*read_byte_t)(conf_object_t* target, u32 addr, void *buf, size_t count);
66typedef exception_t(*write_byte_t)(conf_object_t* target, u32 addr, const void *buf, size_t count);
67
68typedef struct memory_space{
69 conf_object_t* conf_obj;
70 read_byte_t read;
71 write_byte_t write;
72}memory_space_intf;
73
74
75/*
76 * a running instance for a specific archteciture.
77 */
78typedef struct generic_arch_s
79{
80 char* arch_name;
81 void (*init) (void);
82 void (*reset) (void);
83 void (*step_once) (void);
84 void (*set_pc)(u32 addr);
85 u32 (*get_pc)(void);
86 u32 (*get_step)(void);
87 //chy 2004-04-15
88 //int (*ICE_write_byte) (u32 addr, uint8_t v);
89 //int (*ICE_read_byte)(u32 addr, uint8_t *pv);
90 u32 (*get_regval_by_id)(int id);
91 u32 (*get_regnum)(void);
92 char* (*get_regname_by_id)(int id);
93 exception_t (*set_regval_by_id)(int id, u32 value);
94 /*
95 * read a data by virtual address.
96 */
97 exception_t (*mmu_read)(short size, u32 addr, u32 * value);
98 /*
99 * write a data by a virtual address.
100 */
101 exception_t (*mmu_write)(short size, u32 addr, u32 value);
102 /**
103 * get a signal from external
104 */
105 //exception_t (*signal)(interrupt_signal_t* signal);
106
107 endian_t endianess;
108 align_t alignment;
109} generic_arch_t;
110 56
111typedef u32 addr_t; 57typedef u32 addr_t;
112
113#endif
HIC SVNT DRACONES