diff options
| -rw-r--r-- | src/core/hle/service/nvdrv/devices/nvhost_gpu.cpp | 1 | ||||
| -rw-r--r-- | src/video_core/dma_pusher.cpp | 26 | ||||
| -rw-r--r-- | src/video_core/dma_pusher.h | 3 |
3 files changed, 1 insertions, 29 deletions
diff --git a/src/core/hle/service/nvdrv/devices/nvhost_gpu.cpp b/src/core/hle/service/nvdrv/devices/nvhost_gpu.cpp index 152019548..b1d9d55b5 100644 --- a/src/core/hle/service/nvdrv/devices/nvhost_gpu.cpp +++ b/src/core/hle/service/nvdrv/devices/nvhost_gpu.cpp | |||
| @@ -214,7 +214,6 @@ u32 nvhost_gpu::SubmitGPFIFOImpl(IoctlSubmitGpfifo& params, std::vector<u8>& out | |||
| 214 | params.fence_out.value = syncpoint_manager.GetSyncpointMax(params.fence_out.id); | 214 | params.fence_out.value = syncpoint_manager.GetSyncpointMax(params.fence_out.id); |
| 215 | } | 215 | } |
| 216 | 216 | ||
| 217 | entries.RefreshIntegrityChecks(gpu); | ||
| 218 | gpu.PushGPUEntries(std::move(entries)); | 217 | gpu.PushGPUEntries(std::move(entries)); |
| 219 | 218 | ||
| 220 | if (params.flags.add_increment.Value()) { | 219 | if (params.flags.add_increment.Value()) { |
diff --git a/src/video_core/dma_pusher.cpp b/src/video_core/dma_pusher.cpp index 105b85a92..d8801b1f5 100644 --- a/src/video_core/dma_pusher.cpp +++ b/src/video_core/dma_pusher.cpp | |||
| @@ -13,20 +13,6 @@ | |||
| 13 | 13 | ||
| 14 | namespace Tegra { | 14 | namespace Tegra { |
| 15 | 15 | ||
| 16 | void CommandList::RefreshIntegrityChecks(GPU& gpu) { | ||
| 17 | command_list_hashes.resize(command_lists.size()); | ||
| 18 | |||
| 19 | for (std::size_t index = 0; index < command_lists.size(); ++index) { | ||
| 20 | const CommandListHeader command_list_header = command_lists[index]; | ||
| 21 | std::vector<CommandHeader> command_headers(command_list_header.size); | ||
| 22 | gpu.MemoryManager().ReadBlockUnsafe(command_list_header.addr, command_headers.data(), | ||
| 23 | command_list_header.size * sizeof(u32)); | ||
| 24 | command_list_hashes[index] = | ||
| 25 | Common::CityHash64(reinterpret_cast<char*>(command_headers.data()), | ||
| 26 | command_list_header.size * sizeof(u32)); | ||
| 27 | } | ||
| 28 | } | ||
| 29 | |||
| 30 | DmaPusher::DmaPusher(Core::System& system, GPU& gpu) : gpu{gpu}, system{system} {} | 16 | DmaPusher::DmaPusher(Core::System& system, GPU& gpu) : gpu{gpu}, system{system} {} |
| 31 | 17 | ||
| 32 | DmaPusher::~DmaPusher() = default; | 18 | DmaPusher::~DmaPusher() = default; |
| @@ -77,8 +63,7 @@ bool DmaPusher::Step() { | |||
| 77 | dma_pushbuffer.pop(); | 63 | dma_pushbuffer.pop(); |
| 78 | } else { | 64 | } else { |
| 79 | const CommandListHeader command_list_header{ | 65 | const CommandListHeader command_list_header{ |
| 80 | command_list.command_lists[dma_pushbuffer_subindex]}; | 66 | command_list.command_lists[dma_pushbuffer_subindex++]}; |
| 81 | const u64 next_hash = command_list.command_list_hashes[dma_pushbuffer_subindex++]; | ||
| 82 | const GPUVAddr dma_get = command_list_header.addr; | 67 | const GPUVAddr dma_get = command_list_header.addr; |
| 83 | 68 | ||
| 84 | if (dma_pushbuffer_subindex >= command_list.command_lists.size()) { | 69 | if (dma_pushbuffer_subindex >= command_list.command_lists.size()) { |
| @@ -95,15 +80,6 @@ bool DmaPusher::Step() { | |||
| 95 | command_headers.resize(command_list_header.size); | 80 | command_headers.resize(command_list_header.size); |
| 96 | gpu.MemoryManager().ReadBlockUnsafe(dma_get, command_headers.data(), | 81 | gpu.MemoryManager().ReadBlockUnsafe(dma_get, command_headers.data(), |
| 97 | command_list_header.size * sizeof(u32)); | 82 | command_list_header.size * sizeof(u32)); |
| 98 | |||
| 99 | // Integrity check | ||
| 100 | const u64 new_hash = Common::CityHash64(reinterpret_cast<char*>(command_headers.data()), | ||
| 101 | command_list_header.size * sizeof(u32)); | ||
| 102 | if (new_hash != next_hash) { | ||
| 103 | LOG_CRITICAL(HW_GPU, "CommandList at addr=0x{:X} is corrupt, skipping!", dma_get); | ||
| 104 | dma_pushbuffer.pop(); | ||
| 105 | return true; | ||
| 106 | } | ||
| 107 | } | 83 | } |
| 108 | for (std::size_t index = 0; index < command_headers.size();) { | 84 | for (std::size_t index = 0; index < command_headers.size();) { |
| 109 | const CommandHeader& command_header = command_headers[index]; | 85 | const CommandHeader& command_header = command_headers[index]; |
diff --git a/src/video_core/dma_pusher.h b/src/video_core/dma_pusher.h index 9d9a750d9..96ac267f7 100644 --- a/src/video_core/dma_pusher.h +++ b/src/video_core/dma_pusher.h | |||
| @@ -90,10 +90,7 @@ struct CommandList final { | |||
| 90 | explicit CommandList(std::vector<Tegra::CommandHeader>&& prefetch_command_list) | 90 | explicit CommandList(std::vector<Tegra::CommandHeader>&& prefetch_command_list) |
| 91 | : prefetch_command_list{std::move(prefetch_command_list)} {} | 91 | : prefetch_command_list{std::move(prefetch_command_list)} {} |
| 92 | 92 | ||
| 93 | void RefreshIntegrityChecks(GPU& gpu); | ||
| 94 | |||
| 95 | std::vector<Tegra::CommandListHeader> command_lists; | 93 | std::vector<Tegra::CommandListHeader> command_lists; |
| 96 | std::vector<u64> command_list_hashes; | ||
| 97 | std::vector<Tegra::CommandHeader> prefetch_command_list; | 94 | std::vector<Tegra::CommandHeader> prefetch_command_list; |
| 98 | }; | 95 | }; |
| 99 | 96 | ||