diff options
| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom_interpreter.cpp | 15 | ||||
| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom_trans.inc | 43 |
2 files changed, 19 insertions, 39 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp index acf66b350..7f6cf6e29 100644 --- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp +++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp | |||
| @@ -753,6 +753,21 @@ static get_addr_fp_t GetAddressingOp(unsigned int inst) { | |||
| 753 | return nullptr; | 753 | return nullptr; |
| 754 | } | 754 | } |
| 755 | 755 | ||
| 756 | // Specialized for LDRT, LDRBT, STRT, and STRBT, which have specific addressing mode requirements | ||
| 757 | get_addr_fp_t GetAddressingOpLoadStoreT(unsigned int inst) { | ||
| 758 | if (BITS(inst, 25, 27) == 2) { | ||
| 759 | return LnSWoUB(ImmediatePostIndexed); | ||
| 760 | } else if (BITS(inst, 25, 27) == 3) { | ||
| 761 | return LnSWoUB(ScaledRegisterPostIndexed); | ||
| 762 | } | ||
| 763 | // Reaching this would indicate the thumb version | ||
| 764 | // of this instruction, however the 3DS CPU doesn't | ||
| 765 | // support this variant (the 3DS CPU is only ARMv6K, | ||
| 766 | // while this variant is added in ARMv6T2). | ||
| 767 | // So it's sufficient for citra to not implement this. | ||
| 768 | return nullptr; | ||
| 769 | } | ||
| 770 | |||
| 756 | typedef ARM_INST_PTR (*transop_fp_t)(unsigned int, int); | 771 | typedef ARM_INST_PTR (*transop_fp_t)(unsigned int, int); |
| 757 | 772 | ||
| 758 | #include "arm_dyncom_trans.inc" | 773 | #include "arm_dyncom_trans.inc" |
diff --git a/src/core/arm/dyncom/arm_dyncom_trans.inc b/src/core/arm/dyncom/arm_dyncom_trans.inc index 70a585939..48c6f81e7 100644 --- a/src/core/arm/dyncom/arm_dyncom_trans.inc +++ b/src/core/arm/dyncom/arm_dyncom_trans.inc | |||
| @@ -420,13 +420,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrbt)(unsigned int inst, int index) | |||
| 420 | inst_base->br = TransExtData::NON_BRANCH; | 420 | inst_base->br = TransExtData::NON_BRANCH; |
| 421 | 421 | ||
| 422 | inst_cream->inst = inst; | 422 | inst_cream->inst = inst; |
| 423 | if (BITS(inst, 25, 27) == 2) { | 423 | inst_cream->get_addr = GetAddressingOpLoadStoreT(inst); |
| 424 | inst_cream->get_addr = LnSWoUB(ImmediatePostIndexed); | ||
| 425 | } else if (BITS(inst, 25, 27) == 3) { | ||
| 426 | inst_cream->get_addr = LnSWoUB(ScaledRegisterPostIndexed); | ||
| 427 | } else { | ||
| 428 | DEBUG_MSG; | ||
| 429 | } | ||
| 430 | 424 | ||
| 431 | return inst_base; | 425 | return inst_base; |
| 432 | } | 426 | } |
| @@ -522,18 +516,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrt)(unsigned int inst, int index) | |||
| 522 | inst_base->br = TransExtData::NON_BRANCH; | 516 | inst_base->br = TransExtData::NON_BRANCH; |
| 523 | 517 | ||
| 524 | inst_cream->inst = inst; | 518 | inst_cream->inst = inst; |
| 525 | if (BITS(inst, 25, 27) == 2) { | 519 | inst_cream->get_addr = GetAddressingOpLoadStoreT(inst); |
| 526 | inst_cream->get_addr = LnSWoUB(ImmediatePostIndexed); | ||
| 527 | } else if (BITS(inst, 25, 27) == 3) { | ||
| 528 | inst_cream->get_addr = LnSWoUB(ScaledRegisterPostIndexed); | ||
| 529 | } else { | ||
| 530 | // Reaching this would indicate the thumb version | ||
| 531 | // of this instruction, however the 3DS CPU doesn't | ||
| 532 | // support this variant (the 3DS CPU is only ARMv6K, | ||
| 533 | // while this variant is added in ARMv6T2). | ||
| 534 | // So it's sufficient for citra to not implement this. | ||
| 535 | DEBUG_MSG; | ||
| 536 | } | ||
| 537 | 520 | ||
| 538 | if (BITS(inst, 12, 15) == 15) { | 521 | if (BITS(inst, 12, 15) == 15) { |
| 539 | inst_base->br = TransExtData::INDIRECT_BRANCH; | 522 | inst_base->br = TransExtData::INDIRECT_BRANCH; |
| @@ -1424,14 +1407,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(strbt)(unsigned int inst, int index) | |||
| 1424 | inst_base->br = TransExtData::NON_BRANCH; | 1407 | inst_base->br = TransExtData::NON_BRANCH; |
| 1425 | 1408 | ||
| 1426 | inst_cream->inst = inst; | 1409 | inst_cream->inst = inst; |
| 1427 | 1410 | inst_cream->get_addr = GetAddressingOpLoadStoreT(inst); | |
| 1428 | if (BITS(inst, 25, 27) == 2) { | ||
| 1429 | inst_cream->get_addr = LnSWoUB(ImmediatePostIndexed); | ||
| 1430 | } else if (BITS(inst, 25, 27) == 3) { | ||
| 1431 | inst_cream->get_addr = LnSWoUB(ScaledRegisterPostIndexed); | ||
| 1432 | } else { | ||
| 1433 | DEBUG_MSG; | ||
| 1434 | } | ||
| 1435 | 1411 | ||
| 1436 | return inst_base; | 1412 | return inst_base; |
| 1437 | } | 1413 | } |
| @@ -1499,18 +1475,7 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(strt)(unsigned int inst, int index) | |||
| 1499 | inst_base->br = TransExtData::NON_BRANCH; | 1475 | inst_base->br = TransExtData::NON_BRANCH; |
| 1500 | 1476 | ||
| 1501 | inst_cream->inst = inst; | 1477 | inst_cream->inst = inst; |
| 1502 | if (BITS(inst, 25, 27) == 2) { | 1478 | inst_cream->get_addr = GetAddressingOpLoadStoreT(inst); |
| 1503 | inst_cream->get_addr = LnSWoUB(ImmediatePostIndexed); | ||
| 1504 | } else if (BITS(inst, 25, 27) == 3) { | ||
| 1505 | inst_cream->get_addr = LnSWoUB(ScaledRegisterPostIndexed); | ||
| 1506 | } else { | ||
| 1507 | // Reaching this would indicate the thumb version | ||
| 1508 | // of this instruction, however the 3DS CPU doesn't | ||
| 1509 | // support this variant (the 3DS CPU is only ARMv6K, | ||
| 1510 | // while this variant is added in ARMv6T2). | ||
| 1511 | // So it's sufficient for citra to not implement this. | ||
| 1512 | DEBUG_MSG; | ||
| 1513 | } | ||
| 1514 | 1479 | ||
| 1515 | return inst_base; | 1480 | return inst_base; |
| 1516 | } | 1481 | } |