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-rw-r--r--src/assets/citra.icobin0 -> 509287 bytes
-rw-r--r--src/citra/CMakeLists.txt6
-rw-r--r--src/citra/citra.rcbin3146 -> 566 bytes
-rw-r--r--src/citra_qt/CMakeLists.txt1
-rw-r--r--src/citra_qt/citra-qt.rcbin0 -> 566 bytes
-rw-r--r--src/common/common.h4
-rw-r--r--src/common/common_funcs.h8
-rw-r--r--src/common/log.h12
-rw-r--r--src/common/msg_handler.h2
-rw-r--r--src/common/platform.h4
-rw-r--r--src/common/string_util.cpp6
-rw-r--r--src/common/thread.cpp23
-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp697
-rw-r--r--src/core/arm/skyeye_common/vfp/vfpdouble.cpp2
-rw-r--r--src/core/arm/skyeye_common/vfp/vfpinstr.cpp170
-rw-r--r--src/core/arm/skyeye_common/vfp/vfpsingle.cpp2
16 files changed, 267 insertions, 670 deletions
diff --git a/src/assets/citra.ico b/src/assets/citra.ico
new file mode 100644
index 000000000..4fef651e2
--- /dev/null
+++ b/src/assets/citra.ico
Binary files differ
diff --git a/src/citra/CMakeLists.txt b/src/citra/CMakeLists.txt
index b06259f5e..94f8d13c7 100644
--- a/src/citra/CMakeLists.txt
+++ b/src/citra/CMakeLists.txt
@@ -2,6 +2,7 @@ set(SRCS
2 emu_window/emu_window_glfw.cpp 2 emu_window/emu_window_glfw.cpp
3 citra.cpp 3 citra.cpp
4 config.cpp 4 config.cpp
5 citra.rc
5 ) 6 )
6set(HEADERS 7set(HEADERS
7 emu_window/emu_window_glfw.h 8 emu_window/emu_window_glfw.h
@@ -14,7 +15,7 @@ create_directory_groups(${SRCS} ${HEADERS})
14 15
15add_executable(citra ${SRCS} ${HEADERS}) 16add_executable(citra ${SRCS} ${HEADERS})
16target_link_libraries(citra core common video_core) 17target_link_libraries(citra core common video_core)
17target_link_libraries(citra ${OPENGL_gl_LIBRARY} ${GLFW_LIBRARIES} inih) 18target_link_libraries(citra ${GLFW_LIBRARIES} ${OPENGL_gl_LIBRARY} inih)
18 19
19if (UNIX) 20if (UNIX)
20 target_link_libraries(citra -pthread) 21 target_link_libraries(citra -pthread)
@@ -24,6 +25,9 @@ if (APPLE)
24 target_link_libraries(citra iconv ${COREFOUNDATION_LIBRARY}) 25 target_link_libraries(citra iconv ${COREFOUNDATION_LIBRARY})
25elseif (WIN32) 26elseif (WIN32)
26 target_link_libraries(citra winmm) 27 target_link_libraries(citra winmm)
28 if (MINGW) # GCC does not support codecvt, so use iconv instead
29 target_link_libraries(citra iconv)
30 endif()
27else() # Unix 31else() # Unix
28 target_link_libraries(citra rt) 32 target_link_libraries(citra rt)
29endif() 33endif()
diff --git a/src/citra/citra.rc b/src/citra/citra.rc
index c04acc7ff..c28e7dbe5 100644
--- a/src/citra/citra.rc
+++ b/src/citra/citra.rc
Binary files differ
diff --git a/src/citra_qt/CMakeLists.txt b/src/citra_qt/CMakeLists.txt
index 54d0a1271..356ec754f 100644
--- a/src/citra_qt/CMakeLists.txt
+++ b/src/citra_qt/CMakeLists.txt
@@ -17,6 +17,7 @@ set(SRCS
17 bootmanager.cpp 17 bootmanager.cpp
18 hotkeys.cpp 18 hotkeys.cpp
19 main.cpp 19 main.cpp
20 citra-qt.rc
20 ) 21 )
21 22
22set(HEADERS 23set(HEADERS
diff --git a/src/citra_qt/citra-qt.rc b/src/citra_qt/citra-qt.rc
new file mode 100644
index 000000000..dd6f834f5
--- /dev/null
+++ b/src/citra_qt/citra-qt.rc
Binary files differ
diff --git a/src/common/common.h b/src/common/common.h
index 66f0ccd0c..ba33373ae 100644
--- a/src/common/common.h
+++ b/src/common/common.h
@@ -50,11 +50,13 @@ private:
50#elif defined _WIN32 50#elif defined _WIN32
51 51
52// Check MSC ver 52// Check MSC ver
53 #if !defined _MSC_VER || _MSC_VER <= 1000 53 #if defined _MSC_VER && _MSC_VER <= 1000
54 #error needs at least version 1000 of MSC 54 #error needs at least version 1000 of MSC
55 #endif 55 #endif
56 56
57 #ifndef NOMINMAX
57 #define NOMINMAX 58 #define NOMINMAX
59 #endif
58 60
59// Memory leak checks 61// Memory leak checks
60 #define CHECK_HEAP_INTEGRITY() 62 #define CHECK_HEAP_INTEGRITY()
diff --git a/src/common/common_funcs.h b/src/common/common_funcs.h
index ca7abbea6..c2750a63c 100644
--- a/src/common/common_funcs.h
+++ b/src/common/common_funcs.h
@@ -31,7 +31,7 @@ template<> struct CompileTimeAssert<true> {};
31 31
32#define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0])) 32#define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0]))
33 33
34#ifndef _WIN32 34#ifndef _MSC_VER
35 35
36#include <errno.h> 36#include <errno.h>
37#ifdef __linux__ 37#ifdef __linux__
@@ -75,7 +75,7 @@ inline u64 _rotr64(u64 x, unsigned int shift){
75 return (x >> n) | (x << (64 - n)); 75 return (x >> n) | (x << (64 - n));
76} 76}
77 77
78#else // WIN32 78#else // _MSC_VER
79#include <locale.h> 79#include <locale.h>
80 80
81// Function Cross-Compatibility 81// Function Cross-Compatibility
@@ -140,7 +140,7 @@ extern "C" {
140} 140}
141 #define Crash() {DebugBreak();} 141 #define Crash() {DebugBreak();}
142 #endif // M_IX86 142 #endif // M_IX86
143#endif // WIN32 ndef 143#endif // _MSC_VER ndef
144 144
145// Dolphin's min and max functions 145// Dolphin's min and max functions
146#undef min 146#undef min
@@ -168,7 +168,7 @@ inline u32 swap24(const u8* _data) {return (_data[0] << 16) | (_data[1] << 8) |
168#undef swap64 168#undef swap64
169#endif 169#endif
170 170
171#ifdef _WIN32 171#ifdef _MSC_VER
172inline u16 swap16(u16 _data) {return _byteswap_ushort(_data);} 172inline u16 swap16(u16 _data) {return _byteswap_ushort(_data);}
173inline u32 swap32(u32 _data) {return _byteswap_ulong (_data);} 173inline u32 swap32(u32 _data) {return _byteswap_ulong (_data);}
174inline u64 swap64(u64 _data) {return _byteswap_uint64(_data);} 174inline u64 swap64(u64 _data) {return _byteswap_uint64(_data);}
diff --git a/src/common/log.h b/src/common/log.h
index 96d97249f..667f2fbb9 100644
--- a/src/common/log.h
+++ b/src/common/log.h
@@ -8,7 +8,7 @@
8#include "common/msg_handler.h" 8#include "common/msg_handler.h"
9#include "common/logging/log.h" 9#include "common/logging/log.h"
10 10
11#ifdef _WIN32 11#ifdef _MSC_VER
12#ifndef __func__ 12#ifndef __func__
13#define __func__ __FUNCTION__ 13#define __func__ __FUNCTION__
14#endif 14#endif
@@ -39,14 +39,18 @@
39 39
40#define _assert_(_a_) _dbg_assert_(MASTER_LOG, _a_) 40#define _assert_(_a_) _dbg_assert_(MASTER_LOG, _a_)
41 41
42#ifdef _WIN32 42#ifndef GEKKO
43#ifdef _MSC_VER
43#define _assert_msg_(_t_, _a_, _fmt_, ...) \ 44#define _assert_msg_(_t_, _a_, _fmt_, ...) \
44 if (!(_a_)) {\ 45 if (!(_a_)) {\
45 if (!PanicYesNo(_fmt_, __VA_ARGS__)) {Crash();} \ 46 if (!PanicYesNo(_fmt_, __VA_ARGS__)) {Crash();} \
46 } 47 }
47#else // not win32 48#else // not msvc
48#define _assert_msg_(_t_, _a_, _fmt_, ...) \ 49#define _assert_msg_(_t_, _a_, _fmt_, ...) \
49 if (!(_a_)) {\ 50 if (!(_a_)) {\
50 if (!PanicYesNo(_fmt_, ##__VA_ARGS__)) {Crash();} \ 51 if (!PanicYesNo(_fmt_, ##__VA_ARGS__)) {Crash();} \
51 } 52 }
52#endif // WIN32 53#endif // _WIN32
54#else // GEKKO
55#define _assert_msg_(_t_, _a_, _fmt_, ...)
56#endif \ No newline at end of file
diff --git a/src/common/msg_handler.h b/src/common/msg_handler.h
index 7bb216e98..5a483ddb4 100644
--- a/src/common/msg_handler.h
+++ b/src/common/msg_handler.h
@@ -30,7 +30,7 @@ extern bool MsgAlert(bool yes_no, int Style, const char* format, ...)
30void SetEnableAlert(bool enable); 30void SetEnableAlert(bool enable);
31 31
32#ifndef GEKKO 32#ifndef GEKKO
33#ifdef _WIN32 33#ifdef _MSC_VER
34 #define SuccessAlert(format, ...) MsgAlert(false, INFORMATION, format, __VA_ARGS__) 34 #define SuccessAlert(format, ...) MsgAlert(false, INFORMATION, format, __VA_ARGS__)
35 #define PanicAlert(format, ...) MsgAlert(false, WARNING, format, __VA_ARGS__) 35 #define PanicAlert(format, ...) MsgAlert(false, WARNING, format, __VA_ARGS__)
36 #define PanicYesNo(format, ...) MsgAlert(true, WARNING, format, __VA_ARGS__) 36 #define PanicYesNo(format, ...) MsgAlert(true, WARNING, format, __VA_ARGS__)
diff --git a/src/common/platform.h b/src/common/platform.h
index 53d98fe74..ce9cfd4a2 100644
--- a/src/common/platform.h
+++ b/src/common/platform.h
@@ -71,14 +71,18 @@
71 71
72#include <time.h> 72#include <time.h>
73 73
74#ifndef NOMINMAX
74#define NOMINMAX 75#define NOMINMAX
76#endif
75#define EMU_FASTCALL __fastcall 77#define EMU_FASTCALL __fastcall
76 78
79#ifdef _MSC_VER
77inline struct tm* localtime_r(const time_t *clock, struct tm *result) { 80inline struct tm* localtime_r(const time_t *clock, struct tm *result) {
78 if (localtime_s(result, clock) == 0) 81 if (localtime_s(result, clock) == 0)
79 return result; 82 return result;
80 return nullptr; 83 return nullptr;
81} 84}
85#endif
82 86
83#else 87#else
84 88
diff --git a/src/common/string_util.cpp b/src/common/string_util.cpp
index d919b7a4c..b3b772bd9 100644
--- a/src/common/string_util.cpp
+++ b/src/common/string_util.cpp
@@ -7,7 +7,7 @@
7#include "common/common.h" 7#include "common/common.h"
8#include "common/string_util.h" 8#include "common/string_util.h"
9 9
10#ifdef _WIN32 10#ifdef _MSC_VER
11 #include <Windows.h> 11 #include <Windows.h>
12 #include <codecvt> 12 #include <codecvt>
13#else 13#else
@@ -45,7 +45,7 @@ bool CharArrayFromFormatV(char* out, int outsize, const char* format, va_list ar
45{ 45{
46 int writtenCount; 46 int writtenCount;
47 47
48#ifdef _WIN32 48#ifdef _MSC_VER
49 // You would think *printf are simple, right? Iterate on each character, 49 // You would think *printf are simple, right? Iterate on each character,
50 // if it's a format specifier handle it properly, etc. 50 // if it's a format specifier handle it properly, etc.
51 // 51 //
@@ -410,7 +410,7 @@ std::string UriEncode(const std::string & sSrc)
410 return sResult; 410 return sResult;
411} 411}
412 412
413#ifdef _WIN32 413#ifdef _MSC_VER
414 414
415std::string UTF16ToUTF8(const std::u16string& input) 415std::string UTF16ToUTF8(const std::u16string& input)
416{ 416{
diff --git a/src/common/thread.cpp b/src/common/thread.cpp
index 8c83d67b5..8bf005857 100644
--- a/src/common/thread.cpp
+++ b/src/common/thread.cpp
@@ -17,7 +17,7 @@ namespace Common
17 17
18int CurrentThreadId() 18int CurrentThreadId()
19{ 19{
20#ifdef _WIN32 20#ifdef _MSC_VER
21 return GetCurrentThreadId(); 21 return GetCurrentThreadId();
22#elif defined __APPLE__ 22#elif defined __APPLE__
23 return mach_thread_self(); 23 return mach_thread_self();
@@ -27,6 +27,14 @@ int CurrentThreadId()
27} 27}
28 28
29#ifdef _WIN32 29#ifdef _WIN32
30// Supporting functions
31void SleepCurrentThread(int ms)
32{
33 Sleep(ms);
34}
35#endif
36
37#ifdef _MSC_VER
30 38
31void SetThreadAffinity(std::thread::native_handle_type thread, u32 mask) 39void SetThreadAffinity(std::thread::native_handle_type thread, u32 mask)
32{ 40{
@@ -38,12 +46,6 @@ void SetCurrentThreadAffinity(u32 mask)
38 SetThreadAffinityMask(GetCurrentThread(), mask); 46 SetThreadAffinityMask(GetCurrentThread(), mask);
39} 47}
40 48
41// Supporting functions
42void SleepCurrentThread(int ms)
43{
44 Sleep(ms);
45}
46
47void SwitchCurrentThread() 49void SwitchCurrentThread()
48{ 50{
49 SwitchToThread(); 51 SwitchToThread();
@@ -82,7 +84,7 @@ void SetCurrentThreadName(const char* szThreadName)
82 {} 84 {}
83} 85}
84 86
85#else // !WIN32, so must be POSIX threads 87#else // !MSVC_VER, so must be POSIX threads
86 88
87void SetThreadAffinity(std::thread::native_handle_type thread, u32 mask) 89void SetThreadAffinity(std::thread::native_handle_type thread, u32 mask)
88{ 90{
@@ -106,6 +108,7 @@ void SetCurrentThreadAffinity(u32 mask)
106 SetThreadAffinity(pthread_self(), mask); 108 SetThreadAffinity(pthread_self(), mask);
107} 109}
108 110
111#ifndef _WIN32
109void SleepCurrentThread(int ms) 112void SleepCurrentThread(int ms)
110{ 113{
111 usleep(1000 * ms); 114 usleep(1000 * ms);
@@ -115,7 +118,10 @@ void SwitchCurrentThread()
115{ 118{
116 usleep(1000 * 1); 119 usleep(1000 * 1);
117} 120}
121#endif
118 122
123// MinGW with the POSIX threading model does not support pthread_setname_np
124#if !defined(_WIN32) || defined(_MSC_VER)
119void SetCurrentThreadName(const char* szThreadName) 125void SetCurrentThreadName(const char* szThreadName)
120{ 126{
121#ifdef __APPLE__ 127#ifdef __APPLE__
@@ -126,6 +132,7 @@ void SetCurrentThreadName(const char* szThreadName)
126 pthread_setname_np(pthread_self(), szThreadName); 132 pthread_setname_np(pthread_self(), szThreadName);
127#endif 133#endif
128} 134}
135#endif
129 136
130#endif 137#endif
131 138
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index 3afc26f56..c61ae0053 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -18,6 +18,7 @@ using namespace std;
18#include "arm_dyncom_thumb.h" 18#include "arm_dyncom_thumb.h"
19#include "arm_dyncom_run.h" 19#include "arm_dyncom_run.h"
20#include "core/arm/skyeye_common/vfp/vfp.h" 20#include "core/arm/skyeye_common/vfp/vfp.h"
21#include "core/arm/disassembler/arm_disasm.h"
21 22
22#include "core/mem_map.h" 23#include "core/mem_map.h"
23#include "core/hle/hle.h" 24#include "core/hle/hle.h"
@@ -275,50 +276,7 @@ typedef struct _MiscRegPstIdx {
275typedef struct _LSWordorUnsignedByte { 276typedef struct _LSWordorUnsignedByte {
276} LDnST; 277} LDnST;
277 278
278#if USER_MODE_OPT 279typedef void (*get_addr_fp_t)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw);
279static inline fault_t interpreter_read_memory(addr_t virt_addr, addr_t phys_addr, uint32_t &value, uint32_t size){
280 switch(size) {
281 case 8:
282 value = Memory::Read8(virt_addr);
283 break;
284 case 16:
285 value = Memory::Read16(virt_addr);
286 break;
287 case 32:
288 value = Memory::Read32(virt_addr);
289 break;
290 }
291 return NO_FAULT;
292}
293
294static inline fault_t interpreter_write_memory(addr_t virt_addr, addr_t phys_addr, uint32_t value, uint32_t size) {
295 switch(size) {
296 case 8:
297 Memory::Write8(virt_addr, value & 0xff);
298 break;
299 case 16:
300 Memory::Write16(virt_addr, value & 0xffff);
301 break;
302 case 32:
303 Memory::Write32(virt_addr, value);
304 break;
305 }
306 return NO_FAULT;
307}
308
309static inline fault_t check_address_validity(arm_core_t *core, addr_t virt_addr, addr_t *phys_addr, uint32_t rw) {
310 *phys_addr = virt_addr;
311 return NO_FAULT;
312}
313
314#else
315fault_t interpreter_read_memory(cpu_t *cpu, addr_t virt_addr, addr_t phys_addr, uint32_t &value, uint32_t size);
316fault_t interpreter_write_memory(cpu_t *cpu, addr_t virt_addr, addr_t phys_addr, uint32_t value, uint32_t size);
317fault_t interpreter_fetch(cpu_t *cpu, addr_t virt_addr, uint32_t &value, uint32_t size);
318fault_t check_address_validity(arm_core_t *core, addr_t virt_addr, addr_t *phys_addr, uint32_t rw, tlb_type_t access_type = DATA_TLB);
319#endif
320
321typedef fault_t (*get_addr_fp_t)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw);
322 280
323typedef struct _ldst_inst { 281typedef struct _ldst_inst {
324 unsigned int inst; 282 unsigned int inst;
@@ -336,133 +294,105 @@ int CondPassed(arm_processor *cpu, unsigned int cond);
336#define I_BIT BIT(inst, 25) 294#define I_BIT BIT(inst, 25)
337#define P_BIT BIT(inst, 24) 295#define P_BIT BIT(inst, 24)
338#define OFFSET_12 BITS(inst, 0, 11) 296#define OFFSET_12 BITS(inst, 0, 11)
339fault_t LnSWoUB(ImmediateOffset)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw) { 297
298void LnSWoUB(ImmediateOffset)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
340 unsigned int Rn = BITS(inst, 16, 19); 299 unsigned int Rn = BITS(inst, 16, 19);
341 unsigned int addr; 300 unsigned int addr;
342 fault_t fault; 301
343 if (U_BIT) { 302 if (U_BIT)
344 addr = CHECK_READ_REG15_WA(cpu, Rn) + OFFSET_12; 303 addr = CHECK_READ_REG15_WA(cpu, Rn) + OFFSET_12;
345 } else { 304 else
346 addr = CHECK_READ_REG15_WA(cpu, Rn) - OFFSET_12; 305 addr = CHECK_READ_REG15_WA(cpu, Rn) - OFFSET_12;
347 } 306
348 virt_addr = addr; 307 virt_addr = addr;
349 fault = check_address_validity(cpu, addr, &phys_addr, rw);
350 return fault;
351} 308}
352 309
353fault_t LnSWoUB(RegisterOffset)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw) { 310void LnSWoUB(RegisterOffset)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
354 fault_t fault;
355 unsigned int Rn = BITS(inst, 16, 19); 311 unsigned int Rn = BITS(inst, 16, 19);
356 unsigned int Rm = BITS(inst, 0, 3); 312 unsigned int Rm = BITS(inst, 0, 3);
357 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); 313 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
358 unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm); 314 unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm);
359 unsigned int addr; 315 unsigned int addr;
360 if (U_BIT) { 316
317 if (U_BIT)
361 addr = rn + rm; 318 addr = rn + rm;
362 } else { 319 else
363 addr = rn - rm; 320 addr = rn - rm;
364 } 321
365 virt_addr = addr; 322 virt_addr = addr;
366 fault = check_address_validity(cpu, addr, &phys_addr, rw);
367 return fault;
368} 323}
369 324
370fault_t LnSWoUB(ImmediatePostIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw) { 325void LnSWoUB(ImmediatePostIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
371 fault_t fault;
372 unsigned int Rn = BITS(inst, 16, 19); 326 unsigned int Rn = BITS(inst, 16, 19);
373 unsigned int addr = CHECK_READ_REG15_WA(cpu, Rn); 327 unsigned int addr = CHECK_READ_REG15_WA(cpu, Rn);
374
375 virt_addr = addr;
376 fault = check_address_validity(cpu, addr, &phys_addr, rw);
377 if (fault) return fault;
378 328
379 if (U_BIT) { 329 if (U_BIT)
380 cpu->Reg[Rn] += OFFSET_12; 330 cpu->Reg[Rn] += OFFSET_12;
381 } else { 331 else
382 cpu->Reg[Rn] -= OFFSET_12; 332 cpu->Reg[Rn] -= OFFSET_12;
383 } 333
384 return fault; 334 virt_addr = addr;
385} 335}
386 336
387fault_t LnSWoUB(ImmediatePreIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw) { 337void LnSWoUB(ImmediatePreIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
388 fault_t fault;
389 unsigned int Rn = BITS(inst, 16, 19); 338 unsigned int Rn = BITS(inst, 16, 19);
390 unsigned int addr; 339 unsigned int addr;
391 if (U_BIT) { 340
341 if (U_BIT)
392 addr = CHECK_READ_REG15_WA(cpu, Rn) + OFFSET_12; 342 addr = CHECK_READ_REG15_WA(cpu, Rn) + OFFSET_12;
393 } else { 343 else
394 addr = CHECK_READ_REG15_WA(cpu, Rn) - OFFSET_12; 344 addr = CHECK_READ_REG15_WA(cpu, Rn) - OFFSET_12;
395 }
396 345
397 virt_addr = addr; 346 virt_addr = addr;
398 fault = check_address_validity(cpu, addr, &phys_addr, rw);
399 if (fault) return fault;
400 347
401 if (CondPassed(cpu, BITS(inst, 28, 31))) { 348 if (CondPassed(cpu, BITS(inst, 28, 31)))
402 cpu->Reg[Rn] = addr; 349 cpu->Reg[Rn] = addr;
403 }
404 return fault;
405} 350}
406 351
407fault_t MLnS(RegisterPreIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw) { 352void MLnS(RegisterPreIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
408 fault_t fault;
409 unsigned int addr; 353 unsigned int addr;
410 unsigned int Rn = BITS(inst, 16, 19); 354 unsigned int Rn = BITS(inst, 16, 19);
411 unsigned int Rm = BITS(inst, 0, 3); 355 unsigned int Rm = BITS(inst, 0, 3);
412 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); 356 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
413 unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm); 357 unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm);
414 358
415 if (U_BIT) { 359 if (U_BIT)
416 addr = rn + rm; 360 addr = rn + rm;
417 } else 361 else
418 addr = rn - rm; 362 addr = rn - rm;
419 if(BIT(inst, 20)){ // L BIT
420 }
421 if(BIT(inst, 6)){ // Sign Bit
422 }
423 if(BIT(inst, 5)){ // Half Bit
424 }
425 363
426 virt_addr = addr; 364 virt_addr = addr;
427 fault = check_address_validity(cpu, addr, &phys_addr, rw);
428 if (fault) return fault;
429 365
430 if (CondPassed(cpu, BITS(inst, 28, 31))) { 366 if (CondPassed(cpu, BITS(inst, 28, 31)))
431 cpu->Reg[Rn] = addr; 367 cpu->Reg[Rn] = addr;
432 }
433 return fault;
434} 368}
435 369
436fault_t LnSWoUB(RegisterPreIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw) { 370void LnSWoUB(RegisterPreIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
437 fault_t fault;
438 unsigned int Rn = BITS(inst, 16, 19); 371 unsigned int Rn = BITS(inst, 16, 19);
439 unsigned int Rm = BITS(inst, 0, 3); 372 unsigned int Rm = BITS(inst, 0, 3);
440 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); 373 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
441 unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm); 374 unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm);
442 unsigned int addr; 375 unsigned int addr;
443 if (U_BIT) { 376
377 if (U_BIT)
444 addr = rn + rm; 378 addr = rn + rm;
445 } else { 379 else
446 addr = rn - rm; 380 addr = rn - rm;
447 } 381
448 virt_addr = addr; 382 virt_addr = addr;
449 fault = check_address_validity(cpu, addr, &phys_addr, rw); 383
450 if(fault)
451 return fault;
452 if (CondPassed(cpu, BITS(inst, 28, 31))) { 384 if (CondPassed(cpu, BITS(inst, 28, 31))) {
453 cpu->Reg[Rn] = addr; 385 cpu->Reg[Rn] = addr;
454 } 386 }
455 return fault;
456} 387}
457fault_t LnSWoUB(ScaledRegisterPreIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw) { 388
458 fault_t fault; 389void LnSWoUB(ScaledRegisterPreIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
459 unsigned int shift = BITS(inst, 5, 6); 390 unsigned int shift = BITS(inst, 5, 6);
460 unsigned int shift_imm = BITS(inst, 7, 11); 391 unsigned int shift_imm = BITS(inst, 7, 11);
461 unsigned int Rn = BITS(inst, 16, 19); 392 unsigned int Rn = BITS(inst, 16, 19);
462 unsigned int Rm = BITS(inst, 0, 3); 393 unsigned int Rm = BITS(inst, 0, 3);
463 unsigned int index; 394 unsigned int index;
464 unsigned int addr; 395 unsigned int addr;
465
466 unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm); 396 unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm);
467 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); 397 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
468 398
@@ -484,33 +414,27 @@ fault_t LnSWoUB(ScaledRegisterPreIndexed)(arm_processor *cpu, unsigned int inst,
484 DEBUG_MSG; 414 DEBUG_MSG;
485 break; 415 break;
486 } 416 }
487 if (U_BIT) { 417
418 if (U_BIT)
488 addr = rn + index; 419 addr = rn + index;
489 } else 420 else
490 addr = rn - index; 421 addr = rn - index;
422
491 virt_addr = addr; 423 virt_addr = addr;
492 fault = check_address_validity(cpu, addr, &phys_addr, rw);
493 if(fault)
494 return fault;
495 if (CondPassed(cpu, BITS(inst, 28, 31))) {
496 cpu->Reg[Rn] = addr;
497 }
498 424
499 return fault; 425 if (CondPassed(cpu, BITS(inst, 28, 31)))
426 cpu->Reg[Rn] = addr;
500} 427}
501 428
502fault_t LnSWoUB(ScaledRegisterPostIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw) { 429void LnSWoUB(ScaledRegisterPostIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
503 fault_t fault;
504 unsigned int shift = BITS(inst, 5, 6); 430 unsigned int shift = BITS(inst, 5, 6);
505 unsigned int shift_imm = BITS(inst, 7, 11); 431 unsigned int shift_imm = BITS(inst, 7, 11);
506 unsigned int Rn = BITS(inst, 16, 19); 432 unsigned int Rn = BITS(inst, 16, 19);
507 unsigned int Rm = BITS(inst, 0, 3); 433 unsigned int Rm = BITS(inst, 0, 3);
508 unsigned int index; 434 unsigned int index;
509 unsigned int addr; 435 unsigned int addr = CHECK_READ_REG15_WA(cpu, Rn);
510
511 unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm); 436 unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm);
512 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); 437
513 addr = rn;
514 switch (shift) { 438 switch (shift) {
515 case 0: 439 case 0:
516 index = rm << shift_imm; 440 index = rm << shift_imm;
@@ -529,31 +453,23 @@ fault_t LnSWoUB(ScaledRegisterPostIndexed)(arm_processor *cpu, unsigned int inst
529 DEBUG_MSG; 453 DEBUG_MSG;
530 break; 454 break;
531 } 455 }
456
532 virt_addr = addr; 457 virt_addr = addr;
533 fault = check_address_validity(cpu, addr, &phys_addr, rw); 458
534 if(fault)
535 return fault;
536 if (CondPassed(cpu, BITS(inst, 28, 31))) { 459 if (CondPassed(cpu, BITS(inst, 28, 31))) {
537 if (U_BIT) 460 if (U_BIT)
538 cpu->Reg[Rn] += index; 461 cpu->Reg[Rn] += index;
539 else 462 else
540 cpu->Reg[Rn] -= index; 463 cpu->Reg[Rn] -= index;
541 } 464 }
542
543 return fault;
544} 465}
545 466
546fault_t LnSWoUB(RegisterPostIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw) { 467void LnSWoUB(RegisterPostIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
547 fault_t fault;
548 unsigned int Rn = BITS(inst, 16, 19); 468 unsigned int Rn = BITS(inst, 16, 19);
549 unsigned int Rm = BITS(inst, 0, 3); 469 unsigned int Rm = BITS(inst, 0, 3);
550 unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm); 470 unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm);
551 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
552 471
553 unsigned int addr = rn; 472 virt_addr = CHECK_READ_REG15_WA(cpu, Rn);
554 virt_addr = addr;
555 fault = check_address_validity(cpu, addr, &phys_addr, rw);
556 if (fault) return fault;
557 473
558 if (CondPassed(cpu, BITS(inst, 28, 31))) { 474 if (CondPassed(cpu, BITS(inst, 28, 31))) {
559 if (U_BIT) { 475 if (U_BIT) {
@@ -562,52 +478,40 @@ fault_t LnSWoUB(RegisterPostIndexed)(arm_processor *cpu, unsigned int inst, unsi
562 cpu->Reg[Rn] -= rm; 478 cpu->Reg[Rn] -= rm;
563 } 479 }
564 } 480 }
565 return fault;
566} 481}
567 482
568fault_t MLnS(ImmediateOffset)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw) { 483void MLnS(ImmediateOffset)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
569 fault_t fault;
570 unsigned int immedL = BITS(inst, 0, 3); 484 unsigned int immedL = BITS(inst, 0, 3);
571 unsigned int immedH = BITS(inst, 8, 11); 485 unsigned int immedH = BITS(inst, 8, 11);
572
573 unsigned int Rn = BITS(inst, 16, 19); 486 unsigned int Rn = BITS(inst, 16, 19);
574 unsigned int addr; 487 unsigned int addr;
575 488
576 unsigned int offset_8 = (immedH << 4) | immedL; 489 unsigned int offset_8 = (immedH << 4) | immedL;
577 if (U_BIT) { 490
491 if (U_BIT)
578 addr = CHECK_READ_REG15_WA(cpu, Rn) + offset_8; 492 addr = CHECK_READ_REG15_WA(cpu, Rn) + offset_8;
579 } else 493 else
580 addr = CHECK_READ_REG15_WA(cpu, Rn) - offset_8; 494 addr = CHECK_READ_REG15_WA(cpu, Rn) - offset_8;
581 495
582 virt_addr = addr; 496 virt_addr = addr;
583 fault = check_address_validity(cpu, addr, &phys_addr, rw);
584 return fault;
585} 497}
586 498
587fault_t MLnS(RegisterOffset)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw) { 499void MLnS(RegisterOffset)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
588 fault_t fault;
589 unsigned int addr; 500 unsigned int addr;
590 unsigned int Rn = BITS(inst, 16, 19); 501 unsigned int Rn = BITS(inst, 16, 19);
591 unsigned int Rm = BITS(inst, 0, 3); 502 unsigned int Rm = BITS(inst, 0, 3);
592 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); 503 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
593 unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm); 504 unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm);
594 if (U_BIT) { 505
506 if (U_BIT)
595 addr = rn + rm; 507 addr = rn + rm;
596 } else 508 else
597 addr = rn - rm; 509 addr = rn - rm;
598 if(BIT(inst, 20)){ // L BIT 510
599 }
600 if(BIT(inst, 6)){ // Sign Bit
601 }
602 if(BIT(inst, 5)){ // Half Bit
603 }
604 virt_addr = addr; 511 virt_addr = addr;
605 fault = check_address_validity(cpu, addr, &phys_addr, rw);
606 return fault;
607} 512}
608 513
609fault_t MLnS(ImmediatePreIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw) { 514void MLnS(ImmediatePreIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
610 fault_t fault;
611 unsigned int Rn = BITS(inst, 16, 19); 515 unsigned int Rn = BITS(inst, 16, 19);
612 unsigned int immedH = BITS(inst, 8, 11); 516 unsigned int immedH = BITS(inst, 8, 11);
613 unsigned int immedL = BITS(inst, 0, 3); 517 unsigned int immedL = BITS(inst, 0, 3);
@@ -615,189 +519,129 @@ fault_t MLnS(ImmediatePreIndexed)(arm_processor *cpu, unsigned int inst, unsigne
615 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); 519 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
616 unsigned int offset_8 = (immedH << 4) | immedL; 520 unsigned int offset_8 = (immedH << 4) | immedL;
617 521
618 if (U_BIT) { 522 if (U_BIT)
619 addr = rn + offset_8; 523 addr = rn + offset_8;
620 } else 524 else
621 addr = rn - offset_8; 525 addr = rn - offset_8;
622 526
623 virt_addr = addr; 527 virt_addr = addr;
624 fault = check_address_validity(cpu, addr, &phys_addr, rw);
625 if (fault) return fault;
626 528
627 if (CondPassed(cpu, BITS(inst, 28, 31))) { 529 if (CondPassed(cpu, BITS(inst, 28, 31)))
628 cpu->Reg[Rn] = addr; 530 cpu->Reg[Rn] = addr;
629 }
630 return fault;
631} 531}
632 532
633fault_t MLnS(ImmediatePostIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw) { 533void MLnS(ImmediatePostIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
634 fault_t fault;
635 unsigned int Rn = BITS(inst, 16, 19); 534 unsigned int Rn = BITS(inst, 16, 19);
636 unsigned int immedH = BITS(inst, 8, 11); 535 unsigned int immedH = BITS(inst, 8, 11);
637 unsigned int immedL = BITS(inst, 0, 3); 536 unsigned int immedL = BITS(inst, 0, 3);
638 unsigned int addr;
639 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); 537 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
640 addr = rn;
641 538
642 virt_addr = addr; 539 virt_addr = rn;
643 fault = check_address_validity(cpu, addr, &phys_addr, rw);
644 if (fault) return fault;
645 540
646 if (CondPassed(cpu, BITS(inst, 28, 31))) { 541 if (CondPassed(cpu, BITS(inst, 28, 31))) {
647 unsigned int offset_8 = (immedH << 4) | immedL; 542 unsigned int offset_8 = (immedH << 4) | immedL;
648 if (U_BIT) { 543 if (U_BIT)
649 rn += offset_8; 544 rn += offset_8;
650 } else { 545 else
651 rn -= offset_8; 546 rn -= offset_8;
652 } 547
653 cpu->Reg[Rn] = rn; 548 cpu->Reg[Rn] = rn;
654 } 549 }
655
656 return fault;
657} 550}
658fault_t MLnS(RegisterPostIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw) { 551
659 fault_t fault; 552void MLnS(RegisterPostIndexed)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
660 unsigned int Rn = BITS(inst, 16, 19); 553 unsigned int Rn = BITS(inst, 16, 19);
661 unsigned int Rm = BITS(inst, 0, 3); 554 unsigned int Rm = BITS(inst, 0, 3);
662 unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm); 555 unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm);
663 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
664 unsigned int addr = rn;
665 556
666 virt_addr = addr; 557 virt_addr = CHECK_READ_REG15_WA(cpu, Rn);
667 fault = check_address_validity(cpu, addr, &phys_addr, rw);
668 if (fault) return fault;
669 558
670 if (CondPassed(cpu, BITS(inst, 28, 31))) { 559 if (CondPassed(cpu, BITS(inst, 28, 31))) {
671 if (U_BIT) { 560 if (U_BIT)
672 cpu->Reg[Rn] += rm; 561 cpu->Reg[Rn] += rm;
673 } else { 562 else
674 cpu->Reg[Rn] -= rm; 563 cpu->Reg[Rn] -= rm;
675 }
676 } 564 }
677 return fault;
678} 565}
679 566
680fault_t LdnStM(DecrementBefore)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw) { 567void LdnStM(DecrementBefore)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
681 fault_t fault;
682 unsigned int Rn = BITS(inst, 16, 19); 568 unsigned int Rn = BITS(inst, 16, 19);
683 unsigned int i = BITS(inst, 0, 15); 569 unsigned int i = BITS(inst, 0, 15);
684 int count = 0; 570 int count = 0;
685 while(i) { 571
686 if(i & 1) count ++; 572 while (i) {
573 if (i & 1) count++;
687 i = i >> 1; 574 i = i >> 1;
688 } 575 }
689 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
690 unsigned int start_addr = rn - count * 4;
691 unsigned int end_addr = rn - 4;
692 576
693 fault = check_address_validity(cpu, end_addr, &phys_addr, rw); 577 virt_addr = CHECK_READ_REG15_WA(cpu, Rn) - count * 4;
694 virt_addr = end_addr;
695 if (fault) return fault;
696
697 fault = check_address_validity(cpu, start_addr, &phys_addr, rw);
698 virt_addr = start_addr;
699 if (fault) return fault;
700 578
701 if (CondPassed(cpu, BITS(inst, 28, 31)) && BIT(inst, 21)) { 579 if (CondPassed(cpu, BITS(inst, 28, 31)) && BIT(inst, 21))
702 cpu->Reg[Rn] -= count * 4; 580 cpu->Reg[Rn] -= count * 4;
703 }
704
705 return fault;
706} 581}
707 582
708fault_t LdnStM(IncrementBefore)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw) { 583void LdnStM(IncrementBefore)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
709 fault_t fault;
710 unsigned int Rn = BITS(inst, 16, 19); 584 unsigned int Rn = BITS(inst, 16, 19);
711 unsigned int i = BITS(inst, 0, 15); 585 unsigned int i = BITS(inst, 0, 15);
712 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
713 int count = 0; 586 int count = 0;
714 while(i) { 587
715 if(i & 1) count ++; 588 while (i) {
589 if (i & 1) count++;
716 i = i >> 1; 590 i = i >> 1;
717 } 591 }
718 592
719 unsigned int start_addr = rn + 4; 593 virt_addr = CHECK_READ_REG15_WA(cpu, Rn) + 4;
720 unsigned int end_addr = rn + count * 4;
721
722 fault = check_address_validity(cpu, end_addr, &phys_addr, rw);
723 virt_addr = end_addr;
724 if (fault) return fault;
725
726 fault = check_address_validity(cpu, start_addr, &phys_addr, rw);
727 virt_addr = start_addr;
728 if (fault) return fault;
729 594
730 if (CondPassed(cpu, BITS(inst, 28, 31)) && BIT(inst, 21)) { 595 if (CondPassed(cpu, BITS(inst, 28, 31)) && BIT(inst, 21))
731 cpu->Reg[Rn] += count * 4; 596 cpu->Reg[Rn] += count * 4;
732 }
733 return fault;
734} 597}
735 598
736fault_t LdnStM(IncrementAfter)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw) { 599void LdnStM(IncrementAfter)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
737 fault_t fault;
738 unsigned int Rn = BITS(inst, 16, 19); 600 unsigned int Rn = BITS(inst, 16, 19);
739 unsigned int i = BITS(inst, 0, 15); 601 unsigned int i = BITS(inst, 0, 15);
740 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
741 int count = 0; 602 int count = 0;
603
742 while(i) { 604 while(i) {
743 if(i & 1) count ++; 605 if (i & 1) count++;
744 i = i >> 1; 606 i = i >> 1;
745 } 607 }
746 unsigned int start_addr = rn;
747 unsigned int end_addr = rn + count * 4 - 4;
748 608
749 fault = check_address_validity(cpu, end_addr, &phys_addr, rw); 609 virt_addr = CHECK_READ_REG15_WA(cpu, Rn);
750 virt_addr = end_addr;
751 if (fault) return fault;
752
753 fault = check_address_validity(cpu, start_addr, &phys_addr, rw);
754 virt_addr = start_addr;
755 if (fault) return fault;
756 610
757 if (CondPassed(cpu, BITS(inst, 28, 31)) && BIT(inst, 21)) { 611 if (CondPassed(cpu, BITS(inst, 28, 31)) && BIT(inst, 21))
758 cpu->Reg[Rn] += count * 4; 612 cpu->Reg[Rn] += count * 4;
759 }
760 return fault;
761} 613}
762 614
763fault_t LdnStM(DecrementAfter)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw) { 615void LdnStM(DecrementAfter)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
764 fault_t fault;
765 unsigned int Rn = BITS(inst, 16, 19); 616 unsigned int Rn = BITS(inst, 16, 19);
766 unsigned int i = BITS(inst, 0, 15); 617 unsigned int i = BITS(inst, 0, 15);
767 int count = 0; 618 int count = 0;
768 while(i) { 619 while(i) {
769 if(i & 1) count ++; 620 if(i & 1) count++;
770 i = i >> 1; 621 i = i >> 1;
771 } 622 }
772 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); 623 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
773 unsigned int start_addr = rn - count * 4 + 4; 624 unsigned int start_addr = rn - count * 4 + 4;
774 unsigned int end_addr = rn; 625 unsigned int end_addr = rn;
775 626
776 fault = check_address_validity(cpu, end_addr, &phys_addr, rw);
777 virt_addr = end_addr; 627 virt_addr = end_addr;
778 if (fault) return fault;
779
780 fault = check_address_validity(cpu, start_addr, &phys_addr, rw);
781 if (fault) return fault;
782 virt_addr = start_addr; 628 virt_addr = start_addr;
783 629
784 if (CondPassed(cpu, BITS(inst, 28, 31)) && BIT(inst, 21)) { 630 if (CondPassed(cpu, BITS(inst, 28, 31)) && BIT(inst, 21)) {
785 cpu->Reg[Rn] -= count * 4; 631 cpu->Reg[Rn] -= count * 4;
786 } 632 }
787 return fault;
788} 633}
789 634
790fault_t LnSWoUB(ScaledRegisterOffset)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int &phys_addr, unsigned int rw) { 635void LnSWoUB(ScaledRegisterOffset)(arm_processor *cpu, unsigned int inst, unsigned int &virt_addr, unsigned int rw) {
791 fault_t fault;
792 unsigned int shift = BITS(inst, 5, 6); 636 unsigned int shift = BITS(inst, 5, 6);
793 unsigned int shift_imm = BITS(inst, 7, 11); 637 unsigned int shift_imm = BITS(inst, 7, 11);
794 unsigned int Rn = BITS(inst, 16, 19); 638 unsigned int Rn = BITS(inst, 16, 19);
795 unsigned int Rm = BITS(inst, 0, 3); 639 unsigned int Rm = BITS(inst, 0, 3);
796 unsigned int index; 640 unsigned int index;
797 unsigned int addr; 641 unsigned int addr;
798
799 unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm); 642 unsigned int rm = CHECK_READ_REG15_WA(cpu, Rm);
800 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn); 643 unsigned int rn = CHECK_READ_REG15_WA(cpu, Rn);
644
801 switch (shift) { 645 switch (shift) {
802 case 0: 646 case 0:
803 index = rm << shift_imm; 647 index = rm << shift_imm;
@@ -815,8 +659,7 @@ fault_t LnSWoUB(ScaledRegisterOffset)(arm_processor *cpu, unsigned int inst, uns
815 index = 0xFFFFFFFF; 659 index = 0xFFFFFFFF;
816 else 660 else
817 index = 0; 661 index = 0;
818 } 662 } else {
819 else {
820 index = static_cast<int>(rm) >> shift_imm; 663 index = static_cast<int>(rm) >> shift_imm;
821 } 664 }
822 break; 665 break;
@@ -824,15 +667,13 @@ fault_t LnSWoUB(ScaledRegisterOffset)(arm_processor *cpu, unsigned int inst, uns
824 DEBUG_MSG; 667 DEBUG_MSG;
825 break; 668 break;
826 } 669 }
670
827 if (U_BIT) { 671 if (U_BIT) {
828 addr = rn + index; 672 addr = rn + index;
829 } else 673 } else
830 addr = rn - index; 674 addr = rn - index;
831 675
832 virt_addr = addr; 676 virt_addr = addr;
833 fault = check_address_validity(cpu, addr, &phys_addr, rw);
834
835 return fault;
836} 677}
837 678
838#define ISNEG(n) (n < 0) 679#define ISNEG(n) (n < 0)
@@ -3567,30 +3408,19 @@ int InterpreterTranslate(arm_processor *cpu, int &bb_start, addr_t addr) {
3567 if (cpu->TFlag) 3408 if (cpu->TFlag)
3568 thumb = THUMB; 3409 thumb = THUMB;
3569 3410
3570 addr_t phys_addr; 3411 addr_t phys_addr = addr;
3571 addr_t pc_start; 3412 addr_t pc_start = cpu->Reg[15];
3572 fault_t fault = NO_FAULT;
3573 fault = check_address_validity(cpu, addr, &phys_addr, 1);
3574 if(fault != NO_FAULT){
3575 cpu->abortSig = true;
3576 cpu->Aborted = ARMul_PrefetchAbortV;
3577 cpu->AbortAddr = addr;
3578 cpu->CP15[CP15(CP15_INSTR_FAULT_STATUS)] = fault & 0xff;
3579 cpu->CP15[CP15(CP15_FAULT_ADDRESS)] = addr;
3580 return FETCH_EXCEPTION;
3581 }
3582
3583 pc_start = phys_addr;
3584 3413
3585 while(ret == NON_BRANCH) { 3414 while(ret == NON_BRANCH) {
3586 inst = Memory::Read32(phys_addr & 0xFFFFFFFC);//*(uint32_t *)(phys_addr & 0xFFFFFFFC); 3415 inst = Memory::Read32(phys_addr & 0xFFFFFFFC);
3587 3416
3588 size ++; 3417 size++;
3589 // If we are in thumb instruction, we will translate one thumb to one corresponding arm instruction 3418 // If we are in thumb instruction, we will translate one thumb to one corresponding arm instruction
3590 if (cpu->TFlag) { 3419 if (cpu->TFlag) {
3591 uint32_t arm_inst; 3420 uint32_t arm_inst;
3592 tdstate state; 3421 tdstate state;
3593 state = decode_thumb_instr(cpu, inst, phys_addr, &arm_inst, &inst_size, &inst_base); 3422 state = decode_thumb_instr(cpu, inst, phys_addr, &arm_inst, &inst_size, &inst_base);
3423
3594 // We have translated the branch instruction of thumb in thumb decoder 3424 // We have translated the branch instruction of thumb in thumb decoder
3595 if(state == t_branch){ 3425 if(state == t_branch){
3596 goto translated; 3426 goto translated;
@@ -3600,7 +3430,8 @@ int InterpreterTranslate(arm_processor *cpu, int &bb_start, addr_t addr) {
3600 3430
3601 ret = decode_arm_instr(inst, &idx); 3431 ret = decode_arm_instr(inst, &idx);
3602 if (ret == DECODE_FAILURE) { 3432 if (ret == DECODE_FAILURE) {
3603 LOG_ERROR(Core_ARM11, "Decode failure.\tPC : [0x%x]\tInstruction : [%x]", phys_addr, inst); 3433 std::string disasm = ARM_Disasm::Disassemble(phys_addr, inst);
3434 LOG_ERROR(Core_ARM11, "Decode failure.\tPC : [0x%x]\tInstruction : %s [%x]", phys_addr, disasm.c_str(), inst);
3604 LOG_ERROR(Core_ARM11, "cpsr=0x%x, cpu->TFlag=%d, r15=0x%x", cpu->Cpsr, cpu->TFlag, cpu->Reg[15]); 3435 LOG_ERROR(Core_ARM11, "cpsr=0x%x, cpu->TFlag=%d, r15=0x%x", cpu->Cpsr, cpu->TFlag, cpu->Reg[15]);
3605 CITRA_IGNORE_EXIT(-1); 3436 CITRA_IGNORE_EXIT(-1);
3606 } 3437 }
@@ -3629,15 +3460,15 @@ void InterpreterInitInstLength(unsigned long long int *ptr, size_t size) {
3629 memcpy(InstLabel, ptr, size); 3460 memcpy(InstLabel, ptr, size);
3630 qsort(InstLabel, array_size, sizeof(void *), cmp); 3461 qsort(InstLabel, array_size, sizeof(void *), cmp);
3631 InstLength = new unsigned int[array_size - 4]; 3462 InstLength = new unsigned int[array_size - 4];
3632 for (int i = 0; i < array_size - 4; i ++) { 3463 for (int i = 0; i < array_size - 4; i++) {
3633 for (int j = 0; j < array_size; j ++) { 3464 for (int j = 0; j < array_size; j++) {
3634 if (ptr[i] == InstLabel[j]) { 3465 if (ptr[i] == InstLabel[j]) {
3635 InstLength[i] = InstLabel[j + 1] - InstLabel[j]; 3466 InstLength[i] = InstLabel[j + 1] - InstLabel[j];
3636 break; 3467 break;
3637 } 3468 }
3638 } 3469 }
3639 } 3470 }
3640 for (int i = 0; i < array_size - 4; i ++) 3471 for (int i = 0; i < array_size - 4; i++)
3641 LOG_DEBUG(Core_ARM11, "[%d]:%d", i, InstLength[i]); 3472 LOG_DEBUG(Core_ARM11, "[%d]:%d", i, InstLength[i]);
3642} 3473}
3643 3474
@@ -3954,7 +3785,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
3954 unsigned int phys_addr; 3785 unsigned int phys_addr;
3955 unsigned int last_pc = 0; 3786 unsigned int last_pc = 0;
3956 unsigned int num_instrs = 0; 3787 unsigned int num_instrs = 0;
3957 fault_t fault; 3788
3958 static unsigned int last_physical_base = 0, last_logical_base = 0; 3789 static unsigned int last_physical_base = 0, last_logical_base = 0;
3959 int ptr; 3790 int ptr;
3960 bool single_step = (cpu->NumInstrsToExecute == 1); 3791 bool single_step = (cpu->NumInstrsToExecute == 1);
@@ -3975,7 +3806,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
3975 3806
3976 phys_addr = cpu->Reg[15]; 3807 phys_addr = cpu->Reg[15];
3977 3808
3978 if (find_bb(phys_addr, ptr) == -1) 3809 if (find_bb(cpu->Reg[15], ptr) == -1)
3979 if (InterpreterTranslate(cpu, ptr, cpu->Reg[15]) == FETCH_EXCEPTION) 3810 if (InterpreterTranslate(cpu, ptr, cpu->Reg[15]) == FETCH_EXCEPTION)
3980 goto END; 3811 goto END;
3981 3812
@@ -4325,53 +4156,34 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
4325 { 4156 {
4326 ldst_inst *inst_cream = (ldst_inst *)inst_base->component; 4157 ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
4327 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 4158 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
4328 int i; 4159 inst_cream->get_addr(cpu, inst_cream->inst, addr, 1);
4329 unsigned int ret; 4160
4330 fault = inst_cream->get_addr(cpu, inst_cream->inst, addr, phys_addr, 1);
4331 if (fault) {
4332 goto MMU_EXCEPTION;
4333 }
4334 unsigned int inst = inst_cream->inst; 4161 unsigned int inst = inst_cream->inst;
4335 if (BIT(inst, 22) && !BIT(inst, 15)) { 4162 if (BIT(inst, 22) && !BIT(inst, 15)) {
4336 for (i = 0; i < 13; i++) { 4163 for (int i = 0; i < 13; i++) {
4337 if(BIT(inst, i)){ 4164 if(BIT(inst, i)) {
4338 fault = interpreter_read_memory(addr, phys_addr, ret, 32); 4165 cpu->Reg[i] = Memory::Read32(addr);
4339 cpu->Reg[i] = ret;
4340 addr += 4; 4166 addr += 4;
4341 if ((addr & 0xfff) == 0) {
4342 fault = check_address_validity(cpu, addr, &phys_addr, 1);
4343 } else {
4344 phys_addr += 4;
4345 }
4346 } 4167 }
4347 } 4168 }
4348 if (BIT(inst, 13)) { 4169 if (BIT(inst, 13)) {
4349 fault = interpreter_read_memory(addr, phys_addr, ret, 32);
4350
4351 if (cpu->Mode == USER32MODE) 4170 if (cpu->Mode == USER32MODE)
4352 cpu->Reg[13] = ret; 4171 cpu->Reg[13] = Memory::Read32(addr);
4353 else 4172 else
4354 cpu->Reg_usr[0] = ret; 4173 cpu->Reg_usr[0] = Memory::Read32(addr);
4174
4355 addr += 4; 4175 addr += 4;
4356 if ((addr & 0xfff) == 0) {
4357 fault = check_address_validity(cpu, addr, &phys_addr, 1);
4358 } else {
4359 phys_addr += 4;
4360 }
4361 } 4176 }
4362 if (BIT(inst, 14)) { 4177 if (BIT(inst, 14)) {
4363 fault = interpreter_read_memory(addr, phys_addr, ret, 32);
4364
4365 if (cpu->Mode == USER32MODE) 4178 if (cpu->Mode == USER32MODE)
4366 cpu->Reg[14] = ret; 4179 cpu->Reg[14] = Memory::Read32(addr);
4367 else 4180 else
4368 cpu->Reg_usr[1] = ret; 4181 cpu->Reg_usr[1] = Memory::Read32(addr);
4369 } 4182 }
4370 } else if (!BIT(inst, 22)) { 4183 } else if (!BIT(inst, 22)) {
4371 for( i = 0; i < 16; i ++ ){ 4184 for(int i = 0; i < 16; i++ ){
4372 if(BIT(inst, i)){ 4185 if(BIT(inst, i)){
4373 fault = interpreter_read_memory(addr, phys_addr, ret, 32); 4186 unsigned int ret = Memory::Read32(addr);
4374 if (fault) goto MMU_EXCEPTION;
4375 4187
4376 // For armv5t, should enter thumb when bits[0] is non-zero. 4188 // For armv5t, should enter thumb when bits[0] is non-zero.
4377 if(i == 15){ 4189 if(i == 15){
@@ -4381,39 +4193,25 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
4381 4193
4382 cpu->Reg[i] = ret; 4194 cpu->Reg[i] = ret;
4383 addr += 4; 4195 addr += 4;
4384 if ((addr & 0xfff) == 0) {
4385 fault = check_address_validity(cpu, addr, &phys_addr, 1);
4386 } else {
4387 phys_addr += 4;
4388 }
4389 } 4196 }
4390 } 4197 }
4391 } else if (BIT(inst, 22) && BIT(inst, 15)) { 4198 } else if (BIT(inst, 22) && BIT(inst, 15)) {
4392 for( i = 0; i < 15; i ++ ){ 4199 for(int i = 0; i < 15; i++ ){
4393 if(BIT(inst, i)){ 4200 if(BIT(inst, i)){
4394 fault = interpreter_read_memory(addr, phys_addr, ret, 32); 4201 cpu->Reg[i] = Memory::Read32(addr);
4395 cpu->Reg[i] = ret;
4396 addr += 4; 4202 addr += 4;
4397 if ((addr & 0xfff) == 0) {
4398 fault = check_address_validity(cpu, addr, &phys_addr, 1);
4399 } else {
4400 phys_addr += 4;
4401 }
4402 } 4203 }
4403 } 4204 }
4404 4205
4405 if (CurrentModeHasSPSR) { 4206 if (CurrentModeHasSPSR) {
4406 cpu->Cpsr = cpu->Spsr_copy; 4207 cpu->Cpsr = cpu->Spsr_copy;
4407 switch_mode(cpu, cpu->Cpsr & 0x1f); 4208 switch_mode(cpu, cpu->Cpsr & 0x1f);
4408 LOAD_NZCVT; 4209 LOAD_NZCVT;
4409 } 4210 }
4410 4211
4411 fault = interpreter_read_memory(addr, phys_addr, ret, 32); 4212 cpu->Reg[15] = Memory::Read32(addr);
4412 if (fault) { 4213 }
4413 goto MMU_EXCEPTION; 4214
4414 }
4415 cpu->Reg[15] = ret;
4416 }
4417 if (BIT(inst, 15)) { 4215 if (BIT(inst, 15)) {
4418 INC_PC(sizeof(ldst_inst)); 4216 INC_PC(sizeof(ldst_inst));
4419 goto DISPATCH; 4217 goto DISPATCH;
@@ -4445,16 +4243,16 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
4445 { 4243 {
4446 ldst_inst *inst_cream = (ldst_inst *)inst_base->component; 4244 ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
4447 //if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 4245 //if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
4448 fault = inst_cream->get_addr(cpu, inst_cream->inst, addr, phys_addr, 1); 4246 inst_cream->get_addr(cpu, inst_cream->inst, addr, 1);
4449 if (fault) goto MMU_EXCEPTION; 4247
4450 unsigned int value; 4248 unsigned int value = Memory::Read32(addr);
4451 fault = interpreter_read_memory(addr, phys_addr, value, 32);
4452 if (BIT(CP15_REG(CP15_CONTROL), 22) == 1) 4249 if (BIT(CP15_REG(CP15_CONTROL), 22) == 1)
4453 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; 4250 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
4454 else { 4251 else {
4455 value = ROTATE_RIGHT_32(value,(8*(addr&0x3))); 4252 value = ROTATE_RIGHT_32(value,(8*(addr&0x3)));
4456 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; 4253 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
4457 } 4254 }
4255
4458 if (BITS(inst_cream->inst, 12, 15) == 15) { 4256 if (BITS(inst_cream->inst, 12, 15) == 15) {
4459 // For armv5t, should enter thumb when bits[0] is non-zero. 4257 // For armv5t, should enter thumb when bits[0] is non-zero.
4460 cpu->TFlag = value & 0x1; 4258 cpu->TFlag = value & 0x1;
@@ -4463,6 +4261,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
4463 goto DISPATCH; 4261 goto DISPATCH;
4464 } 4262 }
4465 //} 4263 //}
4264
4466 cpu->Reg[15] += GET_INST_SIZE(cpu); 4265 cpu->Reg[15] += GET_INST_SIZE(cpu);
4467 INC_PC(sizeof(ldst_inst)); 4266 INC_PC(sizeof(ldst_inst));
4468 FETCH_INST; 4267 FETCH_INST;
@@ -4472,10 +4271,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
4472 { 4271 {
4473 ldst_inst *inst_cream = (ldst_inst *)inst_base->component; 4272 ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
4474 if (CondPassed(cpu, inst_base->cond)) { 4273 if (CondPassed(cpu, inst_base->cond)) {
4475 fault = inst_cream->get_addr(cpu, inst_cream->inst, addr, phys_addr, 1); 4274 inst_cream->get_addr(cpu, inst_cream->inst, addr, 1);
4476 if (fault) goto MMU_EXCEPTION; 4275 unsigned int value = Memory::Read32(addr);
4477 unsigned int value;
4478 fault = interpreter_read_memory(addr, phys_addr, value, 32);
4479 if (BIT(CP15_REG(CP15_CONTROL), 22) == 1) 4276 if (BIT(CP15_REG(CP15_CONTROL), 22) == 1)
4480 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; 4277 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
4481 else { 4278 else {
@@ -4530,12 +4327,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
4530 { 4327 {
4531 ldst_inst *inst_cream = (ldst_inst *)inst_base->component; 4328 ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
4532 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 4329 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
4533 fault = inst_cream->get_addr(cpu, inst_cream->inst, addr, phys_addr, 1); 4330 inst_cream->get_addr(cpu, inst_cream->inst, addr, 1);
4534 if (fault) goto MMU_EXCEPTION; 4331 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = Memory::Read8(addr);
4535 unsigned int value; 4332
4536 fault = interpreter_read_memory(addr, phys_addr, value, 8);
4537 if (fault) goto MMU_EXCEPTION;
4538 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
4539 if (BITS(inst_cream->inst, 12, 15) == 15) { 4333 if (BITS(inst_cream->inst, 12, 15) == 15) {
4540 INC_PC(sizeof(ldst_inst)); 4334 INC_PC(sizeof(ldst_inst));
4541 goto DISPATCH; 4335 goto DISPATCH;
@@ -4550,12 +4344,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
4550 { 4344 {
4551 ldst_inst *inst_cream = (ldst_inst *)inst_base->component; 4345 ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
4552 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 4346 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
4553 fault = inst_cream->get_addr(cpu, inst_cream->inst, addr, phys_addr, 1); 4347 inst_cream->get_addr(cpu, inst_cream->inst, addr, 1);
4554 if (fault) goto MMU_EXCEPTION; 4348 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = Memory::Read8(addr);
4555 unsigned int value; 4349
4556 fault = interpreter_read_memory(addr, phys_addr, value, 8);
4557 if (fault) goto MMU_EXCEPTION;
4558 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
4559 if (BITS(inst_cream->inst, 12, 15) == 15) { 4350 if (BITS(inst_cream->inst, 12, 15) == 15) {
4560 INC_PC(sizeof(ldst_inst)); 4351 INC_PC(sizeof(ldst_inst));
4561 goto DISPATCH; 4352 goto DISPATCH;
@@ -4571,22 +4362,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
4571 ldst_inst *inst_cream = (ldst_inst *)inst_base->component; 4362 ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
4572 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 4363 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
4573 // Should check if RD is even-numbered, Rd != 14, addr[0:1] == 0, (CP15_reg1_U == 1 || addr[2] == 0) 4364 // Should check if RD is even-numbered, Rd != 14, addr[0:1] == 0, (CP15_reg1_U == 1 || addr[2] == 0)
4574 fault = inst_cream->get_addr(cpu, inst_cream->inst, addr, phys_addr, 1); 4365 inst_cream->get_addr(cpu, inst_cream->inst, addr, 1);
4575 if (fault) goto MMU_EXCEPTION; 4366
4576 uint32_t rear_phys_addr; 4367 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = Memory::Read32(addr);
4577 fault = check_address_validity(cpu, addr + 4, &rear_phys_addr, 1); 4368 cpu->Reg[BITS(inst_cream->inst, 12, 15) + 1] = Memory::Read32(addr + 4);
4578 if(fault){
4579 LOG_ERROR(Core_ARM11, "MMU fault , should rollback the above get_addr\n");
4580 CITRA_IGNORE_EXIT(-1);
4581 goto MMU_EXCEPTION;
4582 }
4583 unsigned int value;
4584 fault = interpreter_read_memory(addr, phys_addr, value, 32);
4585 if (fault) goto MMU_EXCEPTION;
4586 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
4587 fault = interpreter_read_memory(addr + 4, rear_phys_addr, value, 32);
4588 if (fault) goto MMU_EXCEPTION;
4589 cpu->Reg[BITS(inst_cream->inst, 12, 15) + 1] = value;
4590 4369
4591 // No dispatch since this operation should not modify R15 4370 // No dispatch since this operation should not modify R15
4592 } 4371 }
@@ -4601,13 +4380,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
4601 ldst_inst *inst_cream = (ldst_inst *)inst_base->component; 4380 ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
4602 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 4381 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
4603 addr = cpu->Reg[BITS(inst_cream->inst, 16, 19)]; 4382 addr = cpu->Reg[BITS(inst_cream->inst, 16, 19)];
4604 fault = check_address_validity(cpu, addr, &phys_addr, 1);
4605 if (fault) goto MMU_EXCEPTION;
4606 unsigned int value;
4607 fault = interpreter_read_memory(addr, phys_addr, value, 32);
4608 if (fault) goto MMU_EXCEPTION;
4609 4383
4610 add_exclusive_addr(cpu, phys_addr); 4384 unsigned int value = Memory::Read32(addr);
4385
4386 add_exclusive_addr(cpu, addr);
4611 cpu->exclusive_state = 1; 4387 cpu->exclusive_state = 1;
4612 4388
4613 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; 4389 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
@@ -4626,13 +4402,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
4626 ldst_inst *inst_cream = (ldst_inst *)inst_base->component; 4402 ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
4627 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 4403 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
4628 addr = cpu->Reg[BITS(inst_cream->inst, 16, 19)]; 4404 addr = cpu->Reg[BITS(inst_cream->inst, 16, 19)];
4629 fault = check_address_validity(cpu, addr, &phys_addr, 1);
4630 if (fault) goto MMU_EXCEPTION;
4631 unsigned int value;
4632 fault = interpreter_read_memory(addr, phys_addr, value, 8);
4633 if (fault) goto MMU_EXCEPTION;
4634 4405
4635 add_exclusive_addr(cpu, phys_addr); 4406 unsigned int value = Memory::Read8(addr);
4407
4408 add_exclusive_addr(cpu, addr);
4636 cpu->exclusive_state = 1; 4409 cpu->exclusive_state = 1;
4637 4410
4638 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; 4411 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
@@ -4650,12 +4423,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
4650 { 4423 {
4651 ldst_inst *inst_cream = (ldst_inst *)inst_base->component; 4424 ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
4652 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 4425 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
4653 fault = inst_cream->get_addr(cpu, inst_cream->inst, addr, phys_addr, 1); 4426 inst_cream->get_addr(cpu, inst_cream->inst, addr, 1);
4654 if (fault) goto MMU_EXCEPTION; 4427 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = Memory::Read16(addr);
4655 unsigned int value = 0;
4656 fault = interpreter_read_memory(addr, phys_addr, value, 16);
4657 if (fault) goto MMU_EXCEPTION;
4658 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
4659 if (BITS(inst_cream->inst, 12, 15) == 15) { 4428 if (BITS(inst_cream->inst, 12, 15) == 15) {
4660 INC_PC(sizeof(ldst_inst)); 4429 INC_PC(sizeof(ldst_inst));
4661 goto DISPATCH; 4430 goto DISPATCH;
@@ -4670,11 +4439,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
4670 { 4439 {
4671 ldst_inst *inst_cream = (ldst_inst *)inst_base->component; 4440 ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
4672 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 4441 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
4673 fault = inst_cream->get_addr(cpu, inst_cream->inst, addr, phys_addr, 1); 4442 inst_cream->get_addr(cpu, inst_cream->inst, addr, 1);
4674 if (fault) goto MMU_EXCEPTION; 4443 unsigned int value = Memory::Read8(addr);
4675 unsigned int value;
4676 fault = interpreter_read_memory(addr, phys_addr, value, 8);
4677 if (fault) goto MMU_EXCEPTION;
4678 if (BIT(value, 7)) { 4444 if (BIT(value, 7)) {
4679 value |= 0xffffff00; 4445 value |= 0xffffff00;
4680 } 4446 }
@@ -4693,11 +4459,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
4693 { 4459 {
4694 ldst_inst *inst_cream = (ldst_inst *)inst_base->component; 4460 ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
4695 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 4461 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
4696 fault = inst_cream->get_addr(cpu, inst_cream->inst, addr, phys_addr, 1); 4462 inst_cream->get_addr(cpu, inst_cream->inst, addr, 1);
4697 if (fault) goto MMU_EXCEPTION; 4463 unsigned int value = Memory::Read16(addr);
4698 unsigned int value;
4699 fault = interpreter_read_memory(addr, phys_addr, value, 16);
4700 if (fault) goto MMU_EXCEPTION;
4701 if (BIT(value, 15)) { 4464 if (BIT(value, 15)) {
4702 value |= 0xffff0000; 4465 value |= 0xffff0000;
4703 } 4466 }
@@ -4716,11 +4479,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
4716 { 4479 {
4717 ldst_inst *inst_cream = (ldst_inst *)inst_base->component; 4480 ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
4718 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 4481 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
4719 fault = inst_cream->get_addr(cpu, inst_cream->inst, addr, phys_addr, 1); 4482 inst_cream->get_addr(cpu, inst_cream->inst, addr, 1);
4720 if (fault) goto MMU_EXCEPTION; 4483 unsigned int value = Memory::Read32(addr);
4721 unsigned int value;
4722 fault = interpreter_read_memory(addr, phys_addr, value, 32);
4723 if (fault) goto MMU_EXCEPTION;
4724 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; 4484 cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value;
4725 4485
4726 if (BIT(CP15_REG(CP15_CONTROL), 22) == 1) 4486 if (BIT(CP15_REG(CP15_CONTROL), 22) == 1)
@@ -5666,78 +5426,49 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
5666 unsigned int Rn = BITS(inst, 16, 19); 5426 unsigned int Rn = BITS(inst, 16, 19);
5667 unsigned int old_RN = cpu->Reg[Rn]; 5427 unsigned int old_RN = cpu->Reg[Rn];
5668 5428
5669 fault = inst_cream->get_addr(cpu, inst_cream->inst, addr, phys_addr, 0); 5429 inst_cream->get_addr(cpu, inst_cream->inst, addr, 0);
5670 if (fault) goto MMU_EXCEPTION;
5671 if (BIT(inst_cream->inst, 22) == 1) { 5430 if (BIT(inst_cream->inst, 22) == 1) {
5672 for (i = 0; i < 13; i++) { 5431 for (i = 0; i < 13; i++) {
5673 if(BIT(inst_cream->inst, i)){ 5432 if(BIT(inst_cream->inst, i)) {
5674 fault = check_address_validity(cpu, addr, &phys_addr, 0); 5433 Memory::Write32(addr, cpu->Reg[i]);
5675 if (fault) goto MMU_EXCEPTION;
5676 fault = interpreter_write_memory(addr, phys_addr, cpu->Reg[i], 32);
5677 if (fault) goto MMU_EXCEPTION;
5678 addr += 4; 5434 addr += 4;
5679 phys_addr += 4;
5680 } 5435 }
5681 } 5436 }
5682 if (BIT(inst_cream->inst, 13)) { 5437 if (BIT(inst_cream->inst, 13)) {
5683 if (cpu->Mode == USER32MODE) { 5438 if (cpu->Mode == USER32MODE) {
5684 fault = check_address_validity(cpu, addr, &phys_addr, 0); 5439 Memory::Write32(addr, cpu->Reg[i]);
5685 if (fault) goto MMU_EXCEPTION;
5686 fault = interpreter_write_memory(addr, phys_addr, cpu->Reg[i], 32);
5687 if (fault) goto MMU_EXCEPTION;
5688 addr += 4; 5440 addr += 4;
5689 phys_addr += 4;
5690 } else { 5441 } else {
5691 fault = interpreter_write_memory(addr, phys_addr, cpu->Reg_usr[0], 32); 5442 Memory::Write32(addr, cpu->Reg_usr[0]);
5692 if (fault) goto MMU_EXCEPTION;
5693 addr += 4; 5443 addr += 4;
5694 phys_addr += 4;
5695 } 5444 }
5696 } 5445 }
5697 if (BIT(inst_cream->inst, 14)) { 5446 if (BIT(inst_cream->inst, 14)) {
5698 if (cpu->Mode == USER32MODE) { 5447 if (cpu->Mode == USER32MODE) {
5699 fault = check_address_validity(cpu, addr, &phys_addr, 0); 5448 Memory::Write32(addr, cpu->Reg[i]);
5700 if (fault) goto MMU_EXCEPTION;
5701 fault = interpreter_write_memory(addr, phys_addr, cpu->Reg[i], 32);
5702 if (fault) goto MMU_EXCEPTION;
5703 addr += 4; 5449 addr += 4;
5704 phys_addr += 4;
5705 } else { 5450 } else {
5706 fault = check_address_validity(cpu, addr, &phys_addr, 0); 5451 Memory::Write32(addr, cpu->Reg_usr[1]);
5707 if (fault) goto MMU_EXCEPTION;
5708 fault = interpreter_write_memory(addr, phys_addr, cpu->Reg_usr[1], 32);
5709 if (fault) goto MMU_EXCEPTION;
5710 addr += 4; 5452 addr += 4;
5711 phys_addr += 4;
5712 } 5453 }
5713 } 5454 }
5714 if (BIT(inst_cream->inst, 15)) { 5455 if (BIT(inst_cream->inst, 15)) {
5715 fault = check_address_validity(cpu, addr, &phys_addr, 0); 5456 Memory::Write32(addr, cpu->Reg_usr[1] + 8);
5716 if (fault) goto MMU_EXCEPTION;
5717 fault = interpreter_write_memory(addr, phys_addr, cpu->Reg[i] + 8, 32);
5718 if (fault) goto MMU_EXCEPTION;
5719 } 5457 }
5720 } else { 5458 } else {
5721 for( i = 0; i < 15; i ++ ) { 5459 for( i = 0; i < 15; i++ ) {
5722 if(BIT(inst_cream->inst, i)) { 5460 if(BIT(inst_cream->inst, i)) {
5723 fault = check_address_validity(cpu, addr, &phys_addr, 0);
5724 if (fault) goto MMU_EXCEPTION;
5725 if(i == Rn) 5461 if(i == Rn)
5726 fault = interpreter_write_memory(addr, phys_addr, old_RN, 32); 5462 Memory::Write32(addr, old_RN);
5727 else 5463 else
5728 fault = interpreter_write_memory(addr, phys_addr, cpu->Reg[i], 32); 5464 Memory::Write32(addr, cpu->Reg[i]);
5729 if (fault) goto MMU_EXCEPTION;
5730 addr += 4; 5465 addr += 4;
5731 phys_addr += 4;
5732 } 5466 }
5733 } 5467 }
5734 5468
5735 // Check PC reg 5469 // Check PC reg
5736 if(BIT(inst_cream->inst, i)) { 5470 if(BIT(inst_cream->inst, i)) {
5737 fault = check_address_validity(cpu, addr, &phys_addr, 0); 5471 Memory::Write32(addr, cpu->Reg_usr[1] + 8);
5738 if (fault) goto MMU_EXCEPTION;
5739 fault = interpreter_write_memory(addr, phys_addr, cpu->Reg[i] + 8, 32);
5740 if (fault) goto MMU_EXCEPTION;
5741 } 5472 }
5742 } 5473 }
5743 } 5474 }
@@ -5770,11 +5501,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
5770 { 5501 {
5771 ldst_inst *inst_cream = (ldst_inst *)inst_base->component; 5502 ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
5772 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 5503 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
5773 fault = inst_cream->get_addr(cpu, inst_cream->inst, addr, phys_addr, 0); 5504 inst_cream->get_addr(cpu, inst_cream->inst, addr, 0);
5774 if (fault) goto MMU_EXCEPTION;
5775 unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)]; 5505 unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)];
5776 fault = interpreter_write_memory(addr, phys_addr, value, 32); 5506 Memory::Write32(addr, value);
5777 if (fault) goto MMU_EXCEPTION;
5778 } 5507 }
5779 cpu->Reg[15] += GET_INST_SIZE(cpu); 5508 cpu->Reg[15] += GET_INST_SIZE(cpu);
5780 INC_PC(sizeof(ldst_inst)); 5509 INC_PC(sizeof(ldst_inst));
@@ -5811,11 +5540,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
5811 { 5540 {
5812 ldst_inst *inst_cream = (ldst_inst *)inst_base->component; 5541 ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
5813 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 5542 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
5814 fault = inst_cream->get_addr(cpu, inst_cream->inst, addr, phys_addr, 0); 5543 inst_cream->get_addr(cpu, inst_cream->inst, addr, 0);
5815 if (fault) goto MMU_EXCEPTION;
5816 unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xff; 5544 unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xff;
5817 fault = interpreter_write_memory(addr, phys_addr, value, 8); 5545 Memory::Write8(addr, value);
5818 if (fault) goto MMU_EXCEPTION;
5819 } 5546 }
5820 cpu->Reg[15] += GET_INST_SIZE(cpu); 5547 cpu->Reg[15] += GET_INST_SIZE(cpu);
5821 INC_PC(sizeof(ldst_inst)); 5548 INC_PC(sizeof(ldst_inst));
@@ -5826,11 +5553,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
5826 { 5553 {
5827 ldst_inst *inst_cream = (ldst_inst *)inst_base->component; 5554 ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
5828 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 5555 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
5829 fault = inst_cream->get_addr(cpu, inst_cream->inst, addr, phys_addr, 0); 5556 inst_cream->get_addr(cpu, inst_cream->inst, addr, 0);
5830 if (fault) goto MMU_EXCEPTION;
5831 unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xff; 5557 unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xff;
5832 fault = interpreter_write_memory(addr, phys_addr, value, 8); 5558 Memory::Write8(addr, value);
5833 if (fault) goto MMU_EXCEPTION;
5834 } 5559 }
5835 cpu->Reg[15] += GET_INST_SIZE(cpu); 5560 cpu->Reg[15] += GET_INST_SIZE(cpu);
5836 INC_PC(sizeof(ldst_inst)); 5561 INC_PC(sizeof(ldst_inst));
@@ -5841,22 +5566,12 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
5841 { 5566 {
5842 ldst_inst *inst_cream = (ldst_inst *)inst_base->component; 5567 ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
5843 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 5568 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
5844 fault = inst_cream->get_addr(cpu, inst_cream->inst, addr, phys_addr, 0); 5569 inst_cream->get_addr(cpu, inst_cream->inst, addr, 0);
5845 if (fault) goto MMU_EXCEPTION;
5846 uint32_t rear_phys_addr;
5847 fault = check_address_validity(cpu, addr + 4, &rear_phys_addr, 0);
5848 if (fault){
5849 LOG_ERROR(Core_ARM11, "MMU fault , should rollback the above get_addr");
5850 CITRA_IGNORE_EXIT(-1);
5851 goto MMU_EXCEPTION;
5852 }
5853 5570
5854 unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)]; 5571 unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)];
5855 fault = interpreter_write_memory(addr, phys_addr, value, 32); 5572 Memory::Write32(addr, value);
5856 if (fault) goto MMU_EXCEPTION;
5857 value = cpu->Reg[BITS(inst_cream->inst, 12, 15) + 1]; 5573 value = cpu->Reg[BITS(inst_cream->inst, 12, 15) + 1];
5858 fault = interpreter_write_memory(addr + 4, rear_phys_addr, value, 32); 5574 Memory::Write32(addr + 4, value);
5859 if (fault) goto MMU_EXCEPTION;
5860 } 5575 }
5861 cpu->Reg[15] += GET_INST_SIZE(cpu); 5576 cpu->Reg[15] += GET_INST_SIZE(cpu);
5862 INC_PC(sizeof(ldst_inst)); 5577 INC_PC(sizeof(ldst_inst));
@@ -5869,17 +5584,14 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
5869 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 5584 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
5870 addr = cpu->Reg[BITS(inst_cream->inst, 16, 19)]; 5585 addr = cpu->Reg[BITS(inst_cream->inst, 16, 19)];
5871 unsigned int value = cpu->Reg[BITS(inst_cream->inst, 0, 3)]; 5586 unsigned int value = cpu->Reg[BITS(inst_cream->inst, 0, 3)];
5872 fault = check_address_validity(cpu, addr, &phys_addr, 0);
5873 if (fault) goto MMU_EXCEPTION;
5874 5587
5875 int dest_reg = BITS(inst_cream->inst, 12, 15); 5588 int dest_reg = BITS(inst_cream->inst, 12, 15);
5876 if((exclusive_detect(cpu, phys_addr) == 0) && (cpu->exclusive_state == 1)){ 5589 if((exclusive_detect(cpu, addr) == 0) && (cpu->exclusive_state == 1)){
5877 remove_exclusive(cpu, phys_addr); 5590 remove_exclusive(cpu, addr);
5878 cpu->Reg[dest_reg] = 0; 5591 cpu->Reg[dest_reg] = 0;
5879 cpu->exclusive_state = 0; 5592 cpu->exclusive_state = 0;
5880 5593
5881 fault = interpreter_write_memory(addr, phys_addr, value, 32); 5594 Memory::Write32(addr, value);
5882 if (fault) goto MMU_EXCEPTION;
5883 } else { 5595 } else {
5884 // Failed to write due to mutex access 5596 // Failed to write due to mutex access
5885 cpu->Reg[dest_reg] = 1; 5597 cpu->Reg[dest_reg] = 1;
@@ -5896,15 +5608,12 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
5896 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 5608 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
5897 addr = cpu->Reg[BITS(inst_cream->inst, 16, 19)]; 5609 addr = cpu->Reg[BITS(inst_cream->inst, 16, 19)];
5898 unsigned int value = cpu->Reg[BITS(inst_cream->inst, 0, 3)] & 0xff; 5610 unsigned int value = cpu->Reg[BITS(inst_cream->inst, 0, 3)] & 0xff;
5899 fault = check_address_validity(cpu, addr, &phys_addr, 0);
5900 if (fault) goto MMU_EXCEPTION;
5901 int dest_reg = BITS(inst_cream->inst, 12, 15); 5611 int dest_reg = BITS(inst_cream->inst, 12, 15);
5902 if((exclusive_detect(cpu, phys_addr) == 0) && (cpu->exclusive_state == 1)){ 5612 if((exclusive_detect(cpu, addr) == 0) && (cpu->exclusive_state == 1)){
5903 remove_exclusive(cpu, phys_addr); 5613 remove_exclusive(cpu, addr);
5904 cpu->Reg[dest_reg] = 0; 5614 cpu->Reg[dest_reg] = 0;
5905 cpu->exclusive_state = 0; 5615 cpu->exclusive_state = 0;
5906 fault = interpreter_write_memory(addr, phys_addr, value, 8); 5616 Memory::Write8(addr, value);
5907 if (fault) goto MMU_EXCEPTION;
5908 } else { 5617 } else {
5909 cpu->Reg[dest_reg] = 1; 5618 cpu->Reg[dest_reg] = 1;
5910 } 5619 }
@@ -5918,11 +5627,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
5918 { 5627 {
5919 ldst_inst *inst_cream = (ldst_inst *)inst_base->component; 5628 ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
5920 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 5629 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
5921 fault = inst_cream->get_addr(cpu, inst_cream->inst, addr, phys_addr, 0); 5630 inst_cream->get_addr(cpu, inst_cream->inst, addr, 0);
5922 if (fault) goto MMU_EXCEPTION;
5923 unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xffff; 5631 unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)] & 0xffff;
5924 fault = interpreter_write_memory(addr, phys_addr, value, 16); 5632 Memory::Write16(addr, value);
5925 if (fault) goto MMU_EXCEPTION;
5926 } 5633 }
5927 cpu->Reg[15] += GET_INST_SIZE(cpu); 5634 cpu->Reg[15] += GET_INST_SIZE(cpu);
5928 INC_PC(sizeof(ldst_inst)); 5635 INC_PC(sizeof(ldst_inst));
@@ -5933,11 +5640,9 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
5933 { 5640 {
5934 ldst_inst *inst_cream = (ldst_inst *)inst_base->component; 5641 ldst_inst *inst_cream = (ldst_inst *)inst_base->component;
5935 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 5642 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
5936 fault = inst_cream->get_addr(cpu, inst_cream->inst, addr, phys_addr, 0); 5643 inst_cream->get_addr(cpu, inst_cream->inst, addr, 0);
5937 if (fault) goto MMU_EXCEPTION;
5938 unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)]; 5644 unsigned int value = cpu->Reg[BITS(inst_cream->inst, 12, 15)];
5939 fault = interpreter_write_memory(addr, phys_addr, value, 32); 5645 Memory::Write32(addr, value);
5940 if (fault) goto MMU_EXCEPTION;
5941 } 5646 }
5942 cpu->Reg[15] += GET_INST_SIZE(cpu); 5647 cpu->Reg[15] += GET_INST_SIZE(cpu);
5943 INC_PC(sizeof(ldst_inst)); 5648 INC_PC(sizeof(ldst_inst));
@@ -5993,15 +5698,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
5993 swp_inst *inst_cream = (swp_inst *)inst_base->component; 5698 swp_inst *inst_cream = (swp_inst *)inst_base->component;
5994 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 5699 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
5995 addr = RN; 5700 addr = RN;
5996 fault = check_address_validity(cpu, addr, &phys_addr, 1);
5997 if (fault) goto MMU_EXCEPTION;
5998 unsigned int value; 5701 unsigned int value;
5999 fault = interpreter_read_memory(addr, phys_addr, value, 32); 5702 value = Memory::Read32(addr);
6000 if (fault) goto MMU_EXCEPTION; 5703 Memory::Write32(addr, RM);
6001 fault = interpreter_write_memory(addr, phys_addr, RM, 32);
6002 if (fault) goto MMU_EXCEPTION;
6003 5704
6004 assert((phys_addr & 0x3) == 0);
6005 RD = value; 5705 RD = value;
6006 } 5706 }
6007 cpu->Reg[15] += GET_INST_SIZE(cpu); 5707 cpu->Reg[15] += GET_INST_SIZE(cpu);
@@ -6014,13 +5714,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
6014 swp_inst *inst_cream = (swp_inst *)inst_base->component; 5714 swp_inst *inst_cream = (swp_inst *)inst_base->component;
6015 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 5715 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
6016 addr = RN; 5716 addr = RN;
6017 fault = check_address_validity(cpu, addr, &phys_addr, 1); 5717 unsigned int value = Memory::Read8(addr);
6018 if (fault) goto MMU_EXCEPTION; 5718 Memory::Write8(addr, (RM & 0xFF));
6019 unsigned int value;
6020 fault = interpreter_read_memory(addr, phys_addr, value, 8);
6021 if (fault) goto MMU_EXCEPTION;
6022 fault = interpreter_write_memory(addr, phys_addr, (RM & 0xFF), 8);
6023 if (fault) goto MMU_EXCEPTION;
6024 } 5719 }
6025 cpu->Reg[15] += GET_INST_SIZE(cpu); 5720 cpu->Reg[15] += GET_INST_SIZE(cpu);
6026 INC_PC(sizeof(swp_inst)); 5721 INC_PC(sizeof(swp_inst));
@@ -6650,17 +6345,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
6650 #define VFP_INTERPRETER_IMPL 6345 #define VFP_INTERPRETER_IMPL
6651 #include "core/arm/skyeye_common/vfp/vfpinstr.cpp" 6346 #include "core/arm/skyeye_common/vfp/vfpinstr.cpp"
6652 #undef VFP_INTERPRETER_IMPL 6347 #undef VFP_INTERPRETER_IMPL
6653 MMU_EXCEPTION: 6348
6654 {
6655 SAVE_NZCVT;
6656 cpu->abortSig = true;
6657 cpu->Aborted = ARMul_DataAbortV;
6658 cpu->AbortAddr = addr;
6659 cpu->CP15[CP15(CP15_FAULT_STATUS)] = fault & 0xff;
6660 cpu->CP15[CP15(CP15_FAULT_ADDRESS)] = addr;
6661 cpu->NumInstrsToExecute = 0;
6662 return num_instrs;
6663 }
6664 END: 6349 END:
6665 { 6350 {
6666 SAVE_NZCVT; 6351 SAVE_NZCVT;
diff --git a/src/core/arm/skyeye_common/vfp/vfpdouble.cpp b/src/core/arm/skyeye_common/vfp/vfpdouble.cpp
index 765c1f6bc..a9df490ba 100644
--- a/src/core/arm/skyeye_common/vfp/vfpdouble.cpp
+++ b/src/core/arm/skyeye_common/vfp/vfpdouble.cpp
@@ -1064,7 +1064,7 @@ vfp_double_multiply(struct vfp_double *vdd, struct vfp_double *vdn,
1064#define NEG_SUBTRACT (1 << 1) 1064#define NEG_SUBTRACT (1 << 1)
1065 1065
1066static u32 1066static u32
1067vfp_double_multiply_accumulate(ARMul_State* state, int dd, int dn, int dm, u32 fpscr, u32 negate, char *func) 1067vfp_double_multiply_accumulate(ARMul_State* state, int dd, int dn, int dm, u32 fpscr, u32 negate, const char *func)
1068{ 1068{
1069 struct vfp_double vdd, vdp, vdn, vdm; 1069 struct vfp_double vdd, vdp, vdn, vdm;
1070 u32 exceptions; 1070 u32 exceptions;
diff --git a/src/core/arm/skyeye_common/vfp/vfpinstr.cpp b/src/core/arm/skyeye_common/vfp/vfpinstr.cpp
index cc70fc33c..b5fcbac86 100644
--- a/src/core/arm/skyeye_common/vfp/vfpinstr.cpp
+++ b/src/core/arm/skyeye_common/vfp/vfpinstr.cpp
@@ -2891,32 +2891,15 @@ VSTR_INST:
2891 2891
2892 unsigned int base = (inst_cream->n == 15 ? (cpu->Reg[inst_cream->n] & 0xFFFFFFFC) + 8 : cpu->Reg[inst_cream->n]); 2892 unsigned int base = (inst_cream->n == 15 ? (cpu->Reg[inst_cream->n] & 0xFFFFFFFC) + 8 : cpu->Reg[inst_cream->n]);
2893 addr = (inst_cream->add ? base + inst_cream->imm32 : base - inst_cream->imm32); 2893 addr = (inst_cream->add ? base + inst_cream->imm32 : base - inst_cream->imm32);
2894 DBG("VSTR :\n"); 2894
2895
2896
2897 if (inst_cream->single) 2895 if (inst_cream->single)
2898 { 2896 {
2899 fault = check_address_validity(cpu, addr, &phys_addr, 0); 2897 Memory::Write32(addr, cpu->ExtReg[inst_cream->d]);
2900 if (fault) goto MMU_EXCEPTION;
2901 fault = interpreter_write_memory(addr, phys_addr, cpu->ExtReg[inst_cream->d], 32);
2902 if (fault) goto MMU_EXCEPTION;
2903 DBG("\taddr[%x] <= s%d=[%x]\n", addr, inst_cream->d, cpu->ExtReg[inst_cream->d]);
2904 } 2898 }
2905 else 2899 else
2906 { 2900 {
2907 fault = check_address_validity(cpu, addr, &phys_addr, 0); 2901 Memory::Write32(addr, cpu->ExtReg[inst_cream->d*2]);
2908 if (fault) goto MMU_EXCEPTION; 2902 Memory::Write32(addr + 4, cpu->ExtReg[inst_cream->d*2+1]);
2909
2910 /* Check endianness */
2911 fault = interpreter_write_memory(addr, phys_addr, cpu->ExtReg[inst_cream->d*2], 32);
2912 if (fault) goto MMU_EXCEPTION;
2913
2914 fault = check_address_validity(cpu, addr + 4, &phys_addr, 0);
2915 if (fault) goto MMU_EXCEPTION;
2916
2917 fault = interpreter_write_memory(addr + 4, phys_addr, cpu->ExtReg[inst_cream->d*2+1], 32);
2918 if (fault) goto MMU_EXCEPTION;
2919 DBG("\taddr[%x-%x] <= s[%d-%d]=[%x-%x]\n", addr+4, addr, inst_cream->d*2+1, inst_cream->d*2, cpu->ExtReg[inst_cream->d*2+1], cpu->ExtReg[inst_cream->d*2]);
2920 } 2903 }
2921 } 2904 }
2922 cpu->Reg[15] += GET_INST_SIZE(cpu); 2905 cpu->Reg[15] += GET_INST_SIZE(cpu);
@@ -3027,47 +3010,27 @@ VPUSH_INST:
3027{ 3010{
3028 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 3011 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
3029 CHECK_VFP_ENABLED; 3012 CHECK_VFP_ENABLED;
3030
3031 int i; 3013 int i;
3032 3014
3033 vpush_inst *inst_cream = (vpush_inst *)inst_base->component; 3015 vpush_inst *inst_cream = (vpush_inst *)inst_base->component;
3034 3016
3035 DBG("VPUSH :\n");
3036
3037 addr = cpu->Reg[R13] - inst_cream->imm32; 3017 addr = cpu->Reg[R13] - inst_cream->imm32;
3038 3018
3039
3040 for (i = 0; i < inst_cream->regs; i++) 3019 for (i = 0; i < inst_cream->regs; i++)
3041 { 3020 {
3042 if (inst_cream->single) 3021 if (inst_cream->single)
3043 { 3022 {
3044 fault = check_address_validity(cpu, addr, &phys_addr, 0); 3023 Memory::Write32(addr, cpu->ExtReg[inst_cream->d+i]);
3045 if (fault) goto MMU_EXCEPTION;
3046 fault = interpreter_write_memory(addr, phys_addr, cpu->ExtReg[inst_cream->d+i], 32);
3047 if (fault) goto MMU_EXCEPTION;
3048 DBG("\taddr[%x] <= s%d=[%x]\n", addr, inst_cream->d+i, cpu->ExtReg[inst_cream->d+i]);
3049 addr += 4; 3024 addr += 4;
3050 } 3025 }
3051 else 3026 else
3052 { 3027 {
3053 /* Careful of endianness, little by default */ 3028 Memory::Write32(addr, cpu->ExtReg[(inst_cream->d+i)*2]);
3054 fault = check_address_validity(cpu, addr, &phys_addr, 0); 3029 Memory::Write32(addr + 4, cpu->ExtReg[(inst_cream->d+i)*2 + 1]);
3055 if (fault) goto MMU_EXCEPTION;
3056 fault = interpreter_write_memory(addr, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2], 32);
3057 if (fault) goto MMU_EXCEPTION;
3058
3059 fault = check_address_validity(cpu, addr + 4, &phys_addr, 0);
3060 if (fault) goto MMU_EXCEPTION;
3061 fault = interpreter_write_memory(addr + 4, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2 + 1], 32);
3062 if (fault) goto MMU_EXCEPTION;
3063 DBG("\taddr[%x-%x] <= s[%d-%d]=[%x-%x]\n", addr+4, addr, (inst_cream->d+i)*2+1, (inst_cream->d+i)*2, cpu->ExtReg[(inst_cream->d+i)*2+1], cpu->ExtReg[(inst_cream->d+i)*2]);
3064 addr += 8; 3030 addr += 8;
3065 } 3031 }
3066 } 3032 }
3067 DBG("\tsp[%x]", cpu->Reg[R13]);
3068 cpu->Reg[R13] = cpu->Reg[R13] - inst_cream->imm32; 3033 cpu->Reg[R13] = cpu->Reg[R13] - inst_cream->imm32;
3069 DBG("=>[%x]\n", cpu->Reg[R13]);
3070
3071 } 3034 }
3072 cpu->Reg[15] += GET_INST_SIZE(cpu); 3035 cpu->Reg[15] += GET_INST_SIZE(cpu);
3073 INC_PC(sizeof(vpush_inst)); 3036 INC_PC(sizeof(vpush_inst));
@@ -3110,7 +3073,7 @@ int DYNCOM_TRANS(vpush)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
3110 { 3073 {
3111 if (single) 3074 if (single)
3112 { 3075 {
3113 //fault = interpreter_write_memory(addr, phys_addr, cpu->ExtReg[inst_cream->d+i], 32); 3076 //Memory::Write32(addr, cpu->ExtReg[inst_cream->d+i]);
3114 #if 0 3077 #if 0
3115 phys_addr = get_phys_addr(cpu, bb, Addr, 0); 3078 phys_addr = get_phys_addr(cpu, bb, Addr, 0);
3116 bb = cpu->dyncom_engine->bb; 3079 bb = cpu->dyncom_engine->bb;
@@ -3199,43 +3162,24 @@ VSTM_INST: /* encoding 1 */
3199 vstm_inst *inst_cream = (vstm_inst *)inst_base->component; 3162 vstm_inst *inst_cream = (vstm_inst *)inst_base->component;
3200 3163
3201 addr = (inst_cream->add ? cpu->Reg[inst_cream->n] : cpu->Reg[inst_cream->n] - inst_cream->imm32); 3164 addr = (inst_cream->add ? cpu->Reg[inst_cream->n] : cpu->Reg[inst_cream->n] - inst_cream->imm32);
3202 DBG("VSTM : addr[%x]\n", addr); 3165
3203
3204
3205 for (i = 0; i < inst_cream->regs; i++) 3166 for (i = 0; i < inst_cream->regs; i++)
3206 { 3167 {
3207 if (inst_cream->single) 3168 if (inst_cream->single)
3208 { 3169 {
3209 fault = check_address_validity(cpu, addr, &phys_addr, 0); 3170 Memory::Write32(addr, cpu->ExtReg[inst_cream->d+i]);
3210 if (fault) goto MMU_EXCEPTION;
3211
3212 fault = interpreter_write_memory(addr, phys_addr, cpu->ExtReg[inst_cream->d+i], 32);
3213 if (fault) goto MMU_EXCEPTION;
3214 DBG("\taddr[%x] <= s%d=[%x]\n", addr, inst_cream->d+i, cpu->ExtReg[inst_cream->d+i]);
3215 addr += 4; 3171 addr += 4;
3216 } 3172 }
3217 else 3173 else
3218 { 3174 {
3219 /* Careful of endianness, little by default */ 3175 Memory::Write32(addr, cpu->ExtReg[(inst_cream->d+i)*2]);
3220 fault = check_address_validity(cpu, addr, &phys_addr, 0); 3176 Memory::Write32(addr + 4, cpu->ExtReg[(inst_cream->d+i)*2 + 1]);
3221 if (fault) goto MMU_EXCEPTION;
3222
3223 fault = interpreter_write_memory(addr, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2], 32);
3224 if (fault) goto MMU_EXCEPTION;
3225
3226 fault = check_address_validity(cpu, addr + 4, &phys_addr, 0);
3227 if (fault) goto MMU_EXCEPTION;
3228
3229 fault = interpreter_write_memory(addr + 4, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2 + 1], 32);
3230 if (fault) goto MMU_EXCEPTION;
3231 DBG("\taddr[%x-%x] <= s[%d-%d]=[%x-%x]\n", addr+4, addr, (inst_cream->d+i)*2+1, (inst_cream->d+i)*2, cpu->ExtReg[(inst_cream->d+i)*2+1], cpu->ExtReg[(inst_cream->d+i)*2]);
3232 addr += 8; 3177 addr += 8;
3233 } 3178 }
3234 } 3179 }
3235 if (inst_cream->wback){ 3180 if (inst_cream->wback){
3236 cpu->Reg[inst_cream->n] = (inst_cream->add ? cpu->Reg[inst_cream->n] + inst_cream->imm32 : 3181 cpu->Reg[inst_cream->n] = (inst_cream->add ? cpu->Reg[inst_cream->n] + inst_cream->imm32 :
3237 cpu->Reg[inst_cream->n] - inst_cream->imm32); 3182 cpu->Reg[inst_cream->n] - inst_cream->imm32);
3238 DBG("\twback r%d[%x]\n", inst_cream->n, cpu->Reg[inst_cream->n]);
3239 } 3183 }
3240 3184
3241 } 3185 }
@@ -3290,7 +3234,7 @@ int DYNCOM_TRANS(vstm)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
3290 if (single) 3234 if (single)
3291 { 3235 {
3292 3236
3293 //fault = interpreter_write_memory(addr, phys_addr, cpu->ExtReg[inst_cream->d+i], 32); 3237 //Memory::Write32(addr, cpu->ExtReg[inst_cream->d+i]);
3294 /* if R(i) is R15? */ 3238 /* if R(i) is R15? */
3295 #if 0 3239 #if 0
3296 phys_addr = get_phys_addr(cpu, bb, Addr, 0); 3240 phys_addr = get_phys_addr(cpu, bb, Addr, 0);
@@ -3300,14 +3244,13 @@ int DYNCOM_TRANS(vstm)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
3300 //memory_write(cpu, bb, Addr, RSPR(d + i), 32); 3244 //memory_write(cpu, bb, Addr, RSPR(d + i), 32);
3301 memory_write(cpu, bb, Addr, IBITCAST32(FR32(d + i)),32); 3245 memory_write(cpu, bb, Addr, IBITCAST32(FR32(d + i)),32);
3302 bb = cpu->dyncom_engine->bb; 3246 bb = cpu->dyncom_engine->bb;
3303 //if (fault) goto MMU_EXCEPTION;
3304 //DBG("\taddr[%x] <= s%d=[%x]\n", addr, inst_cream->d+i, cpu->ExtReg[inst_cream->d+i]); 3247 //DBG("\taddr[%x] <= s%d=[%x]\n", addr, inst_cream->d+i, cpu->ExtReg[inst_cream->d+i]);
3305 Addr = ADD(Addr, CONST(4)); 3248 Addr = ADD(Addr, CONST(4));
3306 } 3249 }
3307 else 3250 else
3308 { 3251 {
3309 3252
3310 //fault = interpreter_write_memory(addr, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2], 32); 3253 //Memory::Write32(addr, cpu->ExtReg[(inst_cream->d+i)*2]);
3311 #if 0 3254 #if 0
3312 phys_addr = get_phys_addr(cpu, bb, Addr, 0); 3255 phys_addr = get_phys_addr(cpu, bb, Addr, 0);
3313 bb = cpu->dyncom_engine->bb; 3256 bb = cpu->dyncom_engine->bb;
@@ -3316,9 +3259,8 @@ int DYNCOM_TRANS(vstm)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
3316 //memory_write(cpu, bb, Addr, RSPR((d + i) * 2), 32); 3259 //memory_write(cpu, bb, Addr, RSPR((d + i) * 2), 32);
3317 memory_write(cpu, bb, Addr, IBITCAST32(FR32((d + i) * 2)),32); 3260 memory_write(cpu, bb, Addr, IBITCAST32(FR32((d + i) * 2)),32);
3318 bb = cpu->dyncom_engine->bb; 3261 bb = cpu->dyncom_engine->bb;
3319 //if (fault) goto MMU_EXCEPTION;
3320 3262
3321 //fault = interpreter_write_memory(addr + 4, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2 + 1], 32); 3263 //Memory::Write32(addr + 4, cpu->ExtReg[(inst_cream->d+i)*2 + 1]);
3322 #if 0 3264 #if 0
3323 phys_addr = get_phys_addr(cpu, bb, ADD(Addr, CONST(4)), 0); 3265 phys_addr = get_phys_addr(cpu, bb, ADD(Addr, CONST(4)), 0);
3324 bb = cpu->dyncom_engine->bb; 3266 bb = cpu->dyncom_engine->bb;
@@ -3327,7 +3269,6 @@ int DYNCOM_TRANS(vstm)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
3327 //memory_write(cpu, bb, ADD(Addr, CONST(4)), RSPR((d + i) * 2 + 1), 32); 3269 //memory_write(cpu, bb, ADD(Addr, CONST(4)), RSPR((d + i) * 2 + 1), 32);
3328 memory_write(cpu, bb, ADD(Addr, CONST(4)), IBITCAST32(FR32((d + i) * 2 + 1)), 32); 3270 memory_write(cpu, bb, ADD(Addr, CONST(4)), IBITCAST32(FR32((d + i) * 2 + 1)), 32);
3329 bb = cpu->dyncom_engine->bb; 3271 bb = cpu->dyncom_engine->bb;
3330 //if (fault) goto MMU_EXCEPTION;
3331 //DBG("\taddr[%x-%x] <= s[%d-%d]=[%x-%x]\n", addr+4, addr, (inst_cream->d+i)*2+1, (inst_cream->d+i)*2, cpu->ExtReg[(inst_cream->d+i)*2+1], cpu->ExtReg[(inst_cream->d+i)*2]); 3272 //DBG("\taddr[%x-%x] <= s[%d-%d]=[%x-%x]\n", addr+4, addr, (inst_cream->d+i)*2+1, (inst_cream->d+i)*2, cpu->ExtReg[(inst_cream->d+i)*2+1], cpu->ExtReg[(inst_cream->d+i)*2]);
3332 //addr += 8; 3273 //addr += 8;
3333 Addr = ADD(Addr, CONST(8)); 3274 Addr = ADD(Addr, CONST(8));
@@ -3385,49 +3326,27 @@ VPOP_INST:
3385 unsigned int value1, value2; 3326 unsigned int value1, value2;
3386 3327
3387 vpop_inst *inst_cream = (vpop_inst *)inst_base->component; 3328 vpop_inst *inst_cream = (vpop_inst *)inst_base->component;
3388 3329
3389 DBG("VPOP :\n");
3390
3391 addr = cpu->Reg[R13]; 3330 addr = cpu->Reg[R13];
3392
3393 3331
3394 for (i = 0; i < inst_cream->regs; i++) 3332 for (i = 0; i < inst_cream->regs; i++)
3395 { 3333 {
3396 if (inst_cream->single) 3334 if (inst_cream->single)
3397 { 3335 {
3398 fault = check_address_validity(cpu, addr, &phys_addr, 1); 3336 value1 = Memory::Read32(addr);
3399 if (fault) goto MMU_EXCEPTION;
3400
3401 fault = interpreter_read_memory(addr, phys_addr, value1, 32);
3402 if (fault) goto MMU_EXCEPTION;
3403 DBG("\ts%d <= [%x] addr[%x]\n", inst_cream->d+i, value1, addr);
3404 cpu->ExtReg[inst_cream->d+i] = value1; 3337 cpu->ExtReg[inst_cream->d+i] = value1;
3405 addr += 4; 3338 addr += 4;
3406 } 3339 }
3407 else 3340 else
3408 { 3341 {
3409 /* Careful of endianness, little by default */ 3342 value1 = Memory::Read32(addr);
3410 fault = check_address_validity(cpu, addr, &phys_addr, 1); 3343 value2 = Memory::Read32(addr + 4);
3411 if (fault) goto MMU_EXCEPTION;
3412
3413 fault = interpreter_read_memory(addr, phys_addr, value1, 32);
3414 if (fault) goto MMU_EXCEPTION;
3415
3416 fault = check_address_validity(cpu, addr + 4, &phys_addr, 1);
3417 if (fault) goto MMU_EXCEPTION;
3418
3419 fault = interpreter_read_memory(addr + 4, phys_addr, value2, 32);
3420 if (fault) goto MMU_EXCEPTION;
3421 DBG("\ts[%d-%d] <= [%x-%x] addr[%x-%x]\n", (inst_cream->d+i)*2+1, (inst_cream->d+i)*2, value2, value1, addr+4, addr);
3422 cpu->ExtReg[(inst_cream->d+i)*2] = value1; 3344 cpu->ExtReg[(inst_cream->d+i)*2] = value1;
3423 cpu->ExtReg[(inst_cream->d+i)*2 + 1] = value2; 3345 cpu->ExtReg[(inst_cream->d+i)*2 + 1] = value2;
3424 addr += 8; 3346 addr += 8;
3425 } 3347 }
3426 } 3348 }
3427 DBG("\tsp[%x]", cpu->Reg[R13]);
3428 cpu->Reg[R13] = cpu->Reg[R13] + inst_cream->imm32; 3349 cpu->Reg[R13] = cpu->Reg[R13] + inst_cream->imm32;
3429 DBG("=>[%x]\n", cpu->Reg[R13]);
3430
3431 } 3350 }
3432 cpu->Reg[15] += GET_INST_SIZE(cpu); 3351 cpu->Reg[15] += GET_INST_SIZE(cpu);
3433 INC_PC(sizeof(vpop_inst)); 3352 INC_PC(sizeof(vpop_inst));
@@ -3565,33 +3484,19 @@ VLDR_INST:
3565 3484
3566 unsigned int base = (inst_cream->n == 15 ? (cpu->Reg[inst_cream->n] & 0xFFFFFFFC) + 8 : cpu->Reg[inst_cream->n]); 3485 unsigned int base = (inst_cream->n == 15 ? (cpu->Reg[inst_cream->n] & 0xFFFFFFFC) + 8 : cpu->Reg[inst_cream->n]);
3567 addr = (inst_cream->add ? base + inst_cream->imm32 : base - inst_cream->imm32); 3486 addr = (inst_cream->add ? base + inst_cream->imm32 : base - inst_cream->imm32);
3568 DBG("VLDR :\n", addr); 3487
3569
3570
3571 if (inst_cream->single) 3488 if (inst_cream->single)
3572 { 3489 {
3573 fault = check_address_validity(cpu, addr, &phys_addr, 1); 3490 cpu->ExtReg[inst_cream->d] = Memory::Read32(addr);
3574 if (fault) goto MMU_EXCEPTION;
3575 fault = interpreter_read_memory(addr, phys_addr, cpu->ExtReg[inst_cream->d], 32);
3576 if (fault) goto MMU_EXCEPTION;
3577 DBG("\ts%d <= [%x] addr[%x]\n", inst_cream->d, cpu->ExtReg[inst_cream->d], addr);
3578 } 3491 }
3579 else 3492 else
3580 { 3493 {
3581 unsigned int word1, word2; 3494 unsigned int word1, word2;
3582 fault = check_address_validity(cpu, addr, &phys_addr, 1); 3495 word1 = Memory::Read32(addr);
3583 if (fault) goto MMU_EXCEPTION; 3496 word2 = Memory::Read32(addr + 4);
3584 fault = interpreter_read_memory(addr, phys_addr, word1, 32); 3497
3585 if (fault) goto MMU_EXCEPTION;
3586
3587 fault = check_address_validity(cpu, addr + 4, &phys_addr, 1);
3588 if (fault) goto MMU_EXCEPTION;
3589 fault = interpreter_read_memory(addr + 4, phys_addr, word2, 32);
3590 if (fault) goto MMU_EXCEPTION;
3591 /* Check endianness */
3592 cpu->ExtReg[inst_cream->d*2] = word1; 3498 cpu->ExtReg[inst_cream->d*2] = word1;
3593 cpu->ExtReg[inst_cream->d*2+1] = word2; 3499 cpu->ExtReg[inst_cream->d*2+1] = word2;
3594 DBG("\ts[%d-%d] <= [%x-%x] addr[%x-%x]\n", inst_cream->d*2+1, inst_cream->d*2, word2, word1, addr+4, addr);
3595 } 3500 }
3596 } 3501 }
3597 cpu->Reg[15] += GET_INST_SIZE(cpu); 3502 cpu->Reg[15] += GET_INST_SIZE(cpu);
@@ -3729,32 +3634,18 @@ VLDM_INST:
3729 vldm_inst *inst_cream = (vldm_inst *)inst_base->component; 3634 vldm_inst *inst_cream = (vldm_inst *)inst_base->component;
3730 3635
3731 addr = (inst_cream->add ? cpu->Reg[inst_cream->n] : cpu->Reg[inst_cream->n] - inst_cream->imm32); 3636 addr = (inst_cream->add ? cpu->Reg[inst_cream->n] : cpu->Reg[inst_cream->n] - inst_cream->imm32);
3732 DBG("VLDM : addr[%x]\n", addr); 3637
3733
3734 for (i = 0; i < inst_cream->regs; i++) 3638 for (i = 0; i < inst_cream->regs; i++)
3735 { 3639 {
3736 if (inst_cream->single) 3640 if (inst_cream->single)
3737 { 3641 {
3738 fault = check_address_validity(cpu, addr, &phys_addr, 1); 3642 cpu->ExtReg[inst_cream->d+i] = Memory::Read32(addr);
3739 if (fault) goto MMU_EXCEPTION;
3740 fault = interpreter_read_memory(addr, phys_addr, cpu->ExtReg[inst_cream->d+i], 32);
3741 if (fault) goto MMU_EXCEPTION;
3742 DBG("\ts%d <= [%x] addr[%x]\n", inst_cream->d+i, cpu->ExtReg[inst_cream->d+i], addr);
3743 addr += 4; 3643 addr += 4;
3744 } 3644 }
3745 else 3645 else
3746 { 3646 {
3747 /* Careful of endianness, little by default */ 3647 cpu->ExtReg[(inst_cream->d+i)*2] = Memory::Read32(addr);
3748 fault = check_address_validity(cpu, addr, &phys_addr, 1); 3648 cpu->ExtReg[(inst_cream->d+i)*2 + 1] = Memory::Read32(addr + 4);
3749 if (fault) goto MMU_EXCEPTION;
3750 fault = interpreter_read_memory(addr, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2], 32);
3751 if (fault) goto MMU_EXCEPTION;
3752
3753 fault = check_address_validity(cpu, addr + 4, &phys_addr, 1);
3754 if (fault) goto MMU_EXCEPTION;
3755 fault = interpreter_read_memory(addr + 4, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2 + 1], 32);
3756 if (fault) goto MMU_EXCEPTION;
3757 DBG("\ts[%d-%d] <= [%x-%x] addr[%x-%x]\n", (inst_cream->d+i)*2+1, (inst_cream->d+i)*2, cpu->ExtReg[(inst_cream->d+i)*2+1], cpu->ExtReg[(inst_cream->d+i)*2], addr+4, addr);
3758 addr += 8; 3649 addr += 8;
3759 } 3650 }
3760 } 3651 }
@@ -3815,7 +3706,7 @@ int DYNCOM_TRANS(vldm)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
3815 if (single) 3706 if (single)
3816 { 3707 {
3817 3708
3818 //fault = interpreter_write_memory(addr, phys_addr, cpu->ExtReg[inst_cream->d+i], 32); 3709 //Memory::Write32(addr, cpu->ExtReg[inst_cream->d+i]);
3819 /* if R(i) is R15? */ 3710 /* if R(i) is R15? */
3820 #if 0 3711 #if 0
3821 phys_addr = get_phys_addr(cpu, bb, Addr, 1); 3712 phys_addr = get_phys_addr(cpu, bb, Addr, 1);
@@ -3827,7 +3718,6 @@ int DYNCOM_TRANS(vldm)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
3827 val = new LoadInst(cpu->dyncom_engine->read_value, "", false, bb); 3718 val = new LoadInst(cpu->dyncom_engine->read_value, "", false, bb);
3828 //LETS(d + i, val); 3719 //LETS(d + i, val);
3829 LETFPS(d + i, FPBITCAST32(val)); 3720 LETFPS(d + i, FPBITCAST32(val));
3830 //if (fault) goto MMU_EXCEPTION;
3831 //DBG("\taddr[%x] <= s%d=[%x]\n", addr, inst_cream->d+i, cpu->ExtReg[inst_cream->d+i]); 3721 //DBG("\taddr[%x] <= s%d=[%x]\n", addr, inst_cream->d+i, cpu->ExtReg[inst_cream->d+i]);
3832 Addr = ADD(Addr, CONST(4)); 3722 Addr = ADD(Addr, CONST(4));
3833 } 3723 }
@@ -3852,7 +3742,7 @@ int DYNCOM_TRANS(vldm)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
3852 val = new LoadInst(cpu->dyncom_engine->read_value, "", false, bb); 3742 val = new LoadInst(cpu->dyncom_engine->read_value, "", false, bb);
3853 LETFPS((d + i) * 2 + 1, FPBITCAST32(val)); 3743 LETFPS((d + i) * 2 + 1, FPBITCAST32(val));
3854 3744
3855 //fault = interpreter_write_memory(addr + 4, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2 + 1], 32); 3745 //Memory::Write(addr + 4, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2 + 1], 32);
3856 //DBG("\taddr[%x-%x] <= s[%d-%d]=[%x-%x]\n", addr+4, addr, (inst_cream->d+i)*2+1, (inst_cream->d+i)*2, cpu->ExtReg[(inst_cream->d+i)*2+1], cpu->ExtReg[(inst_cream->d+i)*2]); 3746 //DBG("\taddr[%x-%x] <= s[%d-%d]=[%x-%x]\n", addr+4, addr, (inst_cream->d+i)*2+1, (inst_cream->d+i)*2, cpu->ExtReg[(inst_cream->d+i)*2+1], cpu->ExtReg[(inst_cream->d+i)*2]);
3857 //addr += 8; 3747 //addr += 8;
3858 Addr = ADD(Addr, CONST(8)); 3748 Addr = ADD(Addr, CONST(8));
diff --git a/src/core/arm/skyeye_common/vfp/vfpsingle.cpp b/src/core/arm/skyeye_common/vfp/vfpsingle.cpp
index 6c33d8b78..08d0d719f 100644
--- a/src/core/arm/skyeye_common/vfp/vfpsingle.cpp
+++ b/src/core/arm/skyeye_common/vfp/vfpsingle.cpp
@@ -957,7 +957,7 @@ vfp_single_multiply(struct vfp_single *vsd, struct vfp_single *vsn, struct vfp_s
957#define NEG_SUBTRACT (1 << 1) 957#define NEG_SUBTRACT (1 << 1)
958 958
959static u32 959static u32
960vfp_single_multiply_accumulate(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr, u32 negate, char *func) 960vfp_single_multiply_accumulate(ARMul_State* state, int sd, int sn, s32 m, u32 fpscr, u32 negate, const char *func)
961{ 961{
962 962
963 { 963 {
HIC SVNT DRACONES