summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--src/citra_qt/debugger/callstack.cpp3
-rw-r--r--src/citra_qt/debugger/disassembler.cpp5
-rw-r--r--src/common/break_points.cpp4
-rw-r--r--src/common/break_points.h4
-rw-r--r--src/core/arm/dyncom/arm_dyncom_dec.cpp4
-rw-r--r--src/core/arm/dyncom/arm_dyncom_dec.h37
-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp205
-rw-r--r--src/core/arm/interpreter/armsupp.cpp431
-rw-r--r--src/core/arm/skyeye_common/arm_regformat.h90
-rw-r--r--src/core/arm/skyeye_common/armdefs.h4
-rw-r--r--src/core/hle/config_mem.cpp4
11 files changed, 597 insertions, 194 deletions
diff --git a/src/citra_qt/debugger/callstack.cpp b/src/citra_qt/debugger/callstack.cpp
index 9bb22ca2e..3742c2d38 100644
--- a/src/citra_qt/debugger/callstack.cpp
+++ b/src/citra_qt/debugger/callstack.cpp
@@ -27,7 +27,6 @@ CallstackWidget::CallstackWidget(QWidget* parent): QDockWidget(parent)
27 27
28void CallstackWidget::OnDebugModeEntered() 28void CallstackWidget::OnDebugModeEntered()
29{ 29{
30 ARM_Disasm* disasm = new ARM_Disasm();
31 ARM_Interface* app_core = Core::g_app_core; 30 ARM_Interface* app_core = Core::g_app_core;
32 31
33 u32 sp = app_core->GetReg(13); //stack pointer 32 u32 sp = app_core->GetReg(13); //stack pointer
@@ -46,7 +45,7 @@ void CallstackWidget::OnDebugModeEntered()
46 45
47 /* TODO (mattvail) clean me, move to debugger interface */ 46 /* TODO (mattvail) clean me, move to debugger interface */
48 u32 insn = Memory::Read32(call_addr); 47 u32 insn = Memory::Read32(call_addr);
49 if (disasm->Decode(insn) == OP_BL) 48 if (ARM_Disasm::Decode(insn) == OP_BL)
50 { 49 {
51 std::string name; 50 std::string name;
52 // ripped from disasm 51 // ripped from disasm
diff --git a/src/citra_qt/debugger/disassembler.cpp b/src/citra_qt/debugger/disassembler.cpp
index 54d21dc90..f620687ae 100644
--- a/src/citra_qt/debugger/disassembler.cpp
+++ b/src/citra_qt/debugger/disassembler.cpp
@@ -232,11 +232,8 @@ void DisassemblerWidget::OnDebugModeEntered()
232{ 232{
233 ARMword next_instr = Core::g_app_core->GetPC(); 233 ARMword next_instr = Core::g_app_core->GetPC();
234 234
235 // TODO: Make BreakPoints less crappy (i.e. const-correct) so that this doesn't need a const_cast. 235 if (model->GetBreakPoints().IsAddressBreakPoint(next_instr))
236 if (const_cast<BreakPoints&>(model->GetBreakPoints()).IsAddressBreakPoint(next_instr))
237 {
238 emu_thread.SetCpuRunning(false); 236 emu_thread.SetCpuRunning(false);
239 }
240 237
241 model->SetNextInstruction(next_instr); 238 model->SetNextInstruction(next_instr);
242 239
diff --git a/src/common/break_points.cpp b/src/common/break_points.cpp
index 2655d3ce9..15055bd4e 100644
--- a/src/common/break_points.cpp
+++ b/src/common/break_points.cpp
@@ -10,14 +10,14 @@
10#include <sstream> 10#include <sstream>
11#include <algorithm> 11#include <algorithm>
12 12
13bool BreakPoints::IsAddressBreakPoint(u32 iAddress) 13bool BreakPoints::IsAddressBreakPoint(u32 iAddress) const
14{ 14{
15 auto cond = [&iAddress](const TBreakPoint& bp) { return bp.iAddress == iAddress; }; 15 auto cond = [&iAddress](const TBreakPoint& bp) { return bp.iAddress == iAddress; };
16 auto it = std::find_if(m_BreakPoints.begin(), m_BreakPoints.end(), cond); 16 auto it = std::find_if(m_BreakPoints.begin(), m_BreakPoints.end(), cond);
17 return it != m_BreakPoints.end(); 17 return it != m_BreakPoints.end();
18} 18}
19 19
20bool BreakPoints::IsTempBreakPoint(u32 iAddress) 20bool BreakPoints::IsTempBreakPoint(u32 iAddress) const
21{ 21{
22 auto cond = [&iAddress](const TBreakPoint& bp) { return bp.iAddress == iAddress && bp.bTemporary; }; 22 auto cond = [&iAddress](const TBreakPoint& bp) { return bp.iAddress == iAddress && bp.bTemporary; };
23 auto it = std::find_if(m_BreakPoints.begin(), m_BreakPoints.end(), cond); 23 auto it = std::find_if(m_BreakPoints.begin(), m_BreakPoints.end(), cond);
diff --git a/src/common/break_points.h b/src/common/break_points.h
index 5557cd50e..4b26cf90d 100644
--- a/src/common/break_points.h
+++ b/src/common/break_points.h
@@ -56,8 +56,8 @@ public:
56 void AddFromStrings(const TBreakPointsStr& bps); 56 void AddFromStrings(const TBreakPointsStr& bps);
57 57
58 // is address breakpoint 58 // is address breakpoint
59 bool IsAddressBreakPoint(u32 iAddress); 59 bool IsAddressBreakPoint(u32 iAddress) const;
60 bool IsTempBreakPoint(u32 iAddress); 60 bool IsTempBreakPoint(u32 iAddress) const;
61 61
62 // Add BreakPoint 62 // Add BreakPoint
63 void Add(u32 em_address, bool temp=false); 63 void Add(u32 em_address, bool temp=false);
diff --git a/src/core/arm/dyncom/arm_dyncom_dec.cpp b/src/core/arm/dyncom/arm_dyncom_dec.cpp
index 9f3b90fd0..12181d0ec 100644
--- a/src/core/arm/dyncom/arm_dyncom_dec.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_dec.cpp
@@ -413,7 +413,7 @@ int decode_arm_instr(uint32_t instr, int32_t *idx) {
413 if (instr != arm_instruction[i].content[base + 2]) { 413 if (instr != arm_instruction[i].content[base + 2]) {
414 break; 414 break;
415 } 415 }
416 } else if (BITS(arm_instruction[i].content[base], arm_instruction[i].content[base + 1]) != arm_instruction[i].content[base + 2]) { 416 } else if (BITS(instr, arm_instruction[i].content[base], arm_instruction[i].content[base + 1]) != arm_instruction[i].content[base + 2]) {
417 break; 417 break;
418 } 418 }
419 base += 3; 419 base += 3;
@@ -429,7 +429,7 @@ int decode_arm_instr(uint32_t instr, int32_t *idx) {
429 if (n != 0) { 429 if (n != 0) {
430 base = 0; 430 base = 0;
431 while (n) { 431 while (n) {
432 if (BITS(arm_exclusion_code[i].content[base], arm_exclusion_code[i].content[base + 1]) != arm_exclusion_code[i].content[base + 2]) { 432 if (BITS(instr, arm_exclusion_code[i].content[base], arm_exclusion_code[i].content[base + 1]) != arm_exclusion_code[i].content[base + 2]) {
433 break; 433 break;
434 } 434 }
435 base += 3; 435 base += 3;
diff --git a/src/core/arm/dyncom/arm_dyncom_dec.h b/src/core/arm/dyncom/arm_dyncom_dec.h
index ee8ff5992..4b5f5ad7e 100644
--- a/src/core/arm/dyncom/arm_dyncom_dec.h
+++ b/src/core/arm/dyncom/arm_dyncom_dec.h
@@ -4,43 +4,6 @@
4 4
5#pragma once 5#pragma once
6 6
7#define BITS(a,b) ((instr >> (a)) & ((1 << (1+(b)-(a)))-1))
8#define BIT(n) ((instr >> (n)) & 1)
9
10// For MUL instructions
11#define RDHi ((instr >> 16) & 0xF)
12#define RDLo ((instr >> 12) & 0xF)
13#define MUL_RD ((instr >> 16) & 0xF)
14#define MUL_RN ((instr >> 12) & 0xF)
15#define RS ((instr >> 8) & 0xF)
16#define RD ((instr >> 12) & 0xF)
17#define RN ((instr >> 16) & 0xF)
18#define RM (instr & 0xF)
19
20// CP15 registers
21#define OPCODE_1 BITS(21, 23)
22#define CRn BITS(16, 19)
23#define CRm BITS(0, 3)
24#define OPCODE_2 BITS(5, 7)
25
26#define I BIT(25)
27#define S BIT(20)
28
29#define SHIFT BITS(5,6)
30#define SHIFT_IMM BITS(7,11)
31#define IMMH BITS(8,11)
32#define IMML BITS(0,3)
33
34#define LSPBIT BIT(24)
35#define LSUBIT BIT(23)
36#define LSBBIT BIT(22)
37#define LSWBIT BIT(21)
38#define LSLBIT BIT(20)
39#define LSSHBITS BITS(5,6)
40#define OFFSET12 BITS(0,11)
41#define SBIT BIT(20)
42#define DESTReg (BITS (12, 15))
43
44int decode_arm_instr(uint32_t instr, int32_t *idx); 7int decode_arm_instr(uint32_t instr, int32_t *idx);
45 8
46enum DECODE_STATUS { 9enum DECODE_STATUS {
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index cfa6de8fc..b0efd7194 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -2156,7 +2156,22 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(revsh)(unsigned int inst, int index)
2156 return INTERPRETER_TRANSLATE(rev)(inst, index); 2156 return INTERPRETER_TRANSLATE(rev)(inst, index);
2157} 2157}
2158 2158
2159static ARM_INST_PTR INTERPRETER_TRANSLATE(rfe)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("RFE"); } 2159static ARM_INST_PTR INTERPRETER_TRANSLATE(rfe)(unsigned int inst, int index)
2160{
2161 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
2162 ldst_inst* const inst_cream = (ldst_inst*)inst_base->component;
2163
2164 inst_base->cond = AL;
2165 inst_base->idx = index;
2166 inst_base->br = INDIRECT_BRANCH;
2167 inst_base->load_r15 = 0;
2168
2169 inst_cream->inst = inst;
2170 inst_cream->get_addr = get_calc_addr_op(inst);
2171
2172 return inst_base;
2173}
2174
2160static ARM_INST_PTR INTERPRETER_TRANSLATE(rsb)(unsigned int inst, int index) 2175static ARM_INST_PTR INTERPRETER_TRANSLATE(rsb)(unsigned int inst, int index)
2161{ 2176{
2162 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(rsb_inst)); 2177 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(rsb_inst));
@@ -2570,7 +2585,23 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(smulw)(unsigned int inst, int index)
2570 inst_base->load_r15 = 1; 2585 inst_base->load_r15 = 1;
2571 return inst_base; 2586 return inst_base;
2572} 2587}
2573static ARM_INST_PTR INTERPRETER_TRANSLATE(srs)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("SRS"); } 2588
2589static ARM_INST_PTR INTERPRETER_TRANSLATE(srs)(unsigned int inst, int index)
2590{
2591 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ldst_inst));
2592 ldst_inst* const inst_cream = (ldst_inst*)inst_base->component;
2593
2594 inst_base->cond = AL;
2595 inst_base->idx = index;
2596 inst_base->br = NON_BRANCH;
2597 inst_base->load_r15 = 0;
2598
2599 inst_cream->inst = inst;
2600 inst_cream->get_addr = get_calc_addr_op(inst);
2601
2602 return inst_base;
2603}
2604
2574static ARM_INST_PTR INTERPRETER_TRANSLATE(ssat)(unsigned int inst, int index) 2605static ARM_INST_PTR INTERPRETER_TRANSLATE(ssat)(unsigned int inst, int index)
2575{ 2606{
2576 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ssat_inst)); 2607 arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(ssat_inst));
@@ -3659,10 +3690,6 @@ static int clz(unsigned int x) {
3659 return n; 3690 return n;
3660} 3691}
3661 3692
3662static bool InAPrivilegedMode(ARMul_State* core) {
3663 return (core->Mode != USER32MODE);
3664}
3665
3666unsigned InterpreterMainLoop(ARMul_State* state) { 3693unsigned InterpreterMainLoop(ARMul_State* state) {
3667 Common::Profiling::ScopeTimer timer_execute(profile_execute); 3694 Common::Profiling::ScopeTimer timer_execute(profile_execute);
3668 3695
@@ -3670,6 +3697,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
3670 #undef RS 3697 #undef RS
3671 3698
3672 #define CRn inst_cream->crn 3699 #define CRn inst_cream->crn
3700 #define OPCODE_1 inst_cream->opcode_1
3673 #define OPCODE_2 inst_cream->opcode_2 3701 #define OPCODE_2 inst_cream->opcode_2
3674 #define CRm inst_cream->crm 3702 #define CRm inst_cream->crm
3675 #define CP15_REG(n) cpu->CP15[CP15(n)] 3703 #define CP15_REG(n) cpu->CP15[CP15(n)]
@@ -4733,94 +4761,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
4733 if (inst_cream->Rd == 15) { 4761 if (inst_cream->Rd == 15) {
4734 DEBUG_MSG; 4762 DEBUG_MSG;
4735 } else { 4763 } else {
4736 if (inst_cream->cp_num == 15) { 4764 if (inst_cream->cp_num == 15)
4737 if (CRn == 1 && CRm == 0 && OPCODE_2 == 0) { 4765 WriteCP15Register(cpu, RD, CRn, OPCODE_1, CRm, OPCODE_2);
4738 CP15_REG(CP15_CONTROL) = RD;
4739 } else if (CRn == 1 && CRm == 0 && OPCODE_2 == 1) {
4740 CP15_REG(CP15_AUXILIARY_CONTROL) = RD;
4741 } else if (CRn == 1 && CRm == 0 && OPCODE_2 == 2) {
4742 CP15_REG(CP15_COPROCESSOR_ACCESS_CONTROL) = RD;
4743 } else if (CRn == 2 && CRm == 0 && OPCODE_2 == 0) {
4744 CP15_REG(CP15_TRANSLATION_BASE_TABLE_0) = RD;
4745 } else if (CRn == 2 && CRm == 0 && OPCODE_2 == 1) {
4746 CP15_REG(CP15_TRANSLATION_BASE_TABLE_1) = RD;
4747 } else if (CRn == 2 && CRm == 0 && OPCODE_2 == 2) {
4748 CP15_REG(CP15_TRANSLATION_BASE_CONTROL) = RD;
4749 } else if (CRn == 3 && CRm == 0 && OPCODE_2 == 0) {
4750 CP15_REG(CP15_DOMAIN_ACCESS_CONTROL) = RD;
4751 } else if(CRn == MMU_CACHE_OPS){
4752 //LOG_WARNING(Core_ARM11, "cache operations have not implemented.");
4753 } else if(CRn == MMU_TLB_OPS){
4754 switch (CRm) {
4755 case 5: // ITLB
4756 switch(OPCODE_2) {
4757 case 0: // Invalidate all
4758 LOG_DEBUG(Core_ARM11, "{TLB} [INSN] invalidate all");
4759 break;
4760 case 1: // Invalidate by MVA
4761 LOG_DEBUG(Core_ARM11, "{TLB} [INSN] invalidate by mva");
4762 break;
4763 case 2: // Invalidate by asid
4764 LOG_DEBUG(Core_ARM11, "{TLB} [INSN] invalidate by asid");
4765 break;
4766 default:
4767 break;
4768 }
4769
4770 break;
4771 case 6: // DTLB
4772 switch(OPCODE_2){
4773 case 0: // Invalidate all
4774 LOG_DEBUG(Core_ARM11, "{TLB} [DATA] invalidate all");
4775 break;
4776 case 1: // Invalidate by MVA
4777 LOG_DEBUG(Core_ARM11, "{TLB} [DATA] invalidate by mva");
4778 break;
4779 case 2: // Invalidate by asid
4780 LOG_DEBUG(Core_ARM11, "{TLB} [DATA] invalidate by asid");
4781 break;
4782 default:
4783 break;
4784 }
4785 break;
4786 case 7: // UNIFILED TLB
4787 switch(OPCODE_2){
4788 case 0: // invalidate all
4789 LOG_DEBUG(Core_ARM11, "{TLB} [UNIFILED] invalidate all");
4790 break;
4791 case 1: // Invalidate by MVA
4792 LOG_DEBUG(Core_ARM11, "{TLB} [UNIFILED] invalidate by mva");
4793 break;
4794 case 2: // Invalidate by asid
4795 LOG_DEBUG(Core_ARM11, "{TLB} [UNIFILED] invalidate by asid");
4796 break;
4797 default:
4798 break;
4799 }
4800 break;
4801 default:
4802 break;
4803 }
4804 } else if(CRn == MMU_PID) {
4805 if(OPCODE_2 == 0) {
4806 CP15_REG(CP15_PID) = RD;
4807 } else if(OPCODE_2 == 1) {
4808 CP15_REG(CP15_CONTEXT_ID) = RD;
4809 } else if (OPCODE_2 == 2) {
4810 CP15_REG(CP15_THREAD_UPRW) = RD;
4811 } else if(OPCODE_2 == 3) {
4812 if (InAPrivilegedMode(cpu))
4813 CP15_REG(CP15_THREAD_URO) = RD;
4814 } else if (OPCODE_2 == 4) {
4815 if (InAPrivilegedMode(cpu))
4816 CP15_REG(CP15_THREAD_PRW) = RD;
4817 } else {
4818 LOG_ERROR(Core_ARM11, "mmu_mcr wrote UNKNOWN - reg %d", CRn);
4819 }
4820 } else {
4821 LOG_ERROR(Core_ARM11, "mcr CRn=%d, CRm=%d OP2=%d is not implemented", CRn, CRm, OPCODE_2);
4822 }
4823 }
4824 } 4766 }
4825 } 4767 }
4826 cpu->Reg[15] += GET_INST_SIZE(cpu); 4768 cpu->Reg[15] += GET_INST_SIZE(cpu);
@@ -4895,50 +4837,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
4895 CITRA_IGNORE_EXIT(-1); 4837 CITRA_IGNORE_EXIT(-1);
4896 goto END; 4838 goto END;
4897 } else { 4839 } else {
4898 if (inst_cream->cp_num == 15) { 4840 if (inst_cream->cp_num == 15)
4899 if(CRn == 0 && OPCODE_2 == 0 && CRm == 0) { 4841 RD = ReadCP15Register(cpu, CRn, OPCODE_1, CRm, OPCODE_2);
4900 RD = cpu->CP15[CP15(CP15_MAIN_ID)];
4901 } else if (CRn == 0 && CRm == 0 && OPCODE_2 == 1) {
4902 RD = cpu->CP15[CP15(CP15_CACHE_TYPE)];
4903 } else if (CRn == 1 && CRm == 0 && OPCODE_2 == 0) {
4904 RD = cpu->CP15[CP15(CP15_CONTROL)];
4905 } else if (CRn == 1 && CRm == 0 && OPCODE_2 == 1) {
4906 RD = cpu->CP15[CP15(CP15_AUXILIARY_CONTROL)];
4907 } else if (CRn == 1 && CRm == 0 && OPCODE_2 == 2) {
4908 RD = cpu->CP15[CP15(CP15_COPROCESSOR_ACCESS_CONTROL)];
4909 } else if (CRn == 2 && CRm == 0 && OPCODE_2 == 0) {
4910 RD = cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_0)];
4911 } else if (CRn == 2 && CRm == 0 && OPCODE_2 == 1) {
4912 RD = cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_1)];
4913 } else if (CRn == 2 && CRm == 0 && OPCODE_2 == 2) {
4914 RD = cpu->CP15[CP15(CP15_TRANSLATION_BASE_CONTROL)];
4915 } else if (CRn == 3 && CRm == 0 && OPCODE_2 == 0) {
4916 RD = cpu->CP15[CP15(CP15_DOMAIN_ACCESS_CONTROL)];
4917 } else if (CRn == 5 && CRm == 0 && OPCODE_2 == 0) {
4918 RD = cpu->CP15[CP15(CP15_FAULT_STATUS)];
4919 } else if (CRn == 5 && CRm == 0 && OPCODE_2 == 1) {
4920 RD = cpu->CP15[CP15(CP15_INSTR_FAULT_STATUS)];
4921 } else if (CRn == 6 && CRm == 0 && OPCODE_2 == 0) {
4922 RD = cpu->CP15[CP15(CP15_FAULT_ADDRESS)];
4923 } else if (CRn == 13) {
4924 if(OPCODE_2 == 0) {
4925 RD = CP15_REG(CP15_PID);
4926 } else if(OPCODE_2 == 1) {
4927 RD = CP15_REG(CP15_CONTEXT_ID);
4928 } else if (OPCODE_2 == 2) {
4929 RD = CP15_REG(CP15_THREAD_UPRW);
4930 } else if(OPCODE_2 == 3) {
4931 RD = Memory::KERNEL_MEMORY_VADDR;
4932 } else if (OPCODE_2 == 4) {
4933 if (InAPrivilegedMode(cpu))
4934 RD = CP15_REG(CP15_THREAD_PRW);
4935 } else {
4936 LOG_ERROR(Core_ARM11, "mmu_mrr wrote UNKNOWN - reg %d", CRn);
4937 }
4938 } else {
4939 LOG_ERROR(Core_ARM11, "mrc CRn=%d, CRm=%d, OP2=%d is not implemented", CRn, CRm, OPCODE_2);
4940 }
4941 }
4942 } 4842 }
4943 } 4843 }
4944 cpu->Reg[15] += GET_INST_SIZE(cpu); 4844 cpu->Reg[15] += GET_INST_SIZE(cpu);
@@ -5293,6 +5193,20 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
5293 } 5193 }
5294 5194
5295 RFE_INST: 5195 RFE_INST:
5196 {
5197 // RFE is unconditional
5198 ldst_inst* const inst_cream = (ldst_inst*)inst_base->component;
5199
5200 u32 address = 0;
5201 inst_cream->get_addr(cpu, inst_cream->inst, address, 1);
5202
5203 cpu->Cpsr = ReadMemory32(cpu, address);
5204 cpu->Reg[15] = ReadMemory32(cpu, address + 4);
5205
5206 INC_PC(sizeof(ldst_inst));
5207 goto DISPATCH;
5208 }
5209
5296 RSB_INST: 5210 RSB_INST:
5297 { 5211 {
5298 if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { 5212 if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
@@ -5934,6 +5848,21 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
5934 } 5848 }
5935 5849
5936 SRS_INST: 5850 SRS_INST:
5851 {
5852 // SRS is unconditional
5853 ldst_inst* const inst_cream = (ldst_inst*)inst_base->component;
5854
5855 u32 address = 0;
5856 inst_cream->get_addr(cpu, inst_cream->inst, address, 1);
5857
5858 WriteMemory32(cpu, address + 0, cpu->Reg[14]);
5859 WriteMemory32(cpu, address + 4, cpu->Spsr_copy);
5860
5861 cpu->Reg[15] += GET_INST_SIZE(cpu);
5862 INC_PC(sizeof(ldst_inst));
5863 FETCH_INST;
5864 GOTO_NEXT_INST;
5865 }
5937 5866
5938 SSAT_INST: 5867 SSAT_INST:
5939 { 5868 {
diff --git a/src/core/arm/interpreter/armsupp.cpp b/src/core/arm/interpreter/armsupp.cpp
index aca2bfbbd..6a11a5804 100644
--- a/src/core/arm/interpreter/armsupp.cpp
+++ b/src/core/arm/interpreter/armsupp.cpp
@@ -15,7 +15,9 @@
15 along with this program; if not, write to the Free Software 15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
17 17
18#include "core/mem_map.h"
18#include "core/arm/skyeye_common/armdefs.h" 19#include "core/arm/skyeye_common/armdefs.h"
20#include "core/arm/skyeye_common/arm_regformat.h"
19 21
20// Unsigned sum of absolute difference 22// Unsigned sum of absolute difference
21u8 ARMul_UnsignedAbsoluteDifference(u8 left, u8 right) 23u8 ARMul_UnsignedAbsoluteDifference(u8 left, u8 right)
@@ -207,3 +209,432 @@ bool InBigEndianMode(ARMul_State* cpu)
207{ 209{
208 return (cpu->Cpsr & (1 << 9)) != 0; 210 return (cpu->Cpsr & (1 << 9)) != 0;
209} 211}
212
213// Whether or not the given CPU is in a mode other than user mode.
214bool InAPrivilegedMode(ARMul_State* cpu)
215{
216 return (cpu->Mode != USER32MODE);
217}
218
219// Reads from the CP15 registers. Used with implementation of the MRC instruction.
220// Note that since the 3DS does not have the hypervisor extensions, these registers
221// are not implemented.
222u32 ReadCP15Register(ARMul_State* cpu, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2)
223{
224 // Unprivileged registers
225 if (crn == 13 && opcode_1 == 0 && crm == 0)
226 {
227 if (opcode_2 == 2)
228 return cpu->CP15[CP15(CP15_THREAD_UPRW)];
229
230 // TODO: Whenever TLS is implemented, this should return
231 // "cpu->CP15[CP15(CP15_THREAD_URO)];"
232 // which contains the address of the 0x200-byte TLS
233 if (opcode_2 == 3)
234 return Memory::KERNEL_MEMORY_VADDR;
235 }
236
237 if (InAPrivilegedMode(cpu))
238 {
239 if (crn == 0 && opcode_1 == 0)
240 {
241 if (crm == 0)
242 {
243 if (opcode_2 == 0)
244 return cpu->CP15[CP15(CP15_MAIN_ID)];
245
246 if (opcode_2 == 1)
247 return cpu->CP15[CP15(CP15_CACHE_TYPE)];
248
249 if (opcode_2 == 3)
250 return cpu->CP15[CP15(CP15_TLB_TYPE)];
251
252 if (opcode_2 == 5)
253 return cpu->CP15[CP15(CP15_CPU_ID)];
254 }
255 else if (crm == 1)
256 {
257 if (opcode_2 == 0)
258 return cpu->CP15[CP15(CP15_PROCESSOR_FEATURE_0)];
259
260 if (opcode_2 == 1)
261 return cpu->CP15[CP15(CP15_PROCESSOR_FEATURE_1)];
262
263 if (opcode_2 == 2)
264 return cpu->CP15[CP15(CP15_DEBUG_FEATURE_0)];
265
266 if (opcode_2 == 4)
267 return cpu->CP15[CP15(CP15_MEMORY_MODEL_FEATURE_0)];
268
269 if (opcode_2 == 5)
270 return cpu->CP15[CP15(CP15_MEMORY_MODEL_FEATURE_1)];
271
272 if (opcode_2 == 6)
273 return cpu->CP15[CP15(CP15_MEMORY_MODEL_FEATURE_2)];
274
275 if (opcode_2 == 7)
276 return cpu->CP15[CP15(CP15_MEMORY_MODEL_FEATURE_3)];
277 }
278 else if (crm == 2)
279 {
280 if (opcode_2 == 0)
281 return cpu->CP15[CP15(CP15_ISA_FEATURE_0)];
282
283 if (opcode_2 == 1)
284 return cpu->CP15[CP15(CP15_ISA_FEATURE_1)];
285
286 if (opcode_2 == 2)
287 return cpu->CP15[CP15(CP15_ISA_FEATURE_2)];
288
289 if (opcode_2 == 3)
290 return cpu->CP15[CP15(CP15_ISA_FEATURE_3)];
291
292 if (opcode_2 == 4)
293 return cpu->CP15[CP15(CP15_ISA_FEATURE_4)];
294 }
295 }
296
297 if (crn == 1 && opcode_1 == 0 && crm == 0)
298 {
299 if (opcode_2 == 0)
300 return cpu->CP15[CP15(CP15_CONTROL)];
301
302 if (opcode_2 == 1)
303 return cpu->CP15[CP15(CP15_AUXILIARY_CONTROL)];
304
305 if (opcode_2 == 2)
306 return cpu->CP15[CP15(CP15_COPROCESSOR_ACCESS_CONTROL)];
307 }
308
309 if (crn == 2 && opcode_1 == 0 && crm == 0)
310 {
311 if (opcode_2 == 0)
312 return cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_0)];
313
314 if (opcode_2 == 1)
315 return cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_1)];
316
317 if (opcode_2 == 2)
318 return cpu->CP15[CP15(CP15_TRANSLATION_BASE_CONTROL)];
319 }
320
321 if (crn == 3 && opcode_1 == 0 && crm == 0 && opcode_2 == 0)
322 return cpu->CP15[CP15(CP15_DOMAIN_ACCESS_CONTROL)];
323
324 if (crn == 5 && opcode_1 == 0 && crm == 0)
325 {
326 if (opcode_2 == 0)
327 return cpu->CP15[CP15(CP15_FAULT_STATUS)];
328
329 if (opcode_2 == 1)
330 return cpu->CP15[CP15(CP15_INSTR_FAULT_STATUS)];
331 }
332
333 if (crn == 6 && opcode_1 == 0 && crm == 0)
334 {
335 if (opcode_2 == 0)
336 return cpu->CP15[CP15(CP15_FAULT_ADDRESS)];
337
338 if (opcode_2 == 1)
339 return cpu->CP15[CP15(CP15_WFAR)];
340 }
341
342 if (crn == 7 && opcode_1 == 0 && crm == 4 && opcode_2 == 0)
343 return cpu->CP15[CP15(CP15_PHYS_ADDRESS)];
344
345 if (crn == 9 && opcode_1 == 0 && crm == 0 && opcode_2 == 0)
346 return cpu->CP15[CP15(CP15_DATA_CACHE_LOCKDOWN)];
347
348 if (crn == 10 && opcode_1 == 0)
349 {
350 if (crm == 0 && opcode_2 == 0)
351 return cpu->CP15[CP15(CP15_TLB_LOCKDOWN)];
352
353 if (crm == 2)
354 {
355 if (opcode_2 == 0)
356 return cpu->CP15[CP15(CP15_PRIMARY_REGION_REMAP)];
357
358 if (opcode_2 == 1)
359 return cpu->CP15[CP15(CP15_NORMAL_REGION_REMAP)];
360 }
361 }
362
363 if (crn == 13 && crm == 0)
364 {
365 if (opcode_2 == 0)
366 return cpu->CP15[CP15(CP15_PID)];
367
368 if (opcode_2 == 1)
369 return cpu->CP15[CP15(CP15_CONTEXT_ID)];
370
371 if (opcode_2 == 4)
372 return cpu->CP15[CP15(CP15_THREAD_PRW)];
373 }
374
375 if (crn == 15)
376 {
377 if (opcode_1 == 0 && crm == 12)
378 {
379 if (opcode_2 == 0)
380 return cpu->CP15[CP15(CP15_PERFORMANCE_MONITOR_CONTROL)];
381
382 if (opcode_2 == 1)
383 return cpu->CP15[CP15(CP15_CYCLE_COUNTER)];
384
385 if (opcode_2 == 2)
386 return cpu->CP15[CP15(CP15_COUNT_0)];
387
388 if (opcode_2 == 3)
389 return cpu->CP15[CP15(CP15_COUNT_1)];
390 }
391
392 if (opcode_1 == 5 && opcode_2 == 2)
393 {
394 if (crm == 5)
395 return cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS)];
396
397 if (crm == 6)
398 return cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS)];
399
400 if (crm == 7)
401 return cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE)];
402 }
403
404 if (opcode_1 == 7 && crm == 1 && opcode_2 == 0)
405 return cpu->CP15[CP15(CP15_TLB_DEBUG_CONTROL)];
406 }
407 }
408
409 LOG_ERROR(Core_ARM11, "MRC CRn=%u, CRm=%u, OP1=%u OP2=%u is not implemented. Returning zero.", crn, crm, opcode_1, opcode_2);
410 return 0;
411}
412
413// Write to the CP15 registers. Used with implementation of the MCR instruction.
414// Note that since the 3DS does not have the hypervisor extensions, these registers
415// are not implemented.
416void WriteCP15Register(ARMul_State* cpu, u32 value, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2)
417{
418 if (InAPrivilegedMode(cpu))
419 {
420 if (crn == 1 && opcode_1 == 0 && crm == 0)
421 {
422 if (opcode_2 == 0)
423 cpu->CP15[CP15(CP15_CONTROL)] = value;
424 else if (opcode_2 == 1)
425 cpu->CP15[CP15(CP15_AUXILIARY_CONTROL)] = value;
426 else if (opcode_2 == 2)
427 cpu->CP15[CP15(CP15_COPROCESSOR_ACCESS_CONTROL)] = value;
428 }
429 else if (crn == 2 && opcode_1 == 0 && crm == 0)
430 {
431 if (opcode_2 == 0)
432 cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_0)] = value;
433 else if (opcode_2 == 1)
434 cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_1)] = value;
435 else if (opcode_2 == 2)
436 cpu->CP15[CP15(CP15_TRANSLATION_BASE_CONTROL)] = value;
437 }
438 else if (crn == 3 && opcode_1 == 0 && crm == 0 && opcode_2 == 0)
439 {
440 cpu->CP15[CP15(CP15_DOMAIN_ACCESS_CONTROL)] = value;
441 }
442 else if (crn == 5 && opcode_1 == 0 && crm == 0)
443 {
444 if (opcode_2 == 0)
445 cpu->CP15[CP15(CP15_FAULT_STATUS)] = value;
446 else if (opcode_2 == 1)
447 cpu->CP15[CP15(CP15_INSTR_FAULT_STATUS)] = value;
448 }
449 else if (crn == 6 && opcode_1 == 0 && crm == 0)
450 {
451 if (opcode_2 == 0)
452 cpu->CP15[CP15(CP15_FAULT_ADDRESS)] = value;
453 else if (opcode_2 == 1)
454 cpu->CP15[CP15(CP15_WFAR)] = value;
455 }
456 else if (crn == 7 && opcode_1 == 0)
457 {
458 LOG_WARNING(Core_ARM11, "Cache operations are not fully implemented.");
459
460 if (crm == 0 && opcode_2 == 4)
461 {
462 cpu->CP15[CP15(CP15_WAIT_FOR_INTERRUPT)] = value;
463 }
464 else if (crm == 4 && opcode_2 == 0)
465 {
466 // NOTE: Not entirely accurate. This should do permission checks.
467 cpu->CP15[CP15(CP15_PHYS_ADDRESS)] = Memory::VirtualToPhysicalAddress(value);
468 }
469 else if (crm == 5)
470 {
471 if (opcode_2 == 0)
472 cpu->CP15[CP15(CP15_INVALIDATE_INSTR_CACHE)] = value;
473 else if (opcode_2 == 1)
474 cpu->CP15[CP15(CP15_INVALIDATE_INSTR_CACHE_USING_MVA)] = value;
475 else if (opcode_2 == 2)
476 cpu->CP15[CP15(CP15_INVALIDATE_INSTR_CACHE_USING_INDEX)] = value;
477 else if (opcode_2 == 6)
478 cpu->CP15[CP15(CP15_FLUSH_BRANCH_TARGET_CACHE)] = value;
479 else if (opcode_2 == 7)
480 cpu->CP15[CP15(CP15_FLUSH_BRANCH_TARGET_CACHE_ENTRY)] = value;
481 }
482 else if (crm == 6)
483 {
484 if (opcode_2 == 0)
485 cpu->CP15[CP15(CP15_INVALIDATE_DATA_CACHE)] = value;
486 else if (opcode_2 == 1)
487 cpu->CP15[CP15(CP15_INVALIDATE_DATA_CACHE_LINE_USING_MVA)] = value;
488 else if (opcode_2 == 2)
489 cpu->CP15[CP15(CP15_INVALIDATE_DATA_CACHE_LINE_USING_INDEX)] = value;
490 }
491 else if (crm == 7 && opcode_2 == 0)
492 {
493 cpu->CP15[CP15(CP15_INVALIDATE_DATA_AND_INSTR_CACHE)] = value;
494 }
495 else if (crm == 10)
496 {
497 if (opcode_2 == 0)
498 cpu->CP15[CP15(CP15_CLEAN_DATA_CACHE)] = value;
499 else if (opcode_2 == 1)
500 cpu->CP15[CP15(CP15_CLEAN_DATA_CACHE_LINE_USING_MVA)] = value;
501 else if (opcode_2 == 2)
502 cpu->CP15[CP15(CP15_CLEAN_DATA_CACHE_LINE_USING_INDEX)] = value;
503 }
504 else if (crm == 14)
505 {
506 if (opcode_2 == 0)
507 cpu->CP15[CP15(CP15_CLEAN_AND_INVALIDATE_DATA_CACHE)] = value;
508 else if (opcode_2 == 1)
509 cpu->CP15[CP15(CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_MVA)] = value;
510 else if (opcode_2 == 2)
511 cpu->CP15[CP15(CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_INDEX)] = value;
512 }
513 }
514 else if (crn == 8 && opcode_1 == 0)
515 {
516 LOG_WARNING(Core_ARM11, "TLB operations not fully implemented.");
517
518 if (crm == 5)
519 {
520 if (opcode_2 == 0)
521 cpu->CP15[CP15(CP15_INVALIDATE_ITLB)] = value;
522 else if (opcode_2 == 1)
523 cpu->CP15[CP15(CP15_INVALIDATE_ITLB_SINGLE_ENTRY)] = value;
524 else if (opcode_2 == 2)
525 cpu->CP15[CP15(CP15_INVALIDATE_ITLB_ENTRY_ON_ASID_MATCH)] = value;
526 else if (opcode_2 == 3)
527 cpu->CP15[CP15(CP15_INVALIDATE_ITLB_ENTRY_ON_MVA)] = value;
528 }
529 else if (crm == 6)
530 {
531 if (opcode_2 == 0)
532 cpu->CP15[CP15(CP15_INVALIDATE_DTLB)] = value;
533 else if (opcode_2 == 1)
534 cpu->CP15[CP15(CP15_INVALIDATE_DTLB_SINGLE_ENTRY)] = value;
535 else if (opcode_2 == 2)
536 cpu->CP15[CP15(CP15_INVALIDATE_DTLB_ENTRY_ON_ASID_MATCH)] = value;
537 else if (opcode_2 == 3)
538 cpu->CP15[CP15(CP15_INVALIDATE_DTLB_ENTRY_ON_MVA)] = value;
539 }
540 else if (crm == 7)
541 {
542 if (opcode_2 == 0)
543 cpu->CP15[CP15(CP15_INVALIDATE_UTLB)] = value;
544 else if (opcode_2 == 1)
545 cpu->CP15[CP15(CP15_INVALIDATE_UTLB_SINGLE_ENTRY)] = value;
546 else if (opcode_2 == 2)
547 cpu->CP15[CP15(CP15_INVALIDATE_UTLB_ENTRY_ON_ASID_MATCH)] = value;
548 else if (opcode_2 == 3)
549 cpu->CP15[CP15(CP15_INVALIDATE_UTLB_ENTRY_ON_MVA)] = value;
550 }
551 }
552 else if (crn == 9 && opcode_1 == 0 && crm == 0 && opcode_2 == 0)
553 {
554 cpu->CP15[CP15(CP15_DATA_CACHE_LOCKDOWN)] = value;
555 }
556 else if (crn == 10 && opcode_1 == 0)
557 {
558 if (crm == 0 && opcode_2 == 0)
559 {
560 cpu->CP15[CP15(CP15_TLB_LOCKDOWN)] = value;
561 }
562 else if (crm == 2)
563 {
564 if (opcode_2 == 0)
565 cpu->CP15[CP15(CP15_PRIMARY_REGION_REMAP)] = value;
566 else if (opcode_2 == 1)
567 cpu->CP15[CP15(CP15_NORMAL_REGION_REMAP)] = value;
568 }
569 }
570 else if (crn == 13 && opcode_1 == 0 && crm == 0)
571 {
572 if (opcode_2 == 0)
573 cpu->CP15[CP15(CP15_PID)] = value;
574 else if (opcode_2 == 1)
575 cpu->CP15[CP15(CP15_CONTEXT_ID)] = value;
576 else if (opcode_2 == 3)
577 cpu->CP15[CP15(CP15_THREAD_URO)] = value;
578 else if (opcode_2 == 4)
579 cpu->CP15[CP15(CP15_THREAD_PRW)] = value;
580 }
581 else if (crn == 15)
582 {
583 if (opcode_1 == 0 && crm == 12)
584 {
585 if (opcode_2 == 0)
586 cpu->CP15[CP15(CP15_PERFORMANCE_MONITOR_CONTROL)] = value;
587 else if (opcode_2 == 1)
588 cpu->CP15[CP15(CP15_CYCLE_COUNTER)] = value;
589 else if (opcode_2 == 2)
590 cpu->CP15[CP15(CP15_COUNT_0)] = value;
591 else if (opcode_2 == 3)
592 cpu->CP15[CP15(CP15_COUNT_1)] = value;
593 }
594 else if (opcode_1 == 5)
595 {
596 if (crm == 4)
597 {
598 if (opcode_2 == 2)
599 cpu->CP15[CP15(CP15_READ_MAIN_TLB_LOCKDOWN_ENTRY)] = value;
600 else if (opcode_2 == 4)
601 cpu->CP15[CP15(CP15_WRITE_MAIN_TLB_LOCKDOWN_ENTRY)] = value;
602 }
603 else if (crm == 5 && opcode_2 == 2)
604 {
605 cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS)] = value;
606 }
607 else if (crm == 6 && opcode_2 == 2)
608 {
609 cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS)] = value;
610 }
611 else if (crm == 7 && opcode_2 == 2)
612 {
613 cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE)] = value;
614 }
615 }
616 else if (opcode_1 == 7 && crm == 1 && opcode_2 == 0)
617 {
618 cpu->CP15[CP15(CP15_TLB_DEBUG_CONTROL)] = value;
619 }
620 }
621 }
622
623 // Unprivileged registers
624 if (crn == 7 && opcode_1 == 0 && crm == 5 && opcode_2 == 4)
625 {
626 cpu->CP15[CP15(CP15_FLUSH_PREFETCH_BUFFER)] = value;
627 }
628 else if (crn == 7 && opcode_1 == 0 && crm == 10)
629 {
630 if (opcode_2 == 4)
631 cpu->CP15[CP15(CP15_DATA_SYNC_BARRIER)] = value;
632 else if (opcode_2 == 5)
633 cpu->CP15[CP15(CP15_DATA_MEMORY_BARRIER)] = value;
634
635 }
636 else if (crn == 13 && opcode_1 == 0 && crm == 0 && opcode_2 == 2)
637 {
638 cpu->CP15[CP15(CP15_THREAD_UPRW)] = value;
639 }
640}
diff --git a/src/core/arm/skyeye_common/arm_regformat.h b/src/core/arm/skyeye_common/arm_regformat.h
index 5be3a561f..c232376e0 100644
--- a/src/core/arm/skyeye_common/arm_regformat.h
+++ b/src/core/arm/skyeye_common/arm_regformat.h
@@ -50,6 +50,8 @@ enum {
50 EXCLUSIVE_TAG, 50 EXCLUSIVE_TAG,
51 EXCLUSIVE_STATE, 51 EXCLUSIVE_STATE,
52 EXCLUSIVE_RESULT, 52 EXCLUSIVE_RESULT,
53
54 // c0 - Information registers
53 CP15_BASE, 55 CP15_BASE,
54 CP15_C0 = CP15_BASE, 56 CP15_C0 = CP15_BASE,
55 CP15_C0_C0 = CP15_C0, 57 CP15_C0_C0 = CP15_C0,
@@ -57,15 +59,30 @@ enum {
57 CP15_CACHE_TYPE, 59 CP15_CACHE_TYPE,
58 CP15_TCM_STATUS, 60 CP15_TCM_STATUS,
59 CP15_TLB_TYPE, 61 CP15_TLB_TYPE,
62 CP15_CPU_ID,
60 CP15_C0_C1, 63 CP15_C0_C1,
61 CP15_PROCESSOR_FEATURE_0 = CP15_C0_C1, 64 CP15_PROCESSOR_FEATURE_0 = CP15_C0_C1,
62 CP15_PROCESSOR_FEATURE_1, 65 CP15_PROCESSOR_FEATURE_1,
63 CP15_DEBUG_FEATURE_0, 66 CP15_DEBUG_FEATURE_0,
64 CP15_AUXILIARY_FEATURE_0, 67 CP15_AUXILIARY_FEATURE_0,
68 CP15_MEMORY_MODEL_FEATURE_0,
69 CP15_MEMORY_MODEL_FEATURE_1,
70 CP15_MEMORY_MODEL_FEATURE_2,
71 CP15_MEMORY_MODEL_FEATURE_3,
72 CP15_C0_C2,
73 CP15_ISA_FEATURE_0 = CP15_C0_C2,
74 CP15_ISA_FEATURE_1,
75 CP15_ISA_FEATURE_2,
76 CP15_ISA_FEATURE_3,
77 CP15_ISA_FEATURE_4,
78
79 // c1 - Control registers
65 CP15_C1_C0, 80 CP15_C1_C0,
66 CP15_CONTROL = CP15_C1_C0, 81 CP15_CONTROL = CP15_C1_C0,
67 CP15_AUXILIARY_CONTROL, 82 CP15_AUXILIARY_CONTROL,
68 CP15_COPROCESSOR_ACCESS_CONTROL, 83 CP15_COPROCESSOR_ACCESS_CONTROL,
84
85 // c2 - Translation table registers
69 CP15_C2, 86 CP15_C2,
70 CP15_C2_C0 = CP15_C2, 87 CP15_C2_C0 = CP15_C2,
71 CP15_TRANSLATION_BASE = CP15_C2_C0, 88 CP15_TRANSLATION_BASE = CP15_C2_C0,
@@ -74,24 +91,87 @@ enum {
74 CP15_TRANSLATION_BASE_CONTROL, 91 CP15_TRANSLATION_BASE_CONTROL,
75 CP15_DOMAIN_ACCESS_CONTROL, 92 CP15_DOMAIN_ACCESS_CONTROL,
76 CP15_RESERVED, 93 CP15_RESERVED,
77 /* Fault status */ 94
95 // c5 - Fault status registers
78 CP15_FAULT_STATUS, 96 CP15_FAULT_STATUS,
79 CP15_INSTR_FAULT_STATUS, 97 CP15_INSTR_FAULT_STATUS,
80 CP15_COMBINED_DATA_FSR = CP15_FAULT_STATUS, 98 CP15_COMBINED_DATA_FSR = CP15_FAULT_STATUS,
81 CP15_INST_FSR, 99 CP15_INST_FSR,
82 /* Fault Address register */ 100
101 // c6 - Fault Address registers
83 CP15_FAULT_ADDRESS, 102 CP15_FAULT_ADDRESS,
84 CP15_COMBINED_DATA_FAR = CP15_FAULT_ADDRESS, 103 CP15_COMBINED_DATA_FAR = CP15_FAULT_ADDRESS,
85 CP15_WFAR, 104 CP15_WFAR,
86 CP15_IFAR, 105 CP15_IFAR,
106
107 // c7 - Cache operation registers
108 CP15_WAIT_FOR_INTERRUPT,
109 CP15_PHYS_ADDRESS,
110 CP15_INVALIDATE_INSTR_CACHE,
111 CP15_INVALIDATE_INSTR_CACHE_USING_MVA,
112 CP15_INVALIDATE_INSTR_CACHE_USING_INDEX,
113 CP15_FLUSH_PREFETCH_BUFFER,
114 CP15_FLUSH_BRANCH_TARGET_CACHE,
115 CP15_FLUSH_BRANCH_TARGET_CACHE_ENTRY,
116 CP15_INVALIDATE_DATA_CACHE,
117 CP15_INVALIDATE_DATA_CACHE_LINE_USING_MVA,
118 CP15_INVALIDATE_DATA_CACHE_LINE_USING_INDEX,
119 CP15_INVALIDATE_DATA_AND_INSTR_CACHE,
120 CP15_CLEAN_DATA_CACHE,
121 CP15_CLEAN_DATA_CACHE_LINE_USING_MVA,
122 CP15_CLEAN_DATA_CACHE_LINE_USING_INDEX,
123 CP15_DATA_SYNC_BARRIER,
124 CP15_DATA_MEMORY_BARRIER,
125 CP15_CLEAN_AND_INVALIDATE_DATA_CACHE,
126 CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_MVA,
127 CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_INDEX,
128
129 // c8 - TLB operations
130 CP15_INVALIDATE_ITLB,
131 CP15_INVALIDATE_ITLB_SINGLE_ENTRY,
132 CP15_INVALIDATE_ITLB_ENTRY_ON_ASID_MATCH,
133 CP15_INVALIDATE_ITLB_ENTRY_ON_MVA,
134 CP15_INVALIDATE_DTLB,
135 CP15_INVALIDATE_DTLB_SINGLE_ENTRY,
136 CP15_INVALIDATE_DTLB_ENTRY_ON_ASID_MATCH,
137 CP15_INVALIDATE_DTLB_ENTRY_ON_MVA,
138 CP15_INVALIDATE_UTLB,
139 CP15_INVALIDATE_UTLB_SINGLE_ENTRY,
140 CP15_INVALIDATE_UTLB_ENTRY_ON_ASID_MATCH,
141 CP15_INVALIDATE_UTLB_ENTRY_ON_MVA,
142
143 // c9 - Data cache lockdown register
144 CP15_DATA_CACHE_LOCKDOWN,
145
146 // c10 - TLB/Memory map registers
147 CP15_TLB_LOCKDOWN,
148 CP15_PRIMARY_REGION_REMAP,
149 CP15_NORMAL_REGION_REMAP,
150
151 // c13 - Thread related registers
87 CP15_PID, 152 CP15_PID,
88 CP15_CONTEXT_ID, 153 CP15_CONTEXT_ID,
89 CP15_THREAD_UPRW, // Thread ID register - User/Privileged Read/Write 154 CP15_THREAD_UPRW, // Thread ID register - User/Privileged Read/Write
90 CP15_THREAD_URO, // Thread ID register - User Read Only (Privileged R/W) 155 CP15_THREAD_URO, // Thread ID register - User Read Only (Privileged R/W)
91 CP15_THREAD_PRW, // Thread ID register - Privileged R/W only. 156 CP15_THREAD_PRW, // Thread ID register - Privileged R/W only.
92 CP15_TLB_FAULT_ADDR, /* defined by SkyEye */ 157
93 CP15_TLB_FAULT_STATUS, /* defined by SkyEye */ 158 // c15 - Performance and TLB lockdown registers
94 /* VFP registers */ 159 CP15_PERFORMANCE_MONITOR_CONTROL,
160 CP15_CYCLE_COUNTER,
161 CP15_COUNT_0,
162 CP15_COUNT_1,
163 CP15_READ_MAIN_TLB_LOCKDOWN_ENTRY,
164 CP15_WRITE_MAIN_TLB_LOCKDOWN_ENTRY,
165 CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS,
166 CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS,
167 CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE,
168 CP15_TLB_DEBUG_CONTROL,
169
170 // Skyeye defined
171 CP15_TLB_FAULT_ADDR,
172 CP15_TLB_FAULT_STATUS,
173
174 // VFP registers
95 VFP_BASE, 175 VFP_BASE,
96 VFP_FPSID = VFP_BASE, 176 VFP_FPSID = VFP_BASE,
97 VFP_FPSCR, 177 VFP_FPSCR,
diff --git a/src/core/arm/skyeye_common/armdefs.h b/src/core/arm/skyeye_common/armdefs.h
index c1a19fecc..d5b0242c3 100644
--- a/src/core/arm/skyeye_common/armdefs.h
+++ b/src/core/arm/skyeye_common/armdefs.h
@@ -357,3 +357,7 @@ extern u32 ARMul_SignedSatQ(s32, u8, bool*);
357extern u32 ARMul_UnsignedSatQ(s32, u8, bool*); 357extern u32 ARMul_UnsignedSatQ(s32, u8, bool*);
358 358
359extern bool InBigEndianMode(ARMul_State*); 359extern bool InBigEndianMode(ARMul_State*);
360extern bool InAPrivilegedMode(ARMul_State*);
361
362extern u32 ReadCP15Register(ARMul_State* cpu, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2);
363extern void WriteCP15Register(ARMul_State* cpu, u32 value, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2);
diff --git a/src/core/hle/config_mem.cpp b/src/core/hle/config_mem.cpp
index b10c19d1d..40bae9346 100644
--- a/src/core/hle/config_mem.cpp
+++ b/src/core/hle/config_mem.cpp
@@ -65,9 +65,9 @@ void Init() {
65 config_mem.sys_core_ver = 0x2; 65 config_mem.sys_core_ver = 0x2;
66 config_mem.unit_info = 0x1; // Bit 0 set for Retail 66 config_mem.unit_info = 0x1; // Bit 0 set for Retail
67 config_mem.prev_firm = 0; 67 config_mem.prev_firm = 0;
68 config_mem.app_mem_type = 0; // Defualt app mem type 68 config_mem.app_mem_type = 0x2; // Default app mem type is 0
69 config_mem.unit_info = 0x1; // Bit 0 set for Retail 69 config_mem.unit_info = 0x1; // Bit 0 set for Retail
70 config_mem.app_mem_alloc = 0x04000000; // Default app memory size is 64MB 70 config_mem.app_mem_alloc = 0x06000000; // Set to 96MB, since some games use more than the default (64MB)
71 config_mem.base_mem_alloc = 0x01400000; // Default base memory is 20MB 71 config_mem.base_mem_alloc = 0x01400000; // Default base memory is 20MB
72 config_mem.sys_mem_alloc = Memory::FCRAM_SIZE - (config_mem.app_mem_alloc + config_mem.base_mem_alloc); 72 config_mem.sys_mem_alloc = Memory::FCRAM_SIZE - (config_mem.app_mem_alloc + config_mem.base_mem_alloc);
73 config_mem.firm_unk = 0; 73 config_mem.firm_unk = 0;
HIC SVNT DRACONES