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-rw-r--r--src/core/CMakeLists.txt2
-rw-r--r--src/core/arm/dyncom/arm_dyncom.cpp5
-rw-r--r--src/core/arm/dyncom/arm_dyncom_thumb.cpp6
-rw-r--r--src/core/arm/skyeye_common/armdefs.h4
-rw-r--r--src/core/arm/skyeye_common/armos.h54
-rw-r--r--src/core/arm/skyeye_common/skyeye_defs.h13
6 files changed, 2 insertions, 82 deletions
diff --git a/src/core/CMakeLists.txt b/src/core/CMakeLists.txt
index fa6b4215a..aaa6d87f3 100644
--- a/src/core/CMakeLists.txt
+++ b/src/core/CMakeLists.txt
@@ -115,8 +115,6 @@ set(HEADERS
115 arm/skyeye_common/armdefs.h 115 arm/skyeye_common/armdefs.h
116 arm/skyeye_common/armemu.h 116 arm/skyeye_common/armemu.h
117 arm/skyeye_common/armmmu.h 117 arm/skyeye_common/armmmu.h
118 arm/skyeye_common/armos.h
119 arm/skyeye_common/skyeye_defs.h
120 arm/skyeye_common/vfp/asm_vfp.h 118 arm/skyeye_common/vfp/asm_vfp.h
121 arm/skyeye_common/vfp/vfp.h 119 arm/skyeye_common/vfp/vfp.h
122 arm/skyeye_common/vfp/vfp_helper.h 120 arm/skyeye_common/vfp/vfp_helper.h
diff --git a/src/core/arm/dyncom/arm_dyncom.cpp b/src/core/arm/dyncom/arm_dyncom.cpp
index 42a63e46f..0072ae533 100644
--- a/src/core/arm/dyncom/arm_dyncom.cpp
+++ b/src/core/arm/dyncom/arm_dyncom.cpp
@@ -16,10 +16,6 @@
16#include "core/core.h" 16#include "core/core.h"
17#include "core/core_timing.h" 17#include "core/core_timing.h"
18 18
19const static cpu_config_t s_arm11_cpu_info = {
20 "armv6", "arm11", 0x0007b000, 0x0007f000, NONCACHE
21};
22
23ARM_DynCom::ARM_DynCom(PrivilegeMode initial_mode) { 19ARM_DynCom::ARM_DynCom(PrivilegeMode initial_mode) {
24 state = Common::make_unique<ARMul_State>(); 20 state = Common::make_unique<ARMul_State>();
25 21
@@ -27,7 +23,6 @@ ARM_DynCom::ARM_DynCom(PrivilegeMode initial_mode) {
27 ARMul_SelectProcessor(state.get(), ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop); 23 ARMul_SelectProcessor(state.get(), ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop);
28 24
29 state->abort_model = ABORT_BASE_RESTORED; 25 state->abort_model = ABORT_BASE_RESTORED;
30 state->cpu = (cpu_config_t*)&s_arm11_cpu_info;
31 26
32 state->bigendSig = LOW; 27 state->bigendSig = LOW;
33 state->lateabtSig = LOW; 28 state->lateabtSig = LOW;
diff --git a/src/core/arm/dyncom/arm_dyncom_thumb.cpp b/src/core/arm/dyncom/arm_dyncom_thumb.cpp
index bfb45f104..08b5c0b77 100644
--- a/src/core/arm/dyncom/arm_dyncom_thumb.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_thumb.cpp
@@ -6,8 +6,6 @@
6// ARM instruction, and using the existing ARM simulator. 6// ARM instruction, and using the existing ARM simulator.
7 7
8#include "core/arm/dyncom/arm_dyncom_thumb.h" 8#include "core/arm/dyncom/arm_dyncom_thumb.h"
9#include "core/arm/skyeye_common/armos.h"
10#include "core/arm/skyeye_common/skyeye_defs.h"
11 9
12// Decode a 16bit Thumb instruction. The instruction is in the low 16-bits of the tinstr field, 10// Decode a 16bit Thumb instruction. The instruction is in the low 16-bits of the tinstr field,
13// with the following Thumb instruction held in the high 16-bits. Passing in two Thumb instructions 11// with the following Thumb instruction held in the high 16-bits. Passing in two Thumb instructions
@@ -288,7 +286,7 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
288 : 0xE28DDF00) // ADD 286 : 0xE28DDF00) // ADD
289 |(tinstr & 0x007F); // off7 287 |(tinstr & 0x007F); // off7
290 } else if ((tinstr & 0x0F00) == 0x0e00) 288 } else if ((tinstr & 0x0F00) == 0x0e00)
291 *ainstr = 0xEF000000 | SWI_Breakpoint; 289 *ainstr = 0xEF000000 | 0x180000; // base | BKPT mask
292 else { 290 else {
293 static const ARMword subset[4] = { 291 static const ARMword subset[4] = {
294 0xE92D0000, // STMDB sp!,{rlist} 292 0xE92D0000, // STMDB sp!,{rlist}
@@ -320,7 +318,7 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
320 *ainstr |= ((tinstr & 0x00FF) << 16); 318 *ainstr |= ((tinstr & 0x00FF) << 16);
321 // New breakpoint value. See gdb/arm-tdep.c 319 // New breakpoint value. See gdb/arm-tdep.c
322 else if ((tinstr & 0x00FF) == 0xFE) 320 else if ((tinstr & 0x00FF) == 0xFE)
323 *ainstr |= SWI_Breakpoint; 321 *ainstr |= 0x180000; // base |= BKPT mask
324 else 322 else
325 *ainstr |= (tinstr & 0x00FF); 323 *ainstr |= (tinstr & 0x00FF);
326 } else if ((tinstr & 0x0F00) != 0x0E00) 324 } else if ((tinstr & 0x0F00) != 0x0E00)
diff --git a/src/core/arm/skyeye_common/armdefs.h b/src/core/arm/skyeye_common/armdefs.h
index 85d523bc2..470f9508d 100644
--- a/src/core/arm/skyeye_common/armdefs.h
+++ b/src/core/arm/skyeye_common/armdefs.h
@@ -21,7 +21,6 @@
21 21
22#include "common/common_types.h" 22#include "common/common_types.h"
23#include "core/arm/skyeye_common/arm_regformat.h" 23#include "core/arm/skyeye_common/arm_regformat.h"
24#include "core/arm/skyeye_common/skyeye_defs.h"
25 24
26#define BITS(s, a, b) ((s << ((sizeof(s) * 8 - 1) - b)) >> (sizeof(s) * 8 - b + a - 1)) 25#define BITS(s, a, b) ((s << ((sizeof(s) * 8 - 1) - b)) >> (sizeof(s) * 8 - b + a - 1))
27#define BIT(s, n) ((s >> (n)) & 1) 26#define BIT(s, n) ((s >> (n)) & 1)
@@ -152,9 +151,6 @@ So, if lateabtSig=1, then it means Late Abort Model(Base Updated Abort Model)
152 // 0 Base Restored Abort Model, 1 the Early Abort Model, 2 Base Updated Abort Model 151 // 0 Base Restored Abort Model, 1 the Early Abort Model, 2 Base Updated Abort Model
153 int abort_model; 152 int abort_model;
154 153
155 // Added by ksh in 2005-10-1
156 cpu_config_t* cpu;
157
158 // TODO(bunnei): Move this cache to a better place - it should be per codeset (likely per 154 // TODO(bunnei): Move this cache to a better place - it should be per codeset (likely per
159 // process for our purposes), not per ARMul_State (which tracks CPU core state). 155 // process for our purposes), not per ARMul_State (which tracks CPU core state).
160 std::unordered_map<u32, int> instruction_cache; 156 std::unordered_map<u32, int> instruction_cache;
diff --git a/src/core/arm/skyeye_common/armos.h b/src/core/arm/skyeye_common/armos.h
deleted file mode 100644
index 1217a728b..000000000
--- a/src/core/arm/skyeye_common/armos.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/* armos.h -- ARMulator OS definitions: ARM6 Instruction Emulator.
2 Copyright (C) 1994 Advanced RISC Machines Ltd.
3
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
8
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17*/
18
19//
20// SWI Numbers
21//
22
23#define SWI_Syscall 0x0
24#define SWI_Exit 0x1
25#define SWI_Read 0x3
26#define SWI_Write 0x4
27#define SWI_Open 0x5
28#define SWI_Close 0x6
29#define SWI_Seek 0x13
30#define SWI_Rename 0x26
31#define SWI_Break 0x11
32
33#define SWI_Times 0x2b
34#define SWI_Brk 0x2d
35
36#define SWI_Mmap 0x5a
37#define SWI_Munmap 0x5b
38#define SWI_Mmap2 0xc0
39
40#define SWI_GetUID32 0xc7
41#define SWI_GetGID32 0xc8
42#define SWI_GetEUID32 0xc9
43#define SWI_GetEGID32 0xca
44
45#define SWI_ExitGroup 0xf8
46
47#define SWI_Uname 0x7a
48#define SWI_Fcntl 0xdd
49#define SWI_Fstat64 0xc5
50#define SWI_Gettimeofday 0x4e
51#define SWI_Set_tls 0xf0005
52
53#define SWI_Breakpoint 0x180000 /* see gdb's tm-arm.h */
54
diff --git a/src/core/arm/skyeye_common/skyeye_defs.h b/src/core/arm/skyeye_common/skyeye_defs.h
deleted file mode 100644
index 94b02459d..000000000
--- a/src/core/arm/skyeye_common/skyeye_defs.h
+++ /dev/null
@@ -1,13 +0,0 @@
1#pragma once
2
3#include "common/common_types.h"
4
5struct cpu_config_t
6{
7 const char* cpu_arch_name; // CPU architecture version name.e.g. ARMv4T
8 const char* cpu_name; // CPU name. e.g. ARM7TDMI or ARM720T
9 u32 cpu_val; // CPU value; also call MMU ID or processor id;see
10 // ARM Architecture Reference Manual B2-6
11 u32 cpu_mask; // cpu_val's mask.
12 u32 cachetype; // CPU cache type
13};