diff options
| -rw-r--r-- | src/shader_recompiler/frontend/maxwell/translate/impl/load_constant.cpp | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/load_constant.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/load_constant.cpp index 2300088e3..8007a4d46 100644 --- a/src/shader_recompiler/frontend/maxwell/translate/impl/load_constant.cpp +++ b/src/shader_recompiler/frontend/maxwell/translate/impl/load_constant.cpp | |||
| @@ -11,10 +11,20 @@ namespace Shader::Maxwell { | |||
| 11 | using namespace LDC; | 11 | using namespace LDC; |
| 12 | namespace { | 12 | namespace { |
| 13 | std::pair<IR::U32, IR::U32> Slot(IR::IREmitter& ir, Mode mode, const IR::U32& imm_index, | 13 | std::pair<IR::U32, IR::U32> Slot(IR::IREmitter& ir, Mode mode, const IR::U32& imm_index, |
| 14 | const IR::U32& reg, const IR::U32& imm) { | 14 | const IR::U32& reg, const IR::U32& imm_offset) { |
| 15 | switch (mode) { | 15 | switch (mode) { |
| 16 | case Mode::Default: | 16 | case Mode::Default: |
| 17 | return {imm_index, ir.IAdd(reg, imm)}; | 17 | return {imm_index, ir.IAdd(reg, imm_offset)}; |
| 18 | case Mode::IS: { | ||
| 19 | // Segmented addressing mode | ||
| 20 | // Ra+imm_offset points into a flat mapping of const buffer | ||
| 21 | // address space | ||
| 22 | const IR::U32 address{ir.IAdd(reg, imm_offset)}; | ||
| 23 | const IR::U32 index{ir.BitFieldExtract(address, ir.Imm32(16), ir.Imm32(16))}; | ||
| 24 | const IR::U32 offset{ir.BitFieldExtract(address, ir.Imm32(0), ir.Imm32(16))}; | ||
| 25 | |||
| 26 | return {ir.IAdd(index, imm_index), offset}; | ||
| 27 | } | ||
| 18 | default: | 28 | default: |
| 19 | break; | 29 | break; |
| 20 | } | 30 | } |