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-rw-r--r--src/core/arm/dynarmic/arm_dynarmic_64.cpp6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/core/arm/dynarmic/arm_dynarmic_64.cpp b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
index d96226c41..24107f9f6 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_64.cpp
+++ b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
@@ -93,17 +93,19 @@ public:
93 static constexpr u64 ICACHE_LINE_SIZE = 64; 93 static constexpr u64 ICACHE_LINE_SIZE = 64;
94 94
95 const u64 cache_line_start = value & ~(ICACHE_LINE_SIZE - 1); 95 const u64 cache_line_start = value & ~(ICACHE_LINE_SIZE - 1);
96 parent.InvalidateCacheRange(cache_line_start, ICACHE_LINE_SIZE); 96 parent.system.InvalidateCpuInstructionCacheRange(cache_line_start, ICACHE_LINE_SIZE);
97 break; 97 break;
98 } 98 }
99 case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoU: 99 case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoU:
100 parent.ClearInstructionCache(); 100 parent.system.InvalidateCpuInstructionCaches();
101 break; 101 break;
102 case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoUInnerSharable: 102 case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoUInnerSharable:
103 default: 103 default:
104 LOG_DEBUG(Core_ARM, "Unprocesseed instruction cache operation: {}", op); 104 LOG_DEBUG(Core_ARM, "Unprocesseed instruction cache operation: {}", op);
105 break; 105 break;
106 } 106 }
107
108 parent.jit->HaltExecution();
107 } 109 }
108 110
109 void ExceptionRaised(u64 pc, Dynarmic::A64::Exception exception) override { 111 void ExceptionRaised(u64 pc, Dynarmic::A64::Exception exception) override {