summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--src/video_core/engines/shader_bytecode.h16
-rw-r--r--src/video_core/shader/decode/memory.cpp9
2 files changed, 20 insertions, 5 deletions
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h
index acf475289..38db4addd 100644
--- a/src/video_core/engines/shader_bytecode.h
+++ b/src/video_core/engines/shader_bytecode.h
@@ -387,6 +387,20 @@ enum class IpaSampleMode : u64 {
387 Offset = 2, 387 Offset = 2,
388}; 388};
389 389
390enum class LmemLoadCacheManagement : u64 {
391 Default = 0,
392 LU = 1,
393 CI = 2,
394 CV = 3,
395};
396
397enum class LmemStoreCacheManagement : u64 {
398 Default = 0,
399 CG = 1,
400 CS = 2,
401 WT = 3,
402};
403
390struct IpaMode { 404struct IpaMode {
391 IpaInterpMode interpolation_mode; 405 IpaInterpMode interpolation_mode;
392 IpaSampleMode sampling_mode; 406 IpaSampleMode sampling_mode;
@@ -782,7 +796,7 @@ union Instruction {
782 } ld_l; 796 } ld_l;
783 797
784 union { 798 union {
785 BitField<44, 2, u64> unknown; 799 BitField<44, 2, LmemStoreCacheManagement> cache_management;
786 } st_l; 800 } st_l;
787 801
788 union { 802 union {
diff --git a/src/video_core/shader/decode/memory.cpp b/src/video_core/shader/decode/memory.cpp
index ff19ada55..ea1092db1 100644
--- a/src/video_core/shader/decode/memory.cpp
+++ b/src/video_core/shader/decode/memory.cpp
@@ -8,6 +8,7 @@
8 8
9#include "common/assert.h" 9#include "common/assert.h"
10#include "common/common_types.h" 10#include "common/common_types.h"
11#include "common/logging/log.h"
11#include "video_core/engines/shader_bytecode.h" 12#include "video_core/engines/shader_bytecode.h"
12#include "video_core/shader/shader_ir.h" 13#include "video_core/shader/shader_ir.h"
13 14
@@ -102,8 +103,8 @@ u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) {
102 break; 103 break;
103 } 104 }
104 case OpCode::Id::LD_L: { 105 case OpCode::Id::LD_L: {
105 UNIMPLEMENTED_IF_MSG(instr.ld_l.unknown == 1, "LD_L Unhandled mode: {}", 106 LOG_DEBUG(HW_GPU, "LD_L cache management mode: {}",
106 static_cast<u32>(instr.ld_l.unknown.Value())); 107 static_cast<u64>(instr.ld_l.unknown.Value()));
107 108
108 const auto GetLmem = [&](s32 offset) { 109 const auto GetLmem = [&](s32 offset) {
109 ASSERT(offset % 4 == 0); 110 ASSERT(offset % 4 == 0);
@@ -214,8 +215,8 @@ u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) {
214 break; 215 break;
215 } 216 }
216 case OpCode::Id::ST_L: { 217 case OpCode::Id::ST_L: {
217 UNIMPLEMENTED_IF_MSG(instr.st_l.unknown == 0, "ST_L Unhandled mode: {}", 218 LOG_DEBUG(HW_GPU, "ST_L cache management mode: {}",
218 static_cast<u32>(instr.st_l.unknown.Value())); 219 static_cast<u64>(instr.st_l.cache_management.Value()));
219 220
220 const auto GetLmemAddr = [&](s32 offset) { 221 const auto GetLmemAddr = [&](s32 offset) {
221 ASSERT(offset % 4 == 0); 222 ASSERT(offset % 4 == 0);