diff options
Diffstat (limited to '')
| -rw-r--r-- | src/video_core/shader/control_flow.cpp | 23 |
1 files changed, 12 insertions, 11 deletions
diff --git a/src/video_core/shader/control_flow.cpp b/src/video_core/shader/control_flow.cpp index 7e6364d94..b427ac873 100644 --- a/src/video_core/shader/control_flow.cpp +++ b/src/video_core/shader/control_flow.cpp | |||
| @@ -182,12 +182,12 @@ std::optional<std::pair<BufferInfo, u64>> TrackLDC(const CFGRebuildState& state, | |||
| 182 | u64 brx_tracked_register) { | 182 | u64 brx_tracked_register) { |
| 183 | return TrackInstruction<std::pair<BufferInfo, u64>>( | 183 | return TrackInstruction<std::pair<BufferInfo, u64>>( |
| 184 | state, pos, | 184 | state, pos, |
| 185 | [brx_tracked_register](auto instr, auto& opcode) { | 185 | [brx_tracked_register](auto instr, const auto& opcode) { |
| 186 | return opcode.GetId() == OpCode::Id::LD_C && | 186 | return opcode.GetId() == OpCode::Id::LD_C && |
| 187 | instr.gpr0.Value() == brx_tracked_register && | 187 | instr.gpr0.Value() == brx_tracked_register && |
| 188 | instr.ld_c.type.Value() == Tegra::Shader::UniformType::Single; | 188 | instr.ld_c.type.Value() == Tegra::Shader::UniformType::Single; |
| 189 | }, | 189 | }, |
| 190 | [](auto instr, auto& opcode) { | 190 | [](auto instr, const auto& opcode) { |
| 191 | const BufferInfo info = {static_cast<u32>(instr.cbuf36.index.Value()), | 191 | const BufferInfo info = {static_cast<u32>(instr.cbuf36.index.Value()), |
| 192 | static_cast<u32>(instr.cbuf36.GetOffset())}; | 192 | static_cast<u32>(instr.cbuf36.GetOffset())}; |
| 193 | return std::make_pair(info, instr.gpr8.Value()); | 193 | return std::make_pair(info, instr.gpr8.Value()); |
| @@ -197,22 +197,23 @@ std::optional<std::pair<BufferInfo, u64>> TrackLDC(const CFGRebuildState& state, | |||
| 197 | std::optional<u64> TrackSHLRegister(const CFGRebuildState& state, u32& pos, | 197 | std::optional<u64> TrackSHLRegister(const CFGRebuildState& state, u32& pos, |
| 198 | u64 ldc_tracked_register) { | 198 | u64 ldc_tracked_register) { |
| 199 | return TrackInstruction<u64>(state, pos, | 199 | return TrackInstruction<u64>(state, pos, |
| 200 | [ldc_tracked_register](auto instr, auto& opcode) { | 200 | [ldc_tracked_register](auto instr, const auto& opcode) { |
| 201 | return opcode.GetId() == OpCode::Id::SHL_IMM && | 201 | return opcode.GetId() == OpCode::Id::SHL_IMM && |
| 202 | instr.gpr0.Value() == ldc_tracked_register; | 202 | instr.gpr0.Value() == ldc_tracked_register; |
| 203 | }, | 203 | }, |
| 204 | [](auto instr, auto&) { return instr.gpr8.Value(); }); | 204 | [](auto instr, const auto&) { return instr.gpr8.Value(); }); |
| 205 | } | 205 | } |
| 206 | 206 | ||
| 207 | std::optional<u32> TrackIMNMXValue(const CFGRebuildState& state, u32& pos, | 207 | std::optional<u32> TrackIMNMXValue(const CFGRebuildState& state, u32& pos, |
| 208 | u64 shl_tracked_register) { | 208 | u64 shl_tracked_register) { |
| 209 | return TrackInstruction<u32>( | 209 | return TrackInstruction<u32>(state, pos, |
| 210 | state, pos, | 210 | [shl_tracked_register](auto instr, const auto& opcode) { |
| 211 | [shl_tracked_register](auto instr, auto& opcode) { | 211 | return opcode.GetId() == OpCode::Id::IMNMX_IMM && |
| 212 | return opcode.GetId() == OpCode::Id::IMNMX_IMM && | 212 | instr.gpr0.Value() == shl_tracked_register; |
| 213 | instr.gpr0.Value() == shl_tracked_register; | 213 | }, |
| 214 | }, | 214 | [](auto instr, const auto&) { |
| 215 | [](auto instr, auto&) { return static_cast<u32>(instr.alu.GetSignedImm20_20() + 1); }); | 215 | return static_cast<u32>(instr.alu.GetSignedImm20_20() + 1); |
| 216 | }); | ||
| 216 | } | 217 | } |
| 217 | 218 | ||
| 218 | std::optional<BranchIndirectInfo> TrackBranchIndirectInfo(const CFGRebuildState& state, u32 pos) { | 219 | std::optional<BranchIndirectInfo> TrackBranchIndirectInfo(const CFGRebuildState& state, u32 pos) { |