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-rw-r--r--src/video_core/command_processor.cpp80
1 files changed, 40 insertions, 40 deletions
diff --git a/src/video_core/command_processor.cpp b/src/video_core/command_processor.cpp
index 2a1c885a7..f2e3aee85 100644
--- a/src/video_core/command_processor.cpp
+++ b/src/video_core/command_processor.cpp
@@ -60,6 +60,46 @@ static inline void WritePicaReg(u32 id, u32 value, u32 mask) {
60 GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::P3D); 60 GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::P3D);
61 break; 61 break;
62 62
63 // Load default vertex input attributes
64 case PICA_REG_INDEX_WORKAROUND(vs_default_attributes_setup.set_value[0], 0x233):
65 case PICA_REG_INDEX_WORKAROUND(vs_default_attributes_setup.set_value[1], 0x234):
66 case PICA_REG_INDEX_WORKAROUND(vs_default_attributes_setup.set_value[2], 0x235):
67 {
68 // TODO: Does actual hardware indeed keep an intermediate buffer or does
69 // it directly write the values?
70 default_attr_write_buffer[default_attr_counter++] = value;
71
72 // Default attributes are written in a packed format such that four float24 values are encoded in
73 // three 32-bit numbers. We write to internal memory once a full such vector is
74 // written.
75 if (default_attr_counter >= 3) {
76 default_attr_counter = 0;
77
78 auto& setup = regs.vs_default_attributes_setup;
79
80 if (setup.index >= 16) {
81 LOG_ERROR(HW_GPU, "Invalid VS default attribute index %d", (int)setup.index);
82 break;
83 }
84
85 Math::Vec4<float24>& attribute = g_state.vs.default_attributes[setup.index];
86
87 // NOTE: The destination component order indeed is "backwards"
88 attribute.w = float24::FromRawFloat24(default_attr_write_buffer[0] >> 8);
89 attribute.z = float24::FromRawFloat24(((default_attr_write_buffer[0] & 0xFF) << 16) | ((default_attr_write_buffer[1] >> 16) & 0xFFFF));
90 attribute.y = float24::FromRawFloat24(((default_attr_write_buffer[1] & 0xFFFF) << 8) | ((default_attr_write_buffer[2] >> 24) & 0xFF));
91 attribute.x = float24::FromRawFloat24(default_attr_write_buffer[2] & 0xFFFFFF);
92
93 LOG_TRACE(HW_GPU, "Set default VS attribute %x to (%f %f %f %f)", (int)setup.index,
94 attribute.x.ToFloat32(), attribute.y.ToFloat32(), attribute.z.ToFloat32(),
95 attribute.w.ToFloat32());
96
97 // TODO: Verify that this actually modifies the register!
98 setup.index = setup.index + 1;
99 }
100 break;
101 }
102
63 case PICA_REG_INDEX_WORKAROUND(command_buffer.trigger[0], 0x23c): 103 case PICA_REG_INDEX_WORKAROUND(command_buffer.trigger[0], 0x23c):
64 case PICA_REG_INDEX_WORKAROUND(command_buffer.trigger[1], 0x23d): 104 case PICA_REG_INDEX_WORKAROUND(command_buffer.trigger[1], 0x23d):
65 { 105 {
@@ -351,46 +391,6 @@ static inline void WritePicaReg(u32 id, u32 value, u32 mask) {
351 break; 391 break;
352 } 392 }
353 393
354 // Load default vertex input attributes
355 case PICA_REG_INDEX_WORKAROUND(vs_default_attributes_setup.set_value[0], 0x233):
356 case PICA_REG_INDEX_WORKAROUND(vs_default_attributes_setup.set_value[1], 0x234):
357 case PICA_REG_INDEX_WORKAROUND(vs_default_attributes_setup.set_value[2], 0x235):
358 {
359 // TODO: Does actual hardware indeed keep an intermediate buffer or does
360 // it directly write the values?
361 default_attr_write_buffer[default_attr_counter++] = value;
362
363 // Default attributes are written in a packed format such that four float24 values are encoded in
364 // three 32-bit numbers. We write to internal memory once a full such vector is
365 // written.
366 if (default_attr_counter >= 3) {
367 default_attr_counter = 0;
368
369 auto& setup = regs.vs_default_attributes_setup;
370
371 if (setup.index >= 16) {
372 LOG_ERROR(HW_GPU, "Invalid VS default attribute index %d", (int)setup.index);
373 break;
374 }
375
376 Math::Vec4<float24>& attribute = g_state.vs.default_attributes[setup.index];
377
378 // NOTE: The destination component order indeed is "backwards"
379 attribute.w = float24::FromRawFloat24(default_attr_write_buffer[0] >> 8);
380 attribute.z = float24::FromRawFloat24(((default_attr_write_buffer[0] & 0xFF) << 16) | ((default_attr_write_buffer[1] >> 16) & 0xFFFF));
381 attribute.y = float24::FromRawFloat24(((default_attr_write_buffer[1] & 0xFFFF) << 8) | ((default_attr_write_buffer[2] >> 24) & 0xFF));
382 attribute.x = float24::FromRawFloat24(default_attr_write_buffer[2] & 0xFFFFFF);
383
384 LOG_TRACE(HW_GPU, "Set default VS attribute %x to (%f %f %f %f)", (int)setup.index,
385 attribute.x.ToFloat32(), attribute.y.ToFloat32(), attribute.z.ToFloat32(),
386 attribute.w.ToFloat32());
387
388 // TODO: Verify that this actually modifies the register!
389 setup.index = setup.index + 1;
390 }
391 break;
392 }
393
394 // Load shader program code 394 // Load shader program code
395 case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[0], 0x2cc): 395 case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[0], 0x2cc):
396 case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[1], 0x2cd): 396 case PICA_REG_INDEX_WORKAROUND(vs_program.set_word[1], 0x2cd):
HIC SVNT DRACONES