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-rw-r--r--src/core/arm/arm_interface.h3
-rw-r--r--src/core/arm/dynarmic/arm_dynarmic.cpp2
-rw-r--r--src/core/arm/unicorn/arm_unicorn.cpp4
3 files changed, 0 insertions, 9 deletions
diff --git a/src/core/arm/arm_interface.h b/src/core/arm/arm_interface.h
index 8416e73b0..a8273bb1c 100644
--- a/src/core/arm/arm_interface.h
+++ b/src/core/arm/arm_interface.h
@@ -20,9 +20,6 @@ public:
20 u64 cpsr; 20 u64 cpsr;
21 std::array<u128, 32> fpu_registers; 21 std::array<u128, 32> fpu_registers;
22 u64 fpscr; 22 u64 fpscr;
23
24 // TODO(bunnei): Fix once we have proper support for tpidrro_el0, etc. in the JIT
25 VAddr tls_address;
26 }; 23 };
27 24
28 /// Runs the CPU until an event happens 25 /// Runs the CPU until an event happens
diff --git a/src/core/arm/dynarmic/arm_dynarmic.cpp b/src/core/arm/dynarmic/arm_dynarmic.cpp
index 3572ee7b9..4417c6da4 100644
--- a/src/core/arm/dynarmic/arm_dynarmic.cpp
+++ b/src/core/arm/dynarmic/arm_dynarmic.cpp
@@ -203,7 +203,6 @@ void ARM_Dynarmic::SaveContext(ARM_Interface::ThreadContext& ctx) {
203 ctx.cpsr = jit->GetPstate(); 203 ctx.cpsr = jit->GetPstate();
204 ctx.fpu_registers = jit->GetVectors(); 204 ctx.fpu_registers = jit->GetVectors();
205 ctx.fpscr = jit->GetFpcr(); 205 ctx.fpscr = jit->GetFpcr();
206 ctx.tls_address = cb->tpidrro_el0;
207} 206}
208 207
209void ARM_Dynarmic::LoadContext(const ARM_Interface::ThreadContext& ctx) { 208void ARM_Dynarmic::LoadContext(const ARM_Interface::ThreadContext& ctx) {
@@ -213,7 +212,6 @@ void ARM_Dynarmic::LoadContext(const ARM_Interface::ThreadContext& ctx) {
213 jit->SetPstate(static_cast<u32>(ctx.cpsr)); 212 jit->SetPstate(static_cast<u32>(ctx.cpsr));
214 jit->SetVectors(ctx.fpu_registers); 213 jit->SetVectors(ctx.fpu_registers);
215 jit->SetFpcr(static_cast<u32>(ctx.fpscr)); 214 jit->SetFpcr(static_cast<u32>(ctx.fpscr));
216 cb->tpidrro_el0 = ctx.tls_address;
217} 215}
218 216
219void ARM_Dynarmic::PrepareReschedule() { 217void ARM_Dynarmic::PrepareReschedule() {
diff --git a/src/core/arm/unicorn/arm_unicorn.cpp b/src/core/arm/unicorn/arm_unicorn.cpp
index d2d699e9b..b7afd9ed8 100644
--- a/src/core/arm/unicorn/arm_unicorn.cpp
+++ b/src/core/arm/unicorn/arm_unicorn.cpp
@@ -220,8 +220,6 @@ void ARM_Unicorn::SaveContext(ARM_Interface::ThreadContext& ctx) {
220 220
221 CHECKED(uc_reg_read_batch(uc, uregs, tregs, 31)); 221 CHECKED(uc_reg_read_batch(uc, uregs, tregs, 31));
222 222
223 ctx.tls_address = GetTlsAddress();
224
225 for (int i = 0; i < 32; ++i) { 223 for (int i = 0; i < 32; ++i) {
226 uregs[i] = UC_ARM64_REG_Q0 + i; 224 uregs[i] = UC_ARM64_REG_Q0 + i;
227 tregs[i] = &ctx.fpu_registers[i]; 225 tregs[i] = &ctx.fpu_registers[i];
@@ -249,8 +247,6 @@ void ARM_Unicorn::LoadContext(const ARM_Interface::ThreadContext& ctx) {
249 247
250 CHECKED(uc_reg_write_batch(uc, uregs, tregs, 31)); 248 CHECKED(uc_reg_write_batch(uc, uregs, tregs, 31));
251 249
252 SetTlsAddress(ctx.tls_address);
253
254 for (auto i = 0; i < 32; ++i) { 250 for (auto i = 0; i < 32; ++i) {
255 uregs[i] = UC_ARM64_REG_Q0 + i; 251 uregs[i] = UC_ARM64_REG_Q0 + i;
256 tregs[i] = (void*)&ctx.fpu_registers[i]; 252 tregs[i] = (void*)&ctx.fpu_registers[i];