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-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp90
-rw-r--r--src/core/arm/interpreter/armsupp.cpp229
-rw-r--r--src/core/arm/skyeye_common/arm_regformat.h33
-rw-r--r--src/core/arm/skyeye_common/armdefs.h1
4 files changed, 265 insertions, 88 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index 88eb49e34..b0efd7194 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -4761,94 +4761,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
4761 if (inst_cream->Rd == 15) { 4761 if (inst_cream->Rd == 15) {
4762 DEBUG_MSG; 4762 DEBUG_MSG;
4763 } else { 4763 } else {
4764 if (inst_cream->cp_num == 15) { 4764 if (inst_cream->cp_num == 15)
4765 if (CRn == 1 && CRm == 0 && OPCODE_2 == 0) { 4765 WriteCP15Register(cpu, RD, CRn, OPCODE_1, CRm, OPCODE_2);
4766 CP15_REG(CP15_CONTROL) = RD;
4767 } else if (CRn == 1 && CRm == 0 && OPCODE_2 == 1) {
4768 CP15_REG(CP15_AUXILIARY_CONTROL) = RD;
4769 } else if (CRn == 1 && CRm == 0 && OPCODE_2 == 2) {
4770 CP15_REG(CP15_COPROCESSOR_ACCESS_CONTROL) = RD;
4771 } else if (CRn == 2 && CRm == 0 && OPCODE_2 == 0) {
4772 CP15_REG(CP15_TRANSLATION_BASE_TABLE_0) = RD;
4773 } else if (CRn == 2 && CRm == 0 && OPCODE_2 == 1) {
4774 CP15_REG(CP15_TRANSLATION_BASE_TABLE_1) = RD;
4775 } else if (CRn == 2 && CRm == 0 && OPCODE_2 == 2) {
4776 CP15_REG(CP15_TRANSLATION_BASE_CONTROL) = RD;
4777 } else if (CRn == 3 && CRm == 0 && OPCODE_2 == 0) {
4778 CP15_REG(CP15_DOMAIN_ACCESS_CONTROL) = RD;
4779 } else if(CRn == MMU_CACHE_OPS){
4780 //LOG_WARNING(Core_ARM11, "cache operations have not implemented.");
4781 } else if(CRn == MMU_TLB_OPS){
4782 switch (CRm) {
4783 case 5: // ITLB
4784 switch(OPCODE_2) {
4785 case 0: // Invalidate all
4786 LOG_DEBUG(Core_ARM11, "{TLB} [INSN] invalidate all");
4787 break;
4788 case 1: // Invalidate by MVA
4789 LOG_DEBUG(Core_ARM11, "{TLB} [INSN] invalidate by mva");
4790 break;
4791 case 2: // Invalidate by asid
4792 LOG_DEBUG(Core_ARM11, "{TLB} [INSN] invalidate by asid");
4793 break;
4794 default:
4795 break;
4796 }
4797
4798 break;
4799 case 6: // DTLB
4800 switch(OPCODE_2){
4801 case 0: // Invalidate all
4802 LOG_DEBUG(Core_ARM11, "{TLB} [DATA] invalidate all");
4803 break;
4804 case 1: // Invalidate by MVA
4805 LOG_DEBUG(Core_ARM11, "{TLB} [DATA] invalidate by mva");
4806 break;
4807 case 2: // Invalidate by asid
4808 LOG_DEBUG(Core_ARM11, "{TLB} [DATA] invalidate by asid");
4809 break;
4810 default:
4811 break;
4812 }
4813 break;
4814 case 7: // UNIFILED TLB
4815 switch(OPCODE_2){
4816 case 0: // invalidate all
4817 LOG_DEBUG(Core_ARM11, "{TLB} [UNIFILED] invalidate all");
4818 break;
4819 case 1: // Invalidate by MVA
4820 LOG_DEBUG(Core_ARM11, "{TLB} [UNIFILED] invalidate by mva");
4821 break;
4822 case 2: // Invalidate by asid
4823 LOG_DEBUG(Core_ARM11, "{TLB} [UNIFILED] invalidate by asid");
4824 break;
4825 default:
4826 break;
4827 }
4828 break;
4829 default:
4830 break;
4831 }
4832 } else if(CRn == MMU_PID) {
4833 if(OPCODE_2 == 0) {
4834 CP15_REG(CP15_PID) = RD;
4835 } else if(OPCODE_2 == 1) {
4836 CP15_REG(CP15_CONTEXT_ID) = RD;
4837 } else if (OPCODE_2 == 2) {
4838 CP15_REG(CP15_THREAD_UPRW) = RD;
4839 } else if(OPCODE_2 == 3) {
4840 if (InAPrivilegedMode(cpu))
4841 CP15_REG(CP15_THREAD_URO) = RD;
4842 } else if (OPCODE_2 == 4) {
4843 if (InAPrivilegedMode(cpu))
4844 CP15_REG(CP15_THREAD_PRW) = RD;
4845 } else {
4846 LOG_ERROR(Core_ARM11, "mmu_mcr wrote UNKNOWN - reg %d", CRn);
4847 }
4848 } else {
4849 LOG_ERROR(Core_ARM11, "mcr CRn=%d, CRm=%d OP2=%d is not implemented", CRn, CRm, OPCODE_2);
4850 }
4851 }
4852 } 4766 }
4853 } 4767 }
4854 cpu->Reg[15] += GET_INST_SIZE(cpu); 4768 cpu->Reg[15] += GET_INST_SIZE(cpu);
diff --git a/src/core/arm/interpreter/armsupp.cpp b/src/core/arm/interpreter/armsupp.cpp
index ad713b561..6a11a5804 100644
--- a/src/core/arm/interpreter/armsupp.cpp
+++ b/src/core/arm/interpreter/armsupp.cpp
@@ -409,3 +409,232 @@ u32 ReadCP15Register(ARMul_State* cpu, u32 crn, u32 opcode_1, u32 crm, u32 opcod
409 LOG_ERROR(Core_ARM11, "MRC CRn=%u, CRm=%u, OP1=%u OP2=%u is not implemented. Returning zero.", crn, crm, opcode_1, opcode_2); 409 LOG_ERROR(Core_ARM11, "MRC CRn=%u, CRm=%u, OP1=%u OP2=%u is not implemented. Returning zero.", crn, crm, opcode_1, opcode_2);
410 return 0; 410 return 0;
411} 411}
412
413// Write to the CP15 registers. Used with implementation of the MCR instruction.
414// Note that since the 3DS does not have the hypervisor extensions, these registers
415// are not implemented.
416void WriteCP15Register(ARMul_State* cpu, u32 value, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2)
417{
418 if (InAPrivilegedMode(cpu))
419 {
420 if (crn == 1 && opcode_1 == 0 && crm == 0)
421 {
422 if (opcode_2 == 0)
423 cpu->CP15[CP15(CP15_CONTROL)] = value;
424 else if (opcode_2 == 1)
425 cpu->CP15[CP15(CP15_AUXILIARY_CONTROL)] = value;
426 else if (opcode_2 == 2)
427 cpu->CP15[CP15(CP15_COPROCESSOR_ACCESS_CONTROL)] = value;
428 }
429 else if (crn == 2 && opcode_1 == 0 && crm == 0)
430 {
431 if (opcode_2 == 0)
432 cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_0)] = value;
433 else if (opcode_2 == 1)
434 cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_1)] = value;
435 else if (opcode_2 == 2)
436 cpu->CP15[CP15(CP15_TRANSLATION_BASE_CONTROL)] = value;
437 }
438 else if (crn == 3 && opcode_1 == 0 && crm == 0 && opcode_2 == 0)
439 {
440 cpu->CP15[CP15(CP15_DOMAIN_ACCESS_CONTROL)] = value;
441 }
442 else if (crn == 5 && opcode_1 == 0 && crm == 0)
443 {
444 if (opcode_2 == 0)
445 cpu->CP15[CP15(CP15_FAULT_STATUS)] = value;
446 else if (opcode_2 == 1)
447 cpu->CP15[CP15(CP15_INSTR_FAULT_STATUS)] = value;
448 }
449 else if (crn == 6 && opcode_1 == 0 && crm == 0)
450 {
451 if (opcode_2 == 0)
452 cpu->CP15[CP15(CP15_FAULT_ADDRESS)] = value;
453 else if (opcode_2 == 1)
454 cpu->CP15[CP15(CP15_WFAR)] = value;
455 }
456 else if (crn == 7 && opcode_1 == 0)
457 {
458 LOG_WARNING(Core_ARM11, "Cache operations are not fully implemented.");
459
460 if (crm == 0 && opcode_2 == 4)
461 {
462 cpu->CP15[CP15(CP15_WAIT_FOR_INTERRUPT)] = value;
463 }
464 else if (crm == 4 && opcode_2 == 0)
465 {
466 // NOTE: Not entirely accurate. This should do permission checks.
467 cpu->CP15[CP15(CP15_PHYS_ADDRESS)] = Memory::VirtualToPhysicalAddress(value);
468 }
469 else if (crm == 5)
470 {
471 if (opcode_2 == 0)
472 cpu->CP15[CP15(CP15_INVALIDATE_INSTR_CACHE)] = value;
473 else if (opcode_2 == 1)
474 cpu->CP15[CP15(CP15_INVALIDATE_INSTR_CACHE_USING_MVA)] = value;
475 else if (opcode_2 == 2)
476 cpu->CP15[CP15(CP15_INVALIDATE_INSTR_CACHE_USING_INDEX)] = value;
477 else if (opcode_2 == 6)
478 cpu->CP15[CP15(CP15_FLUSH_BRANCH_TARGET_CACHE)] = value;
479 else if (opcode_2 == 7)
480 cpu->CP15[CP15(CP15_FLUSH_BRANCH_TARGET_CACHE_ENTRY)] = value;
481 }
482 else if (crm == 6)
483 {
484 if (opcode_2 == 0)
485 cpu->CP15[CP15(CP15_INVALIDATE_DATA_CACHE)] = value;
486 else if (opcode_2 == 1)
487 cpu->CP15[CP15(CP15_INVALIDATE_DATA_CACHE_LINE_USING_MVA)] = value;
488 else if (opcode_2 == 2)
489 cpu->CP15[CP15(CP15_INVALIDATE_DATA_CACHE_LINE_USING_INDEX)] = value;
490 }
491 else if (crm == 7 && opcode_2 == 0)
492 {
493 cpu->CP15[CP15(CP15_INVALIDATE_DATA_AND_INSTR_CACHE)] = value;
494 }
495 else if (crm == 10)
496 {
497 if (opcode_2 == 0)
498 cpu->CP15[CP15(CP15_CLEAN_DATA_CACHE)] = value;
499 else if (opcode_2 == 1)
500 cpu->CP15[CP15(CP15_CLEAN_DATA_CACHE_LINE_USING_MVA)] = value;
501 else if (opcode_2 == 2)
502 cpu->CP15[CP15(CP15_CLEAN_DATA_CACHE_LINE_USING_INDEX)] = value;
503 }
504 else if (crm == 14)
505 {
506 if (opcode_2 == 0)
507 cpu->CP15[CP15(CP15_CLEAN_AND_INVALIDATE_DATA_CACHE)] = value;
508 else if (opcode_2 == 1)
509 cpu->CP15[CP15(CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_MVA)] = value;
510 else if (opcode_2 == 2)
511 cpu->CP15[CP15(CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_INDEX)] = value;
512 }
513 }
514 else if (crn == 8 && opcode_1 == 0)
515 {
516 LOG_WARNING(Core_ARM11, "TLB operations not fully implemented.");
517
518 if (crm == 5)
519 {
520 if (opcode_2 == 0)
521 cpu->CP15[CP15(CP15_INVALIDATE_ITLB)] = value;
522 else if (opcode_2 == 1)
523 cpu->CP15[CP15(CP15_INVALIDATE_ITLB_SINGLE_ENTRY)] = value;
524 else if (opcode_2 == 2)
525 cpu->CP15[CP15(CP15_INVALIDATE_ITLB_ENTRY_ON_ASID_MATCH)] = value;
526 else if (opcode_2 == 3)
527 cpu->CP15[CP15(CP15_INVALIDATE_ITLB_ENTRY_ON_MVA)] = value;
528 }
529 else if (crm == 6)
530 {
531 if (opcode_2 == 0)
532 cpu->CP15[CP15(CP15_INVALIDATE_DTLB)] = value;
533 else if (opcode_2 == 1)
534 cpu->CP15[CP15(CP15_INVALIDATE_DTLB_SINGLE_ENTRY)] = value;
535 else if (opcode_2 == 2)
536 cpu->CP15[CP15(CP15_INVALIDATE_DTLB_ENTRY_ON_ASID_MATCH)] = value;
537 else if (opcode_2 == 3)
538 cpu->CP15[CP15(CP15_INVALIDATE_DTLB_ENTRY_ON_MVA)] = value;
539 }
540 else if (crm == 7)
541 {
542 if (opcode_2 == 0)
543 cpu->CP15[CP15(CP15_INVALIDATE_UTLB)] = value;
544 else if (opcode_2 == 1)
545 cpu->CP15[CP15(CP15_INVALIDATE_UTLB_SINGLE_ENTRY)] = value;
546 else if (opcode_2 == 2)
547 cpu->CP15[CP15(CP15_INVALIDATE_UTLB_ENTRY_ON_ASID_MATCH)] = value;
548 else if (opcode_2 == 3)
549 cpu->CP15[CP15(CP15_INVALIDATE_UTLB_ENTRY_ON_MVA)] = value;
550 }
551 }
552 else if (crn == 9 && opcode_1 == 0 && crm == 0 && opcode_2 == 0)
553 {
554 cpu->CP15[CP15(CP15_DATA_CACHE_LOCKDOWN)] = value;
555 }
556 else if (crn == 10 && opcode_1 == 0)
557 {
558 if (crm == 0 && opcode_2 == 0)
559 {
560 cpu->CP15[CP15(CP15_TLB_LOCKDOWN)] = value;
561 }
562 else if (crm == 2)
563 {
564 if (opcode_2 == 0)
565 cpu->CP15[CP15(CP15_PRIMARY_REGION_REMAP)] = value;
566 else if (opcode_2 == 1)
567 cpu->CP15[CP15(CP15_NORMAL_REGION_REMAP)] = value;
568 }
569 }
570 else if (crn == 13 && opcode_1 == 0 && crm == 0)
571 {
572 if (opcode_2 == 0)
573 cpu->CP15[CP15(CP15_PID)] = value;
574 else if (opcode_2 == 1)
575 cpu->CP15[CP15(CP15_CONTEXT_ID)] = value;
576 else if (opcode_2 == 3)
577 cpu->CP15[CP15(CP15_THREAD_URO)] = value;
578 else if (opcode_2 == 4)
579 cpu->CP15[CP15(CP15_THREAD_PRW)] = value;
580 }
581 else if (crn == 15)
582 {
583 if (opcode_1 == 0 && crm == 12)
584 {
585 if (opcode_2 == 0)
586 cpu->CP15[CP15(CP15_PERFORMANCE_MONITOR_CONTROL)] = value;
587 else if (opcode_2 == 1)
588 cpu->CP15[CP15(CP15_CYCLE_COUNTER)] = value;
589 else if (opcode_2 == 2)
590 cpu->CP15[CP15(CP15_COUNT_0)] = value;
591 else if (opcode_2 == 3)
592 cpu->CP15[CP15(CP15_COUNT_1)] = value;
593 }
594 else if (opcode_1 == 5)
595 {
596 if (crm == 4)
597 {
598 if (opcode_2 == 2)
599 cpu->CP15[CP15(CP15_READ_MAIN_TLB_LOCKDOWN_ENTRY)] = value;
600 else if (opcode_2 == 4)
601 cpu->CP15[CP15(CP15_WRITE_MAIN_TLB_LOCKDOWN_ENTRY)] = value;
602 }
603 else if (crm == 5 && opcode_2 == 2)
604 {
605 cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS)] = value;
606 }
607 else if (crm == 6 && opcode_2 == 2)
608 {
609 cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS)] = value;
610 }
611 else if (crm == 7 && opcode_2 == 2)
612 {
613 cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE)] = value;
614 }
615 }
616 else if (opcode_1 == 7 && crm == 1 && opcode_2 == 0)
617 {
618 cpu->CP15[CP15(CP15_TLB_DEBUG_CONTROL)] = value;
619 }
620 }
621 }
622
623 // Unprivileged registers
624 if (crn == 7 && opcode_1 == 0 && crm == 5 && opcode_2 == 4)
625 {
626 cpu->CP15[CP15(CP15_FLUSH_PREFETCH_BUFFER)] = value;
627 }
628 else if (crn == 7 && opcode_1 == 0 && crm == 10)
629 {
630 if (opcode_2 == 4)
631 cpu->CP15[CP15(CP15_DATA_SYNC_BARRIER)] = value;
632 else if (opcode_2 == 5)
633 cpu->CP15[CP15(CP15_DATA_MEMORY_BARRIER)] = value;
634
635 }
636 else if (crn == 13 && opcode_1 == 0 && crm == 0 && opcode_2 == 2)
637 {
638 cpu->CP15[CP15(CP15_THREAD_UPRW)] = value;
639 }
640}
diff --git a/src/core/arm/skyeye_common/arm_regformat.h b/src/core/arm/skyeye_common/arm_regformat.h
index fb5b70f1e..c232376e0 100644
--- a/src/core/arm/skyeye_common/arm_regformat.h
+++ b/src/core/arm/skyeye_common/arm_regformat.h
@@ -105,7 +105,40 @@ enum {
105 CP15_IFAR, 105 CP15_IFAR,
106 106
107 // c7 - Cache operation registers 107 // c7 - Cache operation registers
108 CP15_WAIT_FOR_INTERRUPT,
108 CP15_PHYS_ADDRESS, 109 CP15_PHYS_ADDRESS,
110 CP15_INVALIDATE_INSTR_CACHE,
111 CP15_INVALIDATE_INSTR_CACHE_USING_MVA,
112 CP15_INVALIDATE_INSTR_CACHE_USING_INDEX,
113 CP15_FLUSH_PREFETCH_BUFFER,
114 CP15_FLUSH_BRANCH_TARGET_CACHE,
115 CP15_FLUSH_BRANCH_TARGET_CACHE_ENTRY,
116 CP15_INVALIDATE_DATA_CACHE,
117 CP15_INVALIDATE_DATA_CACHE_LINE_USING_MVA,
118 CP15_INVALIDATE_DATA_CACHE_LINE_USING_INDEX,
119 CP15_INVALIDATE_DATA_AND_INSTR_CACHE,
120 CP15_CLEAN_DATA_CACHE,
121 CP15_CLEAN_DATA_CACHE_LINE_USING_MVA,
122 CP15_CLEAN_DATA_CACHE_LINE_USING_INDEX,
123 CP15_DATA_SYNC_BARRIER,
124 CP15_DATA_MEMORY_BARRIER,
125 CP15_CLEAN_AND_INVALIDATE_DATA_CACHE,
126 CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_MVA,
127 CP15_CLEAN_AND_INVALIDATE_DATA_CACHE_LINE_USING_INDEX,
128
129 // c8 - TLB operations
130 CP15_INVALIDATE_ITLB,
131 CP15_INVALIDATE_ITLB_SINGLE_ENTRY,
132 CP15_INVALIDATE_ITLB_ENTRY_ON_ASID_MATCH,
133 CP15_INVALIDATE_ITLB_ENTRY_ON_MVA,
134 CP15_INVALIDATE_DTLB,
135 CP15_INVALIDATE_DTLB_SINGLE_ENTRY,
136 CP15_INVALIDATE_DTLB_ENTRY_ON_ASID_MATCH,
137 CP15_INVALIDATE_DTLB_ENTRY_ON_MVA,
138 CP15_INVALIDATE_UTLB,
139 CP15_INVALIDATE_UTLB_SINGLE_ENTRY,
140 CP15_INVALIDATE_UTLB_ENTRY_ON_ASID_MATCH,
141 CP15_INVALIDATE_UTLB_ENTRY_ON_MVA,
109 142
110 // c9 - Data cache lockdown register 143 // c9 - Data cache lockdown register
111 CP15_DATA_CACHE_LOCKDOWN, 144 CP15_DATA_CACHE_LOCKDOWN,
diff --git a/src/core/arm/skyeye_common/armdefs.h b/src/core/arm/skyeye_common/armdefs.h
index 14f2a39d1..d5b0242c3 100644
--- a/src/core/arm/skyeye_common/armdefs.h
+++ b/src/core/arm/skyeye_common/armdefs.h
@@ -360,3 +360,4 @@ extern bool InBigEndianMode(ARMul_State*);
360extern bool InAPrivilegedMode(ARMul_State*); 360extern bool InAPrivilegedMode(ARMul_State*);
361 361
362extern u32 ReadCP15Register(ARMul_State* cpu, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2); 362extern u32 ReadCP15Register(ARMul_State* cpu, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2);
363extern void WriteCP15Register(ARMul_State* cpu, u32 value, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2);
HIC SVNT DRACONES