diff options
Diffstat (limited to '')
| -rw-r--r-- | src/video_core/shader/decode/arithmetic_integer_immediate.cpp | 35 |
1 files changed, 19 insertions, 16 deletions
diff --git a/src/video_core/shader/decode/arithmetic_integer_immediate.cpp b/src/video_core/shader/decode/arithmetic_integer_immediate.cpp index 73880db0e..2a30aab2b 100644 --- a/src/video_core/shader/decode/arithmetic_integer_immediate.cpp +++ b/src/video_core/shader/decode/arithmetic_integer_immediate.cpp | |||
| @@ -28,23 +28,26 @@ u32 ShaderIR::DecodeArithmeticIntegerImmediate(NodeBlock& bb, u32 pc) { | |||
| 28 | case OpCode::Id::IADD32I: { | 28 | case OpCode::Id::IADD32I: { |
| 29 | UNIMPLEMENTED_IF_MSG(instr.iadd32i.saturate, "IADD32I saturation is not implemented"); | 29 | UNIMPLEMENTED_IF_MSG(instr.iadd32i.saturate, "IADD32I saturation is not implemented"); |
| 30 | 30 | ||
| 31 | op_a = GetOperandAbsNegInteger(op_a, false, instr.iadd32i.negate_a, true); | 31 | op_a = GetOperandAbsNegInteger(std::move(op_a), false, instr.iadd32i.negate_a != 0, true); |
| 32 | 32 | ||
| 33 | const Node value = Operation(OperationCode::IAdd, PRECISE, op_a, op_b); | 33 | Node value = Operation(OperationCode::IAdd, PRECISE, std::move(op_a), std::move(op_b)); |
| 34 | 34 | ||
| 35 | SetInternalFlagsFromInteger(bb, value, instr.op_32.generates_cc); | 35 | SetInternalFlagsFromInteger(bb, value, instr.op_32.generates_cc != 0); |
| 36 | SetRegister(bb, instr.gpr0, value); | 36 | SetRegister(bb, instr.gpr0, std::move(value)); |
| 37 | break; | 37 | break; |
| 38 | } | 38 | } |
| 39 | case OpCode::Id::LOP32I: { | 39 | case OpCode::Id::LOP32I: { |
| 40 | if (instr.alu.lop32i.invert_a) | 40 | if (instr.alu.lop32i.invert_a) { |
| 41 | op_a = Operation(OperationCode::IBitwiseNot, NO_PRECISE, op_a); | 41 | op_a = Operation(OperationCode::IBitwiseNot, NO_PRECISE, std::move(op_a)); |
| 42 | } | ||
| 42 | 43 | ||
| 43 | if (instr.alu.lop32i.invert_b) | 44 | if (instr.alu.lop32i.invert_b) { |
| 44 | op_b = Operation(OperationCode::IBitwiseNot, NO_PRECISE, op_b); | 45 | op_b = Operation(OperationCode::IBitwiseNot, NO_PRECISE, std::move(op_b)); |
| 46 | } | ||
| 45 | 47 | ||
| 46 | WriteLogicOperation(bb, instr.gpr0, instr.alu.lop32i.operation, op_a, op_b, | 48 | WriteLogicOperation(bb, instr.gpr0, instr.alu.lop32i.operation, std::move(op_a), |
| 47 | PredicateResultMode::None, Pred::UnusedIndex, instr.op_32.generates_cc); | 49 | std::move(op_b), PredicateResultMode::None, Pred::UnusedIndex, |
| 50 | instr.op_32.generates_cc != 0); | ||
| 48 | break; | 51 | break; |
| 49 | } | 52 | } |
| 50 | default: | 53 | default: |
| @@ -58,14 +61,14 @@ u32 ShaderIR::DecodeArithmeticIntegerImmediate(NodeBlock& bb, u32 pc) { | |||
| 58 | void ShaderIR::WriteLogicOperation(NodeBlock& bb, Register dest, LogicOperation logic_op, Node op_a, | 61 | void ShaderIR::WriteLogicOperation(NodeBlock& bb, Register dest, LogicOperation logic_op, Node op_a, |
| 59 | Node op_b, PredicateResultMode predicate_mode, Pred predicate, | 62 | Node op_b, PredicateResultMode predicate_mode, Pred predicate, |
| 60 | bool sets_cc) { | 63 | bool sets_cc) { |
| 61 | const Node result = [&]() { | 64 | Node result = [&] { |
| 62 | switch (logic_op) { | 65 | switch (logic_op) { |
| 63 | case LogicOperation::And: | 66 | case LogicOperation::And: |
| 64 | return Operation(OperationCode::IBitwiseAnd, PRECISE, op_a, op_b); | 67 | return Operation(OperationCode::IBitwiseAnd, PRECISE, std::move(op_a), std::move(op_b)); |
| 65 | case LogicOperation::Or: | 68 | case LogicOperation::Or: |
| 66 | return Operation(OperationCode::IBitwiseOr, PRECISE, op_a, op_b); | 69 | return Operation(OperationCode::IBitwiseOr, PRECISE, std::move(op_a), std::move(op_b)); |
| 67 | case LogicOperation::Xor: | 70 | case LogicOperation::Xor: |
| 68 | return Operation(OperationCode::IBitwiseXor, PRECISE, op_a, op_b); | 71 | return Operation(OperationCode::IBitwiseXor, PRECISE, std::move(op_a), std::move(op_b)); |
| 69 | case LogicOperation::PassB: | 72 | case LogicOperation::PassB: |
| 70 | return op_b; | 73 | return op_b; |
| 71 | default: | 74 | default: |
| @@ -84,8 +87,8 @@ void ShaderIR::WriteLogicOperation(NodeBlock& bb, Register dest, LogicOperation | |||
| 84 | return; | 87 | return; |
| 85 | case PredicateResultMode::NotZero: { | 88 | case PredicateResultMode::NotZero: { |
| 86 | // Set the predicate to true if the result is not zero. | 89 | // Set the predicate to true if the result is not zero. |
| 87 | const Node compare = Operation(OperationCode::LogicalINotEqual, result, Immediate(0)); | 90 | Node compare = Operation(OperationCode::LogicalINotEqual, std::move(result), Immediate(0)); |
| 88 | SetPredicate(bb, static_cast<u64>(predicate), compare); | 91 | SetPredicate(bb, static_cast<u64>(predicate), std::move(compare)); |
| 89 | break; | 92 | break; |
| 90 | } | 93 | } |
| 91 | default: | 94 | default: |