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| author | 2023-09-22 09:55:54 -0400 | |
|---|---|---|
| committer | 2023-09-22 09:55:54 -0400 | |
| commit | fda08cbbb03edf4315c9c59da261644390967079 (patch) | |
| tree | c8391a33a15892da71fb50e176ea5537116d65d5 /src | |
| parent | Merge pull request #11564 from t895/overlay-inset-fix (diff) | |
| parent | Fix DMA engine register offsets (diff) | |
| download | yuzu-fda08cbbb03edf4315c9c59da261644390967079.tar.gz yuzu-fda08cbbb03edf4315c9c59da261644390967079.tar.xz yuzu-fda08cbbb03edf4315c9c59da261644390967079.zip | |
Merge pull request #11563 from Kelebek1/dma_regs
Fix DMA engine register offsets
Diffstat (limited to 'src')
| -rw-r--r-- | src/video_core/engines/maxwell_dma.cpp | 5 | ||||
| -rw-r--r-- | src/video_core/engines/maxwell_dma.h | 55 |
2 files changed, 32 insertions, 28 deletions
diff --git a/src/video_core/engines/maxwell_dma.cpp b/src/video_core/engines/maxwell_dma.cpp index da8eab7ee..279f0daa1 100644 --- a/src/video_core/engines/maxwell_dma.cpp +++ b/src/video_core/engines/maxwell_dma.cpp | |||
| @@ -109,10 +109,11 @@ void MaxwellDMA::Launch() { | |||
| 109 | const bool is_const_a_dst = regs.remap_const.dst_x == RemapConst::Swizzle::CONST_A; | 109 | const bool is_const_a_dst = regs.remap_const.dst_x == RemapConst::Swizzle::CONST_A; |
| 110 | if (regs.launch_dma.remap_enable != 0 && is_const_a_dst) { | 110 | if (regs.launch_dma.remap_enable != 0 && is_const_a_dst) { |
| 111 | ASSERT(regs.remap_const.component_size_minus_one == 3); | 111 | ASSERT(regs.remap_const.component_size_minus_one == 3); |
| 112 | accelerate.BufferClear(regs.offset_out, regs.line_length_in, regs.remap_consta_value); | 112 | accelerate.BufferClear(regs.offset_out, regs.line_length_in, |
| 113 | regs.remap_const.remap_consta_value); | ||
| 113 | read_buffer.resize_destructive(regs.line_length_in * sizeof(u32)); | 114 | read_buffer.resize_destructive(regs.line_length_in * sizeof(u32)); |
| 114 | std::span<u32> span(reinterpret_cast<u32*>(read_buffer.data()), regs.line_length_in); | 115 | std::span<u32> span(reinterpret_cast<u32*>(read_buffer.data()), regs.line_length_in); |
| 115 | std::ranges::fill(span, regs.remap_consta_value); | 116 | std::ranges::fill(span, regs.remap_const.remap_consta_value); |
| 116 | memory_manager.WriteBlockUnsafe(regs.offset_out, | 117 | memory_manager.WriteBlockUnsafe(regs.offset_out, |
| 117 | reinterpret_cast<u8*>(read_buffer.data()), | 118 | reinterpret_cast<u8*>(read_buffer.data()), |
| 118 | regs.line_length_in * sizeof(u32)); | 119 | regs.line_length_in * sizeof(u32)); |
diff --git a/src/video_core/engines/maxwell_dma.h b/src/video_core/engines/maxwell_dma.h index 69e26cb32..1a43e24b6 100644 --- a/src/video_core/engines/maxwell_dma.h +++ b/src/video_core/engines/maxwell_dma.h | |||
| @@ -214,14 +214,15 @@ public: | |||
| 214 | NO_WRITE = 6, | 214 | NO_WRITE = 6, |
| 215 | }; | 215 | }; |
| 216 | 216 | ||
| 217 | PackedGPUVAddr address; | 217 | u32 remap_consta_value; |
| 218 | u32 remap_constb_value; | ||
| 218 | 219 | ||
| 219 | union { | 220 | union { |
| 221 | BitField<0, 12, u32> dst_components_raw; | ||
| 220 | BitField<0, 3, Swizzle> dst_x; | 222 | BitField<0, 3, Swizzle> dst_x; |
| 221 | BitField<4, 3, Swizzle> dst_y; | 223 | BitField<4, 3, Swizzle> dst_y; |
| 222 | BitField<8, 3, Swizzle> dst_z; | 224 | BitField<8, 3, Swizzle> dst_z; |
| 223 | BitField<12, 3, Swizzle> dst_w; | 225 | BitField<12, 3, Swizzle> dst_w; |
| 224 | BitField<0, 12, u32> dst_components_raw; | ||
| 225 | BitField<16, 2, u32> component_size_minus_one; | 226 | BitField<16, 2, u32> component_size_minus_one; |
| 226 | BitField<20, 2, u32> num_src_components_minus_one; | 227 | BitField<20, 2, u32> num_src_components_minus_one; |
| 227 | BitField<24, 2, u32> num_dst_components_minus_one; | 228 | BitField<24, 2, u32> num_dst_components_minus_one; |
| @@ -274,55 +275,57 @@ private: | |||
| 274 | struct Regs { | 275 | struct Regs { |
| 275 | union { | 276 | union { |
| 276 | struct { | 277 | struct { |
| 277 | u32 reserved[0x40]; | 278 | INSERT_PADDING_BYTES_NOINIT(0x100); |
| 278 | u32 nop; | 279 | u32 nop; |
| 279 | u32 reserved01[0xf]; | 280 | INSERT_PADDING_BYTES_NOINIT(0x3C); |
| 280 | u32 pm_trigger; | 281 | u32 pm_trigger; |
| 281 | u32 reserved02[0x3f]; | 282 | INSERT_PADDING_BYTES_NOINIT(0xFC); |
| 282 | Semaphore semaphore; | 283 | Semaphore semaphore; |
| 283 | u32 reserved03[0x2]; | 284 | INSERT_PADDING_BYTES_NOINIT(0x8); |
| 284 | RenderEnable render_enable; | 285 | RenderEnable render_enable; |
| 285 | PhysMode src_phys_mode; | 286 | PhysMode src_phys_mode; |
| 286 | PhysMode dst_phys_mode; | 287 | PhysMode dst_phys_mode; |
| 287 | u32 reserved04[0x26]; | 288 | INSERT_PADDING_BYTES_NOINIT(0x98); |
| 288 | LaunchDMA launch_dma; | 289 | LaunchDMA launch_dma; |
| 289 | u32 reserved05[0x3f]; | 290 | INSERT_PADDING_BYTES_NOINIT(0xFC); |
| 290 | PackedGPUVAddr offset_in; | 291 | PackedGPUVAddr offset_in; |
| 291 | PackedGPUVAddr offset_out; | 292 | PackedGPUVAddr offset_out; |
| 292 | s32 pitch_in; | 293 | s32 pitch_in; |
| 293 | s32 pitch_out; | 294 | s32 pitch_out; |
| 294 | u32 line_length_in; | 295 | u32 line_length_in; |
| 295 | u32 line_count; | 296 | u32 line_count; |
| 296 | u32 reserved06[0xb6]; | 297 | INSERT_PADDING_BYTES_NOINIT(0x2E0); |
| 297 | u32 remap_consta_value; | ||
| 298 | u32 remap_constb_value; | ||
| 299 | RemapConst remap_const; | 298 | RemapConst remap_const; |
| 300 | DMA::Parameters dst_params; | 299 | DMA::Parameters dst_params; |
| 301 | u32 reserved07[0x1]; | 300 | INSERT_PADDING_BYTES_NOINIT(0x4); |
| 302 | DMA::Parameters src_params; | 301 | DMA::Parameters src_params; |
| 303 | u32 reserved08[0x275]; | 302 | INSERT_PADDING_BYTES_NOINIT(0x9D4); |
| 304 | u32 pm_trigger_end; | 303 | u32 pm_trigger_end; |
| 305 | u32 reserved09[0x3ba]; | 304 | INSERT_PADDING_BYTES_NOINIT(0xEE8); |
| 306 | }; | 305 | }; |
| 307 | std::array<u32, NUM_REGS> reg_array; | 306 | std::array<u32, NUM_REGS> reg_array; |
| 308 | }; | 307 | }; |
| 309 | } regs{}; | 308 | } regs{}; |
| 309 | static_assert(sizeof(Regs) == NUM_REGS * 4); | ||
| 310 | 310 | ||
| 311 | #define ASSERT_REG_POSITION(field_name, position) \ | 311 | #define ASSERT_REG_POSITION(field_name, position) \ |
| 312 | static_assert(offsetof(MaxwellDMA::Regs, field_name) == position * 4, \ | 312 | static_assert(offsetof(MaxwellDMA::Regs, field_name) == position, \ |
| 313 | "Field " #field_name " has invalid position") | 313 | "Field " #field_name " has invalid position") |
| 314 | 314 | ||
| 315 | ASSERT_REG_POSITION(launch_dma, 0xC0); | 315 | ASSERT_REG_POSITION(semaphore, 0x240); |
| 316 | ASSERT_REG_POSITION(offset_in, 0x100); | 316 | ASSERT_REG_POSITION(render_enable, 0x254); |
| 317 | ASSERT_REG_POSITION(offset_out, 0x102); | 317 | ASSERT_REG_POSITION(src_phys_mode, 0x260); |
| 318 | ASSERT_REG_POSITION(pitch_in, 0x104); | 318 | ASSERT_REG_POSITION(launch_dma, 0x300); |
| 319 | ASSERT_REG_POSITION(pitch_out, 0x105); | 319 | ASSERT_REG_POSITION(offset_in, 0x400); |
| 320 | ASSERT_REG_POSITION(line_length_in, 0x106); | 320 | ASSERT_REG_POSITION(offset_out, 0x408); |
| 321 | ASSERT_REG_POSITION(line_count, 0x107); | 321 | ASSERT_REG_POSITION(pitch_in, 0x410); |
| 322 | ASSERT_REG_POSITION(remap_const, 0x1C0); | 322 | ASSERT_REG_POSITION(pitch_out, 0x414); |
| 323 | ASSERT_REG_POSITION(dst_params, 0x1C3); | 323 | ASSERT_REG_POSITION(line_length_in, 0x418); |
| 324 | ASSERT_REG_POSITION(src_params, 0x1CA); | 324 | ASSERT_REG_POSITION(line_count, 0x41C); |
| 325 | 325 | ASSERT_REG_POSITION(remap_const, 0x700); | |
| 326 | ASSERT_REG_POSITION(dst_params, 0x70C); | ||
| 327 | ASSERT_REG_POSITION(src_params, 0x728); | ||
| 328 | ASSERT_REG_POSITION(pm_trigger_end, 0x1114); | ||
| 326 | #undef ASSERT_REG_POSITION | 329 | #undef ASSERT_REG_POSITION |
| 327 | }; | 330 | }; |
| 328 | 331 | ||