diff options
| author | 2019-03-27 07:11:50 -0400 | |
|---|---|---|
| committer | 2019-04-08 11:35:18 -0400 | |
| commit | fd4e994de3196dfdd2a3f2caf4ca8934e719c296 (patch) | |
| tree | 3012794162498bd6caabd7fbf3c3841ae80d6f5a /src | |
| parent | Implement TXQ_B (diff) | |
| download | yuzu-fd4e994de3196dfdd2a3f2caf4ca8934e719c296.tar.gz yuzu-fd4e994de3196dfdd2a3f2caf4ca8934e719c296.tar.xz yuzu-fd4e994de3196dfdd2a3f2caf4ca8934e719c296.zip | |
Refactor GetTextureCode and GetTexCode to use an optional instead of optional parameters
Diffstat (limited to 'src')
| -rw-r--r-- | src/video_core/shader/decode/texture.cpp | 47 | ||||
| -rw-r--r-- | src/video_core/shader/shader_ir.h | 20 |
2 files changed, 33 insertions, 34 deletions
diff --git a/src/video_core/shader/decode/texture.cpp b/src/video_core/shader/decode/texture.cpp index 3eac75bef..5d670b24e 100644 --- a/src/video_core/shader/decode/texture.cpp +++ b/src/video_core/shader/decode/texture.cpp | |||
| @@ -54,7 +54,7 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) { | |||
| 54 | const auto process_mode = instr.tex.GetTextureProcessMode(); | 54 | const auto process_mode = instr.tex.GetTextureProcessMode(); |
| 55 | WriteTexInstructionFloat( | 55 | WriteTexInstructionFloat( |
| 56 | bb, instr, | 56 | bb, instr, |
| 57 | GetTexCode(instr, texture_type, process_mode, depth_compare, is_array, is_aoffi)); | 57 | GetTexCode(instr, texture_type, process_mode, depth_compare, is_array, is_aoffi, {})); |
| 58 | break; | 58 | break; |
| 59 | } | 59 | } |
| 60 | case OpCode::Id::TEX_B: { | 60 | case OpCode::Id::TEX_B: { |
| @@ -69,9 +69,9 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) { | |||
| 69 | const bool is_array = instr.tex_b.array != 0; | 69 | const bool is_array = instr.tex_b.array != 0; |
| 70 | const bool depth_compare = instr.tex_b.UsesMiscMode(TextureMiscMode::DC); | 70 | const bool depth_compare = instr.tex_b.UsesMiscMode(TextureMiscMode::DC); |
| 71 | const auto process_mode = instr.tex_b.GetTextureProcessMode(); | 71 | const auto process_mode = instr.tex_b.GetTextureProcessMode(); |
| 72 | WriteTexInstructionFloat(bb, instr, | 72 | WriteTexInstructionFloat( |
| 73 | GetTexCode(instr, texture_type, process_mode, depth_compare, | 73 | bb, instr, |
| 74 | is_array, true, instr.gpr20)); | 74 | GetTexCode(instr, texture_type, process_mode, depth_compare, is_array, {instr.gpr20})); |
| 75 | break; | 75 | break; |
| 76 | } | 76 | } |
| 77 | case OpCode::Id::TEXS: { | 77 | case OpCode::Id::TEXS: { |
| @@ -162,10 +162,10 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) { | |||
| 162 | // Sadly, not all texture instructions specify the type of texture their sampler | 162 | // Sadly, not all texture instructions specify the type of texture their sampler |
| 163 | // uses. This must be fixed at a later instance. | 163 | // uses. This must be fixed at a later instance. |
| 164 | const auto& sampler = | 164 | const auto& sampler = |
| 165 | !is_bindless | 165 | is_bindless |
| 166 | ? GetSampler(instr.sampler, Tegra::Shader::TextureType::Texture2D, false, false) | 166 | ? GetBindlessSampler(instr.gpr8, Tegra::Shader::TextureType::Texture2D, false, |
| 167 | : GetBindlessSampler(instr.gpr8, Tegra::Shader::TextureType::Texture2D, false, | 167 | false) |
| 168 | false); | 168 | : GetSampler(instr.sampler, Tegra::Shader::TextureType::Texture2D, false, false); |
| 169 | 169 | ||
| 170 | u32 indexer = 0; | 170 | u32 indexer = 0; |
| 171 | switch (instr.txq.query_type) { | 171 | switch (instr.txq.query_type) { |
| @@ -203,9 +203,9 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) { | |||
| 203 | 203 | ||
| 204 | auto texture_type = instr.tmml.texture_type.Value(); | 204 | auto texture_type = instr.tmml.texture_type.Value(); |
| 205 | const bool is_array = instr.tmml.array != 0; | 205 | const bool is_array = instr.tmml.array != 0; |
| 206 | const auto& sampler = !is_bindless | 206 | const auto& sampler = is_bindless |
| 207 | ? GetSampler(instr.sampler, texture_type, is_array, false) | 207 | ? GetBindlessSampler(instr.gpr20, texture_type, is_array, false) |
| 208 | : GetBindlessSampler(instr.gpr20, texture_type, is_array, false); | 208 | : GetSampler(instr.sampler, texture_type, is_array, false); |
| 209 | 209 | ||
| 210 | std::vector<Node> coords; | 210 | std::vector<Node> coords; |
| 211 | 211 | ||
| @@ -381,25 +381,26 @@ void ShaderIR::WriteTexsInstructionHalfFloat(NodeBlock& bb, Instruction instr, | |||
| 381 | 381 | ||
| 382 | Node4 ShaderIR::GetTextureCode(Instruction instr, TextureType texture_type, | 382 | Node4 ShaderIR::GetTextureCode(Instruction instr, TextureType texture_type, |
| 383 | TextureProcessMode process_mode, std::vector<Node> coords, | 383 | TextureProcessMode process_mode, std::vector<Node> coords, |
| 384 | Node array, Node depth_compare, u32 bias_offset, std::vector<Node> aoffi, bool is_bindless, | 384 | Node array, Node depth_compare, u32 bias_offset, std::vector<Node> aoffi, std::optional<Tegra::Shader::Register> bindless_reg) { |
| 385 | Register bindless_reg) { | ||
| 386 | const bool is_array = array; | 385 | const bool is_array = array; |
| 387 | const bool is_shadow = depth_compare; | 386 | const bool is_shadow = depth_compare; |
| 387 | const bool is_bindless = bindless_reg.has_value(); | ||
| 388 | 388 | ||
| 389 | UNIMPLEMENTED_IF_MSG((texture_type == TextureType::Texture3D && (is_array || is_shadow)) || | 389 | UNIMPLEMENTED_IF_MSG((texture_type == TextureType::Texture3D && (is_array || is_shadow)) || |
| 390 | (texture_type == TextureType::TextureCube && is_array && is_shadow), | 390 | (texture_type == TextureType::TextureCube && is_array && is_shadow), |
| 391 | "This method is not supported."); | 391 | "This method is not supported."); |
| 392 | 392 | ||
| 393 | const auto& sampler = !is_bindless | 393 | const auto& sampler = is_bindless |
| 394 | ? GetSampler(instr.sampler, texture_type, is_array, is_shadow) | 394 | ? GetBindlessSampler(*bindless_reg, texture_type, is_array, is_shadow) |
| 395 | : GetBindlessSampler(bindless_reg, texture_type, is_array, is_shadow); | 395 | : GetSampler(instr.sampler, texture_type, is_array, is_shadow); |
| 396 | 396 | ||
| 397 | const bool lod_needed = process_mode == TextureProcessMode::LZ || | 397 | const bool lod_needed = process_mode == TextureProcessMode::LZ || |
| 398 | process_mode == TextureProcessMode::LL || | 398 | process_mode == TextureProcessMode::LL || |
| 399 | process_mode == TextureProcessMode::LLA; | 399 | process_mode == TextureProcessMode::LLA; |
| 400 | 400 | ||
| 401 | // LOD selection (either via bias or explicit textureLod) not supported in GL for | 401 | // LOD selection (either via bias or explicit textureLod) not |
| 402 | // sampler2DArrayShadow and samplerCubeArrayShadow. | 402 | // supported in GL for sampler2DArrayShadow and |
| 403 | // samplerCubeArrayShadow. | ||
| 403 | const bool gl_lod_supported = | 404 | const bool gl_lod_supported = |
| 404 | !((texture_type == Tegra::Shader::TextureType::Texture2D && is_array && is_shadow) || | 405 | !((texture_type == Tegra::Shader::TextureType::Texture2D && is_array && is_shadow) || |
| 405 | (texture_type == Tegra::Shader::TextureType::TextureCube && is_array && is_shadow)); | 406 | (texture_type == Tegra::Shader::TextureType::TextureCube && is_array && is_shadow)); |
| @@ -417,8 +418,9 @@ Node4 ShaderIR::GetTextureCode(Instruction instr, TextureType texture_type, | |||
| 417 | lod = Immediate(0.0f); | 418 | lod = Immediate(0.0f); |
| 418 | break; | 419 | break; |
| 419 | case TextureProcessMode::LB: | 420 | case TextureProcessMode::LB: |
| 420 | // If present, lod or bias are always stored in the register indexed by the gpr20 | 421 | // If present, lod or bias are always stored in the register |
| 421 | // field with an offset depending on the usage of the other registers | 422 | // indexed by the gpr20 field with an offset depending on the |
| 423 | // usage of the other registers | ||
| 422 | bias = GetRegister(instr.gpr20.Value() + bias_offset); | 424 | bias = GetRegister(instr.gpr20.Value() + bias_offset); |
| 423 | break; | 425 | break; |
| 424 | case TextureProcessMode::LL: | 426 | case TextureProcessMode::LL: |
| @@ -442,7 +444,7 @@ Node4 ShaderIR::GetTextureCode(Instruction instr, TextureType texture_type, | |||
| 442 | 444 | ||
| 443 | Node4 ShaderIR::GetTexCode(Instruction instr, TextureType texture_type, | 445 | Node4 ShaderIR::GetTexCode(Instruction instr, TextureType texture_type, |
| 444 | TextureProcessMode process_mode, bool depth_compare, bool is_array, | 446 | TextureProcessMode process_mode, bool depth_compare, bool is_array, |
| 445 | bool is_aoffi, bool is_bindless, Register bindless_reg) { | 447 | bool is_aoffi, std::optional<Tegra::Shader::Register> bindless_reg) { |
| 446 | const bool lod_bias_enabled{ | 448 | const bool lod_bias_enabled{ |
| 447 | (process_mode != TextureProcessMode::None && process_mode != TextureProcessMode::LZ)}; | 449 | (process_mode != TextureProcessMode::None && process_mode != TextureProcessMode::LZ)}; |
| 448 | 450 | ||
| @@ -482,8 +484,7 @@ Node4 ShaderIR::GetTexCode(Instruction instr, TextureType texture_type, | |||
| 482 | dc = GetRegister(parameter_register++); | 484 | dc = GetRegister(parameter_register++); |
| 483 | } | 485 | } |
| 484 | 486 | ||
| 485 | return GetTextureCode(instr, texture_type, process_mode, coords, array, dc, 0, aoffi, is_bindless, | 487 | return GetTextureCode(instr, texture_type, process_mode, coords, array, dc, 0, aoffi, bindless_reg); |
| 486 | bindless_reg); | ||
| 487 | } | 488 | } |
| 488 | 489 | ||
| 489 | Node4 ShaderIR::GetTexsCode(Instruction instr, TextureType texture_type, | 490 | Node4 ShaderIR::GetTexsCode(Instruction instr, TextureType texture_type, |
diff --git a/src/video_core/shader/shader_ir.h b/src/video_core/shader/shader_ir.h index ed321cfe5..11495799f 100644 --- a/src/video_core/shader/shader_ir.h +++ b/src/video_core/shader/shader_ir.h | |||
| @@ -769,11 +769,10 @@ private: | |||
| 769 | void WriteTexsInstructionHalfFloat(NodeBlock& bb, Tegra::Shader::Instruction instr, | 769 | void WriteTexsInstructionHalfFloat(NodeBlock& bb, Tegra::Shader::Instruction instr, |
| 770 | const Node4& components); | 770 | const Node4& components); |
| 771 | 771 | ||
| 772 | Node4 GetTexCode( | 772 | Node4 GetTexCode(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type, |
| 773 | Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type, | 773 | Tegra::Shader::TextureProcessMode process_mode, bool depth_compare, |
| 774 | Tegra::Shader::TextureProcessMode process_mode, bool depth_compare, bool is_array, | 774 | bool is_array, bool is_aoffi, |
| 775 | bool is_aoffi, bool is_bindless = false, | 775 | std::optional<Tegra::Shader::Register> bindless_reg); |
| 776 | Tegra::Shader::Register bindless_reg = static_cast<Tegra::Shader::Register>(0)); | ||
| 777 | 776 | ||
| 778 | Node4 GetTexsCode(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type, | 777 | Node4 GetTexsCode(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type, |
| 779 | Tegra::Shader::TextureProcessMode process_mode, bool depth_compare, | 778 | Tegra::Shader::TextureProcessMode process_mode, bool depth_compare, |
| @@ -790,12 +789,11 @@ private: | |||
| 790 | bool lod_bias_enabled, std::size_t max_coords, std::size_t max_inputs); | 789 | bool lod_bias_enabled, std::size_t max_coords, std::size_t max_inputs); |
| 791 | 790 | ||
| 792 | std::vector<Node> GetAoffiCoordinates(Node aoffi_reg, std::size_t coord_count, bool is_tld4); | 791 | std::vector<Node> GetAoffiCoordinates(Node aoffi_reg, std::size_t coord_count, bool is_tld4); |
| 793 | 792 | ||
| 794 | Node4 GetTextureCode( | 793 | Node4 GetTextureCode(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type, |
| 795 | Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type, | 794 | Tegra::Shader::TextureProcessMode process_mode, std::vector<Node> coords, |
| 796 | Tegra::Shader::TextureProcessMode process_mode, std::vector<Node> coords, Node array, | 795 | Node array, Node depth_compare, u32 bias_offset, std::vector<Node> aoffi, |
| 797 | Node depth_compare, u32 bias_offset, std::vector<Node> aoffi, bool is_bindless = false, | 796 | std::optional<Tegra::Shader::Register> bindless_reg); |
| 798 | Tegra::Shader::Register bindless_reg = static_cast<Tegra::Shader::Register>(0)); | ||
| 799 | 797 | ||
| 800 | Node GetVideoOperand(Node op, bool is_chunk, bool is_signed, Tegra::Shader::VideoType type, | 798 | Node GetVideoOperand(Node op, bool is_chunk, bool is_signed, Tegra::Shader::VideoType type, |
| 801 | u64 byte_height); | 799 | u64 byte_height); |