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authorGravatar Chin2015-01-04 13:59:34 -0500
committerGravatar chinhodado2015-01-19 16:01:06 -0500
commitfa8e6272c8c080b41a809eb064ab5ba6c8680b1e (patch)
treecde74447bf04d5293810043e74c8e5e767e4a892 /src
parentMerge pull request #383 from zhuowei/shared_page (diff)
downloadyuzu-fa8e6272c8c080b41a809eb064ab5ba6c8680b1e.tar.gz
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Cleanup: Logging in Core
Diffstat (limited to 'src')
-rw-r--r--src/core/arm/interpreter/armemu.cpp57
-rw-r--r--src/core/arm/skyeye_common/vfp/vfp.cpp155
-rw-r--r--src/core/arm/skyeye_common/vfp/vfp.h11
-rw-r--r--src/core/arm/skyeye_common/vfp/vfpdouble.cpp85
-rw-r--r--src/core/arm/skyeye_common/vfp/vfpinstr.cpp332
5 files changed, 157 insertions, 483 deletions
diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp
index 12166bf79..adc5c3a05 100644
--- a/src/core/arm/interpreter/armemu.cpp
+++ b/src/core/arm/interpreter/armemu.cpp
@@ -340,7 +340,6 @@ ARMword ARMul_Debug(ARMul_State * state, ARMword pc, ARMword instr)
340 mem_Dbugdump(); 340 mem_Dbugdump();
341 }*/ 341 }*/
342 342
343
344 /*if (pc == 0x0022D168) 343 /*if (pc == 0x0022D168)
345 { 344 {
346 int j = 0; 345 int j = 0;
@@ -1117,7 +1116,6 @@ ARMul_Emulate26 (ARMul_State * state)
1117 1116
1118//chy 2003-08-24 now #if 0 .... #endif process cp14, cp15.reg14, I disable it... 1117//chy 2003-08-24 now #if 0 .... #endif process cp14, cp15.reg14, I disable it...
1119 1118
1120
1121 /* Actual execution of instructions begins here. */ 1119 /* Actual execution of instructions begins here. */
1122 /* If the condition codes don't match, stop here. */ 1120 /* If the condition codes don't match, stop here. */
1123 if (temp) { 1121 if (temp) {
@@ -1178,8 +1176,6 @@ mainswitch:
1178 tmp_rd = ((ARMword)(data << (31 - lsb)) >> (31 - lsb)); 1176 tmp_rd = ((ARMword)(data << (31 - lsb)) >> (31 - lsb));
1179 dst = ((data >> msb) << (msb - lsb)); 1177 dst = ((data >> msb) << (msb - lsb));
1180 dst = (dst << lsb) | tmp_rd; 1178 dst = (dst << lsb) | tmp_rd;
1181 /*SKYEYE_DBG("BFC instr: msb = %d, lsb = %d, Rd[%d] : 0x%x, dst = 0x%x\n",
1182 msb, lsb, Rd, state->Reg[Rd], dst);*/
1183 goto donext; 1179 goto donext;
1184 } // bfc instr 1180 } // bfc instr
1185 else if (((msb >= lsb) && (msb < 32))) { 1181 else if (((msb >= lsb) && (msb < 32))) {
@@ -1189,8 +1185,6 @@ mainswitch:
1189 tmp_rd = ((ARMword)(data << (31 - lsb)) >> (31 - lsb)); 1185 tmp_rd = ((ARMword)(data << (31 - lsb)) >> (31 - lsb));
1190 dst = ((data >> msb) << (msb - lsb)) | tmp_rn; 1186 dst = ((data >> msb) << (msb - lsb)) | tmp_rn;
1191 dst = (dst << lsb) | tmp_rd; 1187 dst = (dst << lsb) | tmp_rd;
1192 /*SKYEYE_DBG("BFI instr:msb = %d, lsb = %d, Rd[%d] : 0x%x, Rn[%d]: 0x%x, dst = 0x%x\n",
1193 msb, lsb, Rd, state->Reg[Rd], Rn, state->Reg[Rn], dst);*/
1194 goto donext; 1188 goto donext;
1195 } // bfi instr 1189 } // bfi instr
1196 } 1190 }
@@ -2215,10 +2209,8 @@ mainswitch:
2215 state->currentexvald == (u32)ARMul_ReadWord(state, state->currentexaddr + 4)) 2209 state->currentexvald == (u32)ARMul_ReadWord(state, state->currentexaddr + 4))
2216 enter = true; 2210 enter = true;
2217 2211
2218
2219 //todo bug this and STREXD and LDREXD http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360e/CHDGJGGC.html 2212 //todo bug this and STREXD and LDREXD http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360e/CHDGJGGC.html
2220 2213
2221
2222 if (enter) { 2214 if (enter) {
2223 ARMul_StoreWordN(state, LHS, state->Reg[RHSReg]); 2215 ARMul_StoreWordN(state, LHS, state->Reg[RHSReg]);
2224 ARMul_StoreWordN(state,LHS + 4 , state->Reg[RHSReg + 1]); 2216 ARMul_StoreWordN(state,LHS + 4 , state->Reg[RHSReg + 1]);
@@ -2254,9 +2246,6 @@ mainswitch:
2254 LHPREUPWB (); 2246 LHPREUPWB ();
2255 /* Continue with remaining instruction decoding. */ 2247 /* Continue with remaining instruction decoding. */
2256 2248
2257
2258
2259
2260#endif 2249#endif
2261 dest = DPSRegRHS; 2250 dest = DPSRegRHS;
2262 WRITESDEST (dest); 2251 WRITESDEST (dest);
@@ -2296,7 +2285,6 @@ mainswitch:
2296 temp = LHS + GetLS7RHS (state, instr); 2285 temp = LHS + GetLS7RHS (state, instr);
2297 LoadHalfWord (state, instr, temp, LSIGNED); 2286 LoadHalfWord (state, instr, temp, LSIGNED);
2298 break; 2287 break;
2299
2300 } 2288 }
2301 if (BITS (4, 7) == 0xb) { 2289 if (BITS (4, 7) == 0xb) {
2302 /* LDRH immediate offset, no write-back, up, pre indexed. */ 2290 /* LDRH immediate offset, no write-back, up, pre indexed. */
@@ -2321,7 +2309,6 @@ mainswitch:
2321 } 2309 }
2322 /* LDR immediate offset, no write-back, up, pre indexed. */ 2310 /* LDR immediate offset, no write-back, up, pre indexed. */
2323 LHPREUP (); 2311 LHPREUP ();
2324
2325 } 2312 }
2326 2313
2327#endif 2314#endif
@@ -2342,7 +2329,6 @@ mainswitch:
2342 2329
2343 if (state->currentexval == (u32)ARMul_LoadHalfWord(state, state->currentexaddr))enter = true; 2330 if (state->currentexval == (u32)ARMul_LoadHalfWord(state, state->currentexaddr))enter = true;
2344 2331
2345
2346 //StoreWord(state, lhs, RHS) 2332 //StoreWord(state, lhs, RHS)
2347 if (state->Aborted) { 2333 if (state->Aborted) {
2348 TAKEABORT; 2334 TAKEABORT;
@@ -2396,7 +2382,6 @@ mainswitch:
2396 WRITESDEST (dest); 2382 WRITESDEST (dest);
2397 break; 2383 break;
2398 2384
2399
2400 /* Data Processing Immediate RHS Instructions. */ 2385 /* Data Processing Immediate RHS Instructions. */
2401 2386
2402 case 0x20: /* AND immed */ 2387 case 0x20: /* AND immed */
@@ -2553,8 +2538,6 @@ mainswitch:
2553 dest = BITS(16, 19); 2538 dest = BITS(16, 19);
2554 dest = ((dest<<12) | BITS(0, 11)); 2539 dest = ((dest<<12) | BITS(0, 11));
2555 WRITEDEST(dest); 2540 WRITEDEST(dest);
2556 //SKYEYE_DBG("In %s, line = %d, pc = 0x%x, instr = 0x%x, R[0:11]: 0x%x, R[16:19]: 0x%x, R[%d]:0x%x\n",
2557 // __func__, __LINE__, pc, instr, BITS(0, 11), BITS(16, 19), DESTReg, state->Reg[DESTReg]);
2558 break; 2541 break;
2559 } else { 2542 } else {
2560 UNDEF_Test; 2543 UNDEF_Test;
@@ -2717,7 +2700,6 @@ mainswitch:
2717 WRITESDEST (~rhs); 2700 WRITESDEST (~rhs);
2718 break; 2701 break;
2719 2702
2720
2721 /* Single Data Transfer Immediate RHS Instructions. */ 2703 /* Single Data Transfer Immediate RHS Instructions. */
2722 2704
2723 case 0x40: /* Store Word, No WriteBack, Post Dec, Immed. */ 2705 case 0x40: /* Store Word, No WriteBack, Post Dec, Immed. */
@@ -2849,7 +2831,6 @@ mainswitch:
2849 state->NtransSig = (state->Mode & 3) ? HIGH : LOW; 2831 state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
2850 break; 2832 break;
2851 2833
2852
2853 case 0x50: /* Store Word, No WriteBack, Pre Dec, Immed. */ 2834 case 0x50: /* Store Word, No WriteBack, Pre Dec, Immed. */
2854 (void) StoreWord (state, instr, LHS - LSImmRHS); 2835 (void) StoreWord (state, instr, LHS - LSImmRHS);
2855 break; 2836 break;
@@ -2946,7 +2927,6 @@ mainswitch:
2946 LSBase = temp; 2927 LSBase = temp;
2947 break; 2928 break;
2948 2929
2949
2950 /* Single Data Transfer Register RHS Instructions. */ 2930 /* Single Data Transfer Register RHS Instructions. */
2951 2931
2952 case 0x60: /* Store Word, No WriteBack, Post Dec, Reg. */ 2932 case 0x60: /* Store Word, No WriteBack, Post Dec, Reg. */
@@ -3234,11 +3214,9 @@ mainswitch:
3234 int Rm = 0; 3214 int Rm = 0;
3235 /* utxb */ 3215 /* utxb */
3236 if (BITS(15, 19) == 0xf && BITS(4, 7) == 0x7) { 3216 if (BITS(15, 19) == 0xf && BITS(4, 7) == 0x7) {
3237
3238 Rm = (RHS >> (8 * BITS(10, 11))) & 0xff; 3217 Rm = (RHS >> (8 * BITS(10, 11))) & 0xff;
3239 DEST = Rm; 3218 DEST = Rm;
3240 } 3219 }
3241
3242 } 3220 }
3243#endif 3221#endif
3244 if (BIT (4)) { 3222 if (BIT (4)) {
@@ -3285,7 +3263,6 @@ mainswitch:
3285 state->NtransSig = (state->Mode & 3) ? HIGH : LOW; 3263 state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
3286 break; 3264 break;
3287 3265
3288
3289 case 0x70: /* Store Word, No WriteBack, Pre Dec, Reg. */ 3266 case 0x70: /* Store Word, No WriteBack, Pre Dec, Reg. */
3290 if (BIT (4)) { 3267 if (BIT (4)) {
3291#ifdef MODE32 3268#ifdef MODE32
@@ -3489,7 +3466,6 @@ mainswitch:
3489 LSBase = temp; 3466 LSBase = temp;
3490 break; 3467 break;
3491 3468
3492
3493 /* Multiple Data Transfer Instructions. */ 3469 /* Multiple Data Transfer Instructions. */
3494 3470
3495 case 0x80: /* Store, No WriteBack, Post Dec. */ 3471 case 0x80: /* Store, No WriteBack, Post Dec. */
@@ -3636,7 +3612,6 @@ mainswitch:
3636 LOADSMULT (instr, temp + 4L, temp + LSMNumRegs); 3612 LOADSMULT (instr, temp + 4L, temp + LSMNumRegs);
3637 break; 3613 break;
3638 3614
3639
3640 /* Branch forward. */ 3615 /* Branch forward. */
3641 case 0xa0: 3616 case 0xa0:
3642 case 0xa1: 3617 case 0xa1:
@@ -3650,7 +3625,6 @@ mainswitch:
3650 FLUSHPIPE; 3625 FLUSHPIPE;
3651 break; 3626 break;
3652 3627
3653
3654 /* Branch backward. */ 3628 /* Branch backward. */
3655 case 0xa8: 3629 case 0xa8:
3656 case 0xa9: 3630 case 0xa9:
@@ -3664,7 +3638,6 @@ mainswitch:
3664 FLUSHPIPE; 3638 FLUSHPIPE;
3665 break; 3639 break;
3666 3640
3667
3668 /* Branch and Link forward. */ 3641 /* Branch and Link forward. */
3669 case 0xb0: 3642 case 0xb0:
3670 case 0xb1: 3643 case 0xb1:
@@ -3690,10 +3663,8 @@ mainswitch:
3690 printf("call %08X %08X %s(%08X %08X %08X %08X %08X %08X %08X)\n", state->Reg[14], state->Reg[15], a, state->Reg[0], state->Reg[1], state->Reg[2], state->Reg[3], mem_Read32(state->Reg[13]), mem_Read32(state->Reg[13] - 4),mem_Read32(state->Reg[13] - 8)); 3663 printf("call %08X %08X %s(%08X %08X %08X %08X %08X %08X %08X)\n", state->Reg[14], state->Reg[15], a, state->Reg[0], state->Reg[1], state->Reg[2], state->Reg[3], mem_Read32(state->Reg[13]), mem_Read32(state->Reg[13] - 4),mem_Read32(state->Reg[13] - 8));
3691#endif 3664#endif
3692 3665
3693
3694 break; 3666 break;
3695 3667
3696
3697 /* Branch and Link backward. */ 3668 /* Branch and Link backward. */
3698 case 0xb8: 3669 case 0xb8:
3699 case 0xb9: 3670 case 0xb9:
@@ -3712,18 +3683,14 @@ mainswitch:
3712 state->Reg[15] = pc + 8 + NEGBRANCH; 3683 state->Reg[15] = pc + 8 + NEGBRANCH;
3713 FLUSHPIPE; 3684 FLUSHPIPE;
3714 3685
3715
3716#ifdef callstacker 3686#ifdef callstacker
3717 memset(a, 0, 256); 3687 memset(a, 0, 256);
3718 aufloeser(a, state->Reg[15]); 3688 aufloeser(a, state->Reg[15]);
3719 printf("call %08X %08X %s(%08X %08X %08X %08X %08X %08X %08X)\n", state->Reg[14], state->Reg[15], a, state->Reg[0], state->Reg[1], state->Reg[2], state->Reg[3], mem_Read32(state->Reg[13]), mem_Read32(state->Reg[13] - 4),mem_Read32(state->Reg[13] - 8)); 3689 printf("call %08X %08X %s(%08X %08X %08X %08X %08X %08X %08X)\n", state->Reg[14], state->Reg[15], a, state->Reg[0], state->Reg[1], state->Reg[2], state->Reg[3], mem_Read32(state->Reg[13]), mem_Read32(state->Reg[13] - 4),mem_Read32(state->Reg[13] - 8));
3720#endif 3690#endif
3721 3691
3722
3723
3724 break; 3692 break;
3725 3693
3726
3727 /* Co-Processor Data Transfers. */ 3694 /* Co-Processor Data Transfers. */
3728 case 0xc4: 3695 case 0xc4:
3729 if ((instr & 0x0FF00FF0) == 0xC400B10) { //vmov BIT(0-3), BIT(12-15), BIT(16-20), vmov d0, r0, r0 3696 if ((instr & 0x0FF00FF0) == 0xC400B10) { //vmov BIT(0-3), BIT(12-15), BIT(16-20), vmov d0, r0, r0
@@ -3859,7 +3826,6 @@ mainswitch:
3859 ARMul_LDC (state, instr, lhs); 3826 ARMul_LDC (state, instr, lhs);
3860 break; 3827 break;
3861 3828
3862
3863 /* Co-Processor Register Transfers (MCR) and Data Ops. */ 3829 /* Co-Processor Register Transfers (MCR) and Data Ops. */
3864 3830
3865 case 0xe2: 3831 case 0xe2:
@@ -3891,7 +3857,6 @@ mainswitch:
3891 ARMul_CDP (state, instr); 3857 ARMul_CDP (state, instr);
3892 break; 3858 break;
3893 3859
3894
3895 /* Co-Processor Register Transfers (MRC) and Data Ops. */ 3860 /* Co-Processor Register Transfers (MRC) and Data Ops. */
3896 case 0xe1: 3861 case 0xe1:
3897 case 0xe3: 3862 case 0xe3:
@@ -3916,7 +3881,6 @@ mainswitch:
3916 ARMul_CDP (state, instr); 3881 ARMul_CDP (state, instr);
3917 break; 3882 break;
3918 3883
3919
3920 /* SWI instruction. */ 3884 /* SWI instruction. */
3921 case 0xf0: 3885 case 0xf0:
3922 case 0xf1: 3886 case 0xf1:
@@ -3936,7 +3900,7 @@ mainswitch:
3936 case 0xff: 3900 case 0xff:
3937 //svc_Execute(state, BITS(0, 23)); 3901 //svc_Execute(state, BITS(0, 23));
3938 HLE::CallSVC(instr); 3902 HLE::CallSVC(instr);
3939 3903
3940 break; 3904 break;
3941 } 3905 }
3942 } 3906 }
@@ -4118,7 +4082,6 @@ TEST_EMULATE:
4118 // continue; 4082 // continue;
4119 else if (state->Emulate != RUN) 4083 else if (state->Emulate != RUN)
4120 break; 4084 break;
4121
4122 } 4085 }
4123 4086
4124 while (state->NumInstrsToExecute); 4087 while (state->NumInstrsToExecute);
@@ -4156,7 +4119,6 @@ exit:
4156 static FILE *fd; 4119 static FILE *fd;
4157 4120
4158 /*if (!init) { 4121 /*if (!init) {
4159
4160 fd = fopen("./pc.txt", "w"); 4122 fd = fopen("./pc.txt", "w");
4161 if (!fd) { 4123 if (!fd) {
4162 exit(-1); 4124 exit(-1);
@@ -4725,8 +4687,6 @@ out:
4725 address, DEST); \ 4687 address, DEST); \
4726 } 4688 }
4727 4689
4728
4729
4730 static unsigned 4690 static unsigned
4731 LoadWord (ARMul_State * state, ARMword instr, ARMword address) { 4691 LoadWord (ARMul_State * state, ARMword instr, ARMword address) {
4732 ARMword dest; 4692 ARMword dest;
@@ -5158,7 +5118,6 @@ out:
5158 /*chy 2004-05-23 chy goto end */ 5118 /*chy 2004-05-23 chy goto end */
5159 if (state->Aborted) 5119 if (state->Aborted)
5160 goto L_ldm_makeabort; 5120 goto L_ldm_makeabort;
5161
5162 } 5121 }
5163 5122
5164 if (BIT (15) && !state->Aborted) 5123 if (BIT (15) && !state->Aborted)
@@ -5202,7 +5161,6 @@ L_ldm_makeabort:
5202 LSBase = WBBase; 5161 LSBase = WBBase;
5203 } 5162 }
5204 /* chy 2005-11-24, over */ 5163 /* chy 2005-11-24, over */
5205
5206 } 5164 }
5207 5165
5208 /* This function does the work of loading the registers listed in an LDM 5166 /* This function does the work of loading the registers listed in an LDM
@@ -5405,7 +5363,6 @@ L_ldm_s_makeabort:
5405 //chy 2004-05-23, needn't store other when aborted 5363 //chy 2004-05-23, needn't store other when aborted
5406 if (state->Aborted) 5364 if (state->Aborted)
5407 goto L_stm_takeabort; 5365 goto L_stm_takeabort;
5408
5409 } 5366 }
5410 5367
5411//chy 2004-05-23,should compare the Abort Models 5368//chy 2004-05-23,should compare the Abort Models
@@ -5508,7 +5465,6 @@ L_stm_takeabort:
5508 /* Restore the correct bank. */ 5465 /* Restore the correct bank. */
5509 (void) ARMul_SwitchMode (state, USER26MODE, state->Mode); 5466 (void) ARMul_SwitchMode (state, USER26MODE, state->Mode);
5510 5467
5511
5512//chy 2004-05-23,should compare the Abort Models 5468//chy 2004-05-23,should compare the Abort Models
5513L_stm_s_takeabort: 5469L_stm_s_takeabort:
5514 if (BIT (21) && LHSReg != 15) { 5470 if (BIT (21) && LHSReg != 15) {
@@ -5763,7 +5719,6 @@ L_stm_s_takeabort:
5763 TAKEABORT; 5719 TAKEABORT;
5764 } 5720 }
5765 5721
5766
5767 if (enter) { 5722 if (enter) {
5768 ARMul_StoreByte(state, lhs, RHS); 5723 ARMul_StoreByte(state, lhs, RHS);
5769 state->Reg[DESTReg] = 0; 5724 state->Reg[DESTReg] = 0;
@@ -6285,7 +6240,7 @@ L_stm_s_takeabort:
6285 u32 rm = ((state->Reg[BITS(0, 3)] >> rotation) & 0xFF) | (((state->Reg[BITS(0, 3)] << (32 - rotation)) & 0xFF) & 0xFF); 6240 u32 rm = ((state->Reg[BITS(0, 3)] >> rotation) & 0xFF) | (((state->Reg[BITS(0, 3)] << (32 - rotation)) & 0xFF) & 0xFF);
6286 if (rm & 0x80) 6241 if (rm & 0x80)
6287 rm |= 0xffffff00; 6242 rm |= 0xffffff00;
6288 6243
6289 // SXTB, otherwise SXTAB 6244 // SXTB, otherwise SXTAB
6290 if (BITS(16, 19) == 0xf) 6245 if (BITS(16, 19) == 0xf)
6291 state->Reg[BITS(12, 15)] = rm; 6246 state->Reg[BITS(12, 15)] = rm;
@@ -6371,7 +6326,7 @@ L_stm_s_takeabort:
6371 const s16 max = 0xFFFF >> (16 - num_bits); 6326 const s16 max = 0xFFFF >> (16 - num_bits);
6372 s16 rn_lo = (state->Reg[rn_idx]); 6327 s16 rn_lo = (state->Reg[rn_idx]);
6373 s16 rn_hi = (state->Reg[rn_idx] >> 16); 6328 s16 rn_hi = (state->Reg[rn_idx] >> 16);
6374 6329
6375 if (max < rn_lo) { 6330 if (max < rn_lo) {
6376 rn_lo = max; 6331 rn_lo = max;
6377 SETQ; 6332 SETQ;
@@ -6379,7 +6334,7 @@ L_stm_s_takeabort:
6379 rn_lo = 0; 6334 rn_lo = 0;
6380 SETQ; 6335 SETQ;
6381 } 6336 }
6382 6337
6383 if (max < rn_hi) { 6338 if (max < rn_hi) {
6384 rn_hi = max; 6339 rn_hi = max;
6385 SETQ; 6340 SETQ;
@@ -6387,14 +6342,14 @@ L_stm_s_takeabort:
6387 rn_hi = 0; 6342 rn_hi = 0;
6388 SETQ; 6343 SETQ;
6389 } 6344 }
6390 6345
6391 state->Reg[rd_idx] = (rn_lo & 0xFFFF) | ((rn_hi << 16) & 0xFFFF); 6346 state->Reg[rd_idx] = (rn_lo & 0xFFFF) | ((rn_hi << 16) & 0xFFFF);
6392 return 1; 6347 return 1;
6393 } 6348 }
6394 else if (op2 == 0x03) { 6349 else if (op2 == 0x03) {
6395 const u8 rotate = BITS(10, 11) * 8; 6350 const u8 rotate = BITS(10, 11) * 8;
6396 const u32 rm = ((state->Reg[BITS(0, 3)] >> rotate) & 0xFF) | (((state->Reg[BITS(0, 3)] << (32 - rotate)) & 0xFF) & 0xFF); 6351 const u32 rm = ((state->Reg[BITS(0, 3)] >> rotate) & 0xFF) | (((state->Reg[BITS(0, 3)] << (32 - rotate)) & 0xFF) & 0xFF);
6397 6352
6398 if (BITS(16, 19) == 0xf) 6353 if (BITS(16, 19) == 0xf)
6399 /* UXTB */ 6354 /* UXTB */
6400 state->Reg[BITS(12, 15)] = rm; 6355 state->Reg[BITS(12, 15)] = rm;
diff --git a/src/core/arm/skyeye_common/vfp/vfp.cpp b/src/core/arm/skyeye_common/vfp/vfp.cpp
index 10d640f37..62a2f63ca 100644
--- a/src/core/arm/skyeye_common/vfp/vfp.cpp
+++ b/src/core/arm/skyeye_common/vfp/vfp.cpp
@@ -20,16 +20,11 @@
20 20
21/* Note: this file handles interface with arm core and vfp registers */ 21/* Note: this file handles interface with arm core and vfp registers */
22 22
23/* Opens debug for classic interpreter only */
24//#define DEBUG
25
26#include "common/common.h" 23#include "common/common.h"
27 24
28#include "core/arm/skyeye_common/armdefs.h" 25#include "core/arm/skyeye_common/armdefs.h"
29#include "core/arm/skyeye_common/vfp/vfp.h" 26#include "core/arm/skyeye_common/vfp/vfp.h"
30 27
31#define DEBUG DBG
32
33//ARMul_State* persistent_state; /* function calls from SoftFloat lib don't have an access to ARMul_state. */ 28//ARMul_State* persistent_state; /* function calls from SoftFloat lib don't have an access to ARMul_state. */
34 29
35unsigned VFPInit(ARMul_State* state) 30unsigned VFPInit(ARMul_State* state)
@@ -75,7 +70,7 @@ unsigned VFPMRC(ARMul_State* state, unsigned type, u32 instr, u32* value)
75 return ARMul_DONE; 70 return ARMul_DONE;
76 } 71 }
77 } 72 }
78 DEBUG("Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, CRn %x, CRm %x, OPC_2 %x\n", 73 LOG_WARNING(Core_ARM11, "Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, CRn %x, CRm %x, OPC_2 %x\n",
79 instr, CoProc, OPC_1, Rt, CRn, CRm, OPC_2); 74 instr, CoProc, OPC_1, Rt, CRn, CRm, OPC_2);
80 75
81 return ARMul_CANT; 76 return ARMul_CANT;
@@ -122,7 +117,7 @@ unsigned VFPMCR(ARMul_State* state, unsigned type, u32 instr, u32 value)
122 return ARMul_DONE; 117 return ARMul_DONE;
123 } 118 }
124 } 119 }
125 DEBUG("Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, CRn %x, CRm %x, OPC_2 %x\n", 120 LOG_WARNING(Core_ARM11, "Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, CRn %x, CRm %x, OPC_2 %x\n",
126 instr, CoProc, OPC_1, Rt, CRn, CRm, OPC_2); 121 instr, CoProc, OPC_1, Rt, CRn, CRm, OPC_2);
127 122
128 return ARMul_CANT; 123 return ARMul_CANT;
@@ -152,7 +147,7 @@ unsigned VFPMRRC(ARMul_State* state, unsigned type, u32 instr, u32* value1, u32*
152 return ARMul_DONE; 147 return ARMul_DONE;
153 } 148 }
154 } 149 }
155 DEBUG("Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, Rt2 %x, CRm %x\n", 150 LOG_WARNING(Core_ARM11, "Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, Rt2 %x, CRm %x\n",
156 instr, CoProc, OPC_1, Rt, Rt2, CRm); 151 instr, CoProc, OPC_1, Rt, Rt2, CRm);
157 152
158 return ARMul_CANT; 153 return ARMul_CANT;
@@ -186,7 +181,7 @@ unsigned VFPMCRR(ARMul_State* state, unsigned type, u32 instr, u32 value1, u32 v
186 return ARMul_DONE; 181 return ARMul_DONE;
187 } 182 }
188 } 183 }
189 DEBUG("Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, Rt2 %x, CRm %x\n", 184 LOG_WARNING(Core_ARM11, "Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, Rt2 %x, CRm %x\n",
190 instr, CoProc, OPC_1, Rt, Rt2, CRm); 185 instr, CoProc, OPC_1, Rt, Rt2, CRm);
191 186
192 return ARMul_CANT; 187 return ARMul_CANT;
@@ -208,17 +203,17 @@ unsigned VFPSTC(ARMul_State* state, unsigned type, u32 instr, u32 * value)
208 203
209 /* VSTM */ 204 /* VSTM */
210 if ( (P|U|D|W) == 0 ) { 205 if ( (P|U|D|W) == 0 ) {
211 DEBUG("In %s, UNDEFINED\n", __FUNCTION__); 206 LOG_ERROR(Core_ARM11, "In %s, UNDEFINED\n", __FUNCTION__);
212 exit(-1); 207 exit(-1);
213 } 208 }
214 if (CoProc == 10 || CoProc == 11) { 209 if (CoProc == 10 || CoProc == 11) {
215#if 1 210#if 1
216 if (P == 0 && U == 0 && W == 0) { 211 if (P == 0 && U == 0 && W == 0) {
217 DEBUG("VSTM Related encodings\n"); 212 LOG_ERROR(Core_ARM11, "VSTM Related encodings\n");
218 exit(-1); 213 exit(-1);
219 } 214 }
220 if (P == U && W == 1) { 215 if (P == U && W == 1) {
221 DEBUG("UNDEFINED\n"); 216 LOG_ERROR(Core_ARM11, "UNDEFINED\n");
222 exit(-1); 217 exit(-1);
223 } 218 }
224#endif 219#endif
@@ -235,7 +230,7 @@ unsigned VFPSTC(ARMul_State* state, unsigned type, u32 instr, u32 * value)
235 230
236 return VSTM(state, type, instr, value); 231 return VSTM(state, type, instr, value);
237 } 232 }
238 DEBUG("Can't identify %x, CoProc %x, CRd %x, Rn %x, imm8 %x, P %x, U %x, D %x, W %x\n", 233 LOG_WARNING(Core_ARM11, "Can't identify %x, CoProc %x, CRd %x, Rn %x, imm8 %x, P %x, U %x, D %x, W %x\n",
239 instr, CoProc, CRd, Rn, imm8, P, U, D, W); 234 instr, CoProc, CRd, Rn, imm8, P, U, D, W);
240 235
241 return ARMul_CANT; 236 return ARMul_CANT;
@@ -256,7 +251,7 @@ unsigned VFPLDC(ARMul_State* state, unsigned type, u32 instr, u32 value)
256 /* TODO check access permission */ 251 /* TODO check access permission */
257 252
258 if ( (P|U|D|W) == 0 ) { 253 if ( (P|U|D|W) == 0 ) {
259 DEBUG("In %s, UNDEFINED\n", __FUNCTION__); 254 LOG_ERROR(Core_ARM11, "In %s, UNDEFINED\n", __FUNCTION__);
260 exit(-1); 255 exit(-1);
261 } 256 }
262 if (CoProc == 10 || CoProc == 11) 257 if (CoProc == 10 || CoProc == 11)
@@ -273,7 +268,7 @@ unsigned VFPLDC(ARMul_State* state, unsigned type, u32 instr, u32 value)
273 268
274 return VLDM(state, type, instr, value); 269 return VLDM(state, type, instr, value);
275 } 270 }
276 DEBUG("Can't identify %x, CoProc %x, CRd %x, Rn %x, imm8 %x, P %x, U %x, D %x, W %x\n", 271 LOG_WARNING(Core_ARM11, "Can't identify %x, CoProc %x, CRd %x, Rn %x, imm8 %x, P %x, U %x, D %x, W %x\n",
277 instr, CoProc, CRd, Rn, imm8, P, U, D, W); 272 instr, CoProc, CRd, Rn, imm8, P, U, D, W);
278 273
279 return ARMul_CANT; 274 return ARMul_CANT;
@@ -340,33 +335,6 @@ unsigned VFPCDP(ARMul_State* state, unsigned type, u32 instr)
340 335
341 if (CoProc == 10 || CoProc == 11) 336 if (CoProc == 10 || CoProc == 11)
342 { 337 {
343 if ((OPC_1 & 0xB) == 0 && (OPC_2 & 0x2) == 0)
344 DBG("VMLA :\n");
345
346 if ((OPC_1 & 0xB) == 0 && (OPC_2 & 0x2) == 2)
347 DBG("VMLS :\n");
348
349 if ((OPC_1 & 0xB) == 1 && (OPC_2 & 0x2) == 2)
350 DBG("VNMLA :\n");
351
352 if ((OPC_1 & 0xB) == 1 && (OPC_2 & 0x2) == 0)
353 DBG("VNMLS :\n");
354
355 if ((OPC_1 & 0xB) == 2 && (OPC_2 & 0x2) == 2)
356 DBG("VNMUL :\n");
357
358 if ((OPC_1 & 0xB) == 2 && (OPC_2 & 0x2) == 0)
359 DBG("VMUL :\n");
360
361 if ((OPC_1 & 0xB) == 3 && (OPC_2 & 0x2) == 0)
362 DBG("VADD :\n");
363
364 if ((OPC_1 & 0xB) == 3 && (OPC_2 & 0x2) == 2)
365 DBG("VSUB :\n");
366
367 if ((OPC_1 & 0xB) == 0xA && (OPC_2 & 0x2) == 0)
368 DBG("VDIV :\n");
369
370 if ((OPC_1 & 0xB) == 0xB && BITS(4, 7) == 0) 338 if ((OPC_1 & 0xB) == 0xB && BITS(4, 7) == 0)
371 { 339 {
372 unsigned int single = BIT(8) == 0; 340 unsigned int single = BIT(8) == 0;
@@ -392,30 +360,6 @@ unsigned VFPCDP(ARMul_State* state, unsigned type, u32 instr)
392 return ARMul_DONE; 360 return ARMul_DONE;
393 } 361 }
394 362
395 if ((OPC_1 & 0xB) == 0xB && CRn == 0 && (OPC_2 & 0x7) == 6)
396 DBG("VABS :\n");
397
398 if ((OPC_1 & 0xB) == 0xB && CRn == 1 && (OPC_2 & 0x7) == 2)
399 DBG("VNEG :\n");
400
401 if ((OPC_1 & 0xB) == 0xB && CRn == 1 && (OPC_2 & 0x7) == 6)
402 DBG("VSQRT :\n");
403
404 if ((OPC_1 & 0xB) == 0xB && CRn == 4 && (OPC_2 & 0x2) == 2)
405 DBG("VCMP(1) :\n");
406
407 if ((OPC_1 & 0xB) == 0xB && CRn == 5 && (OPC_2 & 0x2) == 2 && CRm == 0)
408 DBG("VCMP(2) :\n");
409
410 if ((OPC_1 & 0xB) == 0xB && CRn == 7 && (OPC_2 & 0x6) == 6)
411 DBG("VCVT(BDS) :\n");
412
413 if ((OPC_1 & 0xB) == 0xB && CRn >= 0xA && (OPC_2 & 0x2) == 2)
414 DBG("VCVT(BFF) :\n");
415
416 if ((OPC_1 & 0xB) == 0xB && CRn > 7 && (OPC_2 & 0x2) == 2)
417 DBG("VCVT(BFI) :\n");
418
419 int exceptions = 0; 363 int exceptions = 0;
420 if (CoProc == 10) 364 if (CoProc == 10)
421 exceptions = vfp_single_cpdo(state, instr, state->VFP[VFP_OFFSET(VFP_FPSCR)]); 365 exceptions = vfp_single_cpdo(state, instr, state->VFP[VFP_OFFSET(VFP_FPSCR)]);
@@ -426,40 +370,33 @@ unsigned VFPCDP(ARMul_State* state, unsigned type, u32 instr)
426 370
427 return ARMul_DONE; 371 return ARMul_DONE;
428 } 372 }
429 DEBUG("Can't identify %x\n", instr); 373 LOG_WARNING(Core_ARM11, "Can't identify %x\n", instr);
430 return ARMul_CANT; 374 return ARMul_CANT;
431} 375}
432 376
433
434/* ----------- MRC ------------ */ 377/* ----------- MRC ------------ */
435void VMOVBRS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword n, ARMword* value) 378void VMOVBRS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword n, ARMword* value)
436{ 379{
437 DBG("VMOV(BRS) :\n");
438 if (to_arm) 380 if (to_arm)
439 { 381 {
440 DBG("\tr%d <= s%d=[%x]\n", t, n, state->ExtReg[n]);
441 *value = state->ExtReg[n]; 382 *value = state->ExtReg[n];
442 } 383 }
443 else 384 else
444 { 385 {
445 DBG("\ts%d <= r%d=[%x]\n", n, t, *value);
446 state->ExtReg[n] = *value; 386 state->ExtReg[n] = *value;
447 } 387 }
448} 388}
449void VMRS(ARMul_State* state, ARMword reg, ARMword Rt, ARMword* value) 389void VMRS(ARMul_State* state, ARMword reg, ARMword Rt, ARMword* value)
450{ 390{
451 DBG("VMRS :");
452 if (reg == 1) 391 if (reg == 1)
453 { 392 {
454 if (Rt != 15) 393 if (Rt != 15)
455 { 394 {
456 *value = state->VFP[VFP_OFFSET(VFP_FPSCR)]; 395 *value = state->VFP[VFP_OFFSET(VFP_FPSCR)];
457 DBG("\tr%d <= fpscr[%08x]\n", Rt, state->VFP[VFP_OFFSET(VFP_FPSCR)]);
458 } 396 }
459 else 397 else
460 { 398 {
461 *value = state->VFP[VFP_OFFSET(VFP_FPSCR)] ; 399 *value = state->VFP[VFP_OFFSET(VFP_FPSCR)] ;
462 DBG("\tflags <= fpscr[%1xxxxxxxx]\n", state->VFP[VFP_OFFSET(VFP_FPSCR)]>>28);
463 } 400 }
464 } 401 }
465 else 402 else
@@ -468,54 +405,46 @@ void VMRS(ARMul_State* state, ARMword reg, ARMword Rt, ARMword* value)
468 { 405 {
469 case 0: 406 case 0:
470 *value = state->VFP[VFP_OFFSET(VFP_FPSID)]; 407 *value = state->VFP[VFP_OFFSET(VFP_FPSID)];
471 DBG("\tr%d <= fpsid[%08x]\n", Rt, state->VFP[VFP_OFFSET(VFP_FPSID)]);
472 break; 408 break;
473 case 6: 409 case 6:
474 /* MVFR1, VFPv3 only ? */ 410 /* MVFR1, VFPv3 only ? */
475 DBG("\tr%d <= MVFR1 unimplemented\n", Rt); 411 LOG_TRACE(Core_ARM11, "\tr%d <= MVFR1 unimplemented\n", Rt);
476 break; 412 break;
477 case 7: 413 case 7:
478 /* MVFR0, VFPv3 only? */ 414 /* MVFR0, VFPv3 only? */
479 DBG("\tr%d <= MVFR0 unimplemented\n", Rt); 415 LOG_TRACE(Core_ARM11, "\tr%d <= MVFR0 unimplemented\n", Rt);
480 break; 416 break;
481 case 8: 417 case 8:
482 *value = state->VFP[VFP_OFFSET(VFP_FPEXC)]; 418 *value = state->VFP[VFP_OFFSET(VFP_FPEXC)];
483 DBG("\tr%d <= fpexc[%08x]\n", Rt, state->VFP[VFP_OFFSET(VFP_FPEXC)]);
484 break; 419 break;
485 default: 420 default:
486 DBG("\tSUBARCHITECTURE DEFINED\n"); 421 LOG_TRACE(Core_ARM11, "\tSUBARCHITECTURE DEFINED\n");
487 break; 422 break;
488 } 423 }
489 } 424 }
490} 425}
491void VMOVBRRD(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2) 426void VMOVBRRD(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2)
492{ 427{
493 DBG("VMOV(BRRD) :\n");
494 if (to_arm) 428 if (to_arm)
495 { 429 {
496 DBG("\tr[%d-%d] <= s[%d-%d]=[%x-%x]\n", t2, t, n*2+1, n*2, state->ExtReg[n*2+1], state->ExtReg[n*2]);
497 *value2 = state->ExtReg[n*2+1]; 430 *value2 = state->ExtReg[n*2+1];
498 *value1 = state->ExtReg[n*2]; 431 *value1 = state->ExtReg[n*2];
499 } 432 }
500 else 433 else
501 { 434 {
502 DBG("\ts[%d-%d] <= r[%d-%d]=[%x-%x]\n", n*2+1, n*2, t2, t, *value2, *value1);
503 state->ExtReg[n*2+1] = *value2; 435 state->ExtReg[n*2+1] = *value2;
504 state->ExtReg[n*2] = *value1; 436 state->ExtReg[n*2] = *value1;
505 } 437 }
506} 438}
507void VMOVBRRSS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2) 439void VMOVBRRSS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2)
508{ 440{
509 DBG("VMOV(BRRSS) :\n");
510 if (to_arm) 441 if (to_arm)
511 { 442 {
512 DBG("\tr[%d-%d] <= s[%d-%d]=[%x-%x]\n", t2, t, n+1, n, state->ExtReg[n+1], state->ExtReg[n]);
513 *value1 = state->ExtReg[n+0]; 443 *value1 = state->ExtReg[n+0];
514 *value2 = state->ExtReg[n+1]; 444 *value2 = state->ExtReg[n+1];
515 } 445 }
516 else 446 else
517 { 447 {
518 DBG("\ts[%d-%d] <= r[%d-%d]=[%x-%x]\n", n+1, n, t2, t, *value2, *value1);
519 state->ExtReg[n+0] = *value1; 448 state->ExtReg[n+0] = *value1;
520 state->ExtReg[n+1] = *value2; 449 state->ExtReg[n+1] = *value2;
521 } 450 }
@@ -526,12 +455,10 @@ void VMSR(ARMul_State* state, ARMword reg, ARMword Rt)
526{ 455{
527 if (reg == 1) 456 if (reg == 1)
528 { 457 {
529 DBG("VMSR :\tfpscr <= r%d=[%x]\n", Rt, state->Reg[Rt]);
530 state->VFP[VFP_OFFSET(VFP_FPSCR)] = state->Reg[Rt]; 458 state->VFP[VFP_OFFSET(VFP_FPSCR)] = state->Reg[Rt];
531 } 459 }
532 else if (reg == 8) 460 else if (reg == 8)
533 { 461 {
534 DBG("VMSR :\tfpexc <= r%d=[%x]\n", Rt, state->Reg[Rt]);
535 state->VFP[VFP_OFFSET(VFP_FPEXC)] = state->Reg[Rt]; 462 state->VFP[VFP_OFFSET(VFP_FPEXC)] = state->Reg[Rt];
536 } 463 }
537} 464}
@@ -556,8 +483,6 @@ int VSTR(ARMul_State* state, int type, ARMword instr, ARMword* value)
556 d = single_reg ? BITS(12, 15)<<1|BIT(22) : BIT(22)<<4|BITS(12, 15); /* Base register */ 483 d = single_reg ? BITS(12, 15)<<1|BIT(22) : BIT(22)<<4|BITS(12, 15); /* Base register */
557 n = BITS(16, 19); /* destination register */ 484 n = BITS(16, 19); /* destination register */
558 485
559 DBG("VSTR :\n");
560
561 i = 0; 486 i = 0;
562 regs = 1; 487 regs = 1;
563 488
@@ -568,7 +493,6 @@ int VSTR(ARMul_State* state, int type, ARMword instr, ARMword* value)
568 if (single_reg) 493 if (single_reg)
569 { 494 {
570 *value = state->ExtReg[d+i]; 495 *value = state->ExtReg[d+i];
571 DBG("\taddr[?] <= s%d=[%x]\n", d+i, state->ExtReg[d+i]);
572 i++; 496 i++;
573 if (i < regs) 497 if (i < regs)
574 return ARMul_INC; 498 return ARMul_INC;
@@ -579,7 +503,6 @@ int VSTR(ARMul_State* state, int type, ARMword instr, ARMword* value)
579 { 503 {
580 /* FIXME Careful of endianness, may need to rework this */ 504 /* FIXME Careful of endianness, may need to rework this */
581 *value = state->ExtReg[d*2+i]; 505 *value = state->ExtReg[d*2+i];
582 DBG("\taddr[?] <= s[%d]=[%x]\n", d*2+i, state->ExtReg[d*2+i]);
583 i++; 506 i++;
584 if (i < regs*2) 507 if (i < regs*2)
585 return ARMul_INC; 508 return ARMul_INC;
@@ -601,10 +524,7 @@ int VPUSH(ARMul_State* state, int type, ARMword instr, ARMword* value)
601 imm32 = BITS(0,7)<<2; /* may not be used */ 524 imm32 = BITS(0,7)<<2; /* may not be used */
602 regs = single_regs ? BITS(0, 7) : BITS(1, 7); /* FSTMX if regs is odd */ 525 regs = single_regs ? BITS(0, 7) : BITS(1, 7); /* FSTMX if regs is odd */
603 526
604 DBG("VPUSH :\n");
605 DBG("\tsp[%x]", state->Reg[R13]);
606 state->Reg[R13] = state->Reg[R13] - imm32; 527 state->Reg[R13] = state->Reg[R13] - imm32;
607 DBG("=>[%x]\n", state->Reg[R13]);
608 528
609 i = 0; 529 i = 0;
610 530
@@ -615,7 +535,6 @@ int VPUSH(ARMul_State* state, int type, ARMword instr, ARMword* value)
615 if (single_regs) 535 if (single_regs)
616 { 536 {
617 *value = state->ExtReg[d + i]; 537 *value = state->ExtReg[d + i];
618 DBG("\taddr[?] <= s%d=[%x]\n", d+i, state->ExtReg[d + i]);
619 i++; 538 i++;
620 if (i < regs) 539 if (i < regs)
621 return ARMul_INC; 540 return ARMul_INC;
@@ -626,7 +545,6 @@ int VPUSH(ARMul_State* state, int type, ARMword instr, ARMword* value)
626 { 545 {
627 /* FIXME Careful of endianness, may need to rework this */ 546 /* FIXME Careful of endianness, may need to rework this */
628 *value = state->ExtReg[d*2 + i]; 547 *value = state->ExtReg[d*2 + i];
629 DBG("\taddr[?] <= s[%d]=[%x]\n", d*2 + i, state->ExtReg[d*2 + i]);
630 i++; 548 i++;
631 if (i < regs*2) 549 if (i < regs*2)
632 return ARMul_INC; 550 return ARMul_INC;
@@ -651,11 +569,8 @@ int VSTM(ARMul_State* state, int type, ARMword instr, ARMword* value)
651 imm32 = BITS(0,7) * 4; /* may not be used */ 569 imm32 = BITS(0,7) * 4; /* may not be used */
652 regs = single_regs ? BITS(0, 7) : BITS(0, 7)>>1; /* FSTMX if regs is odd */ 570 regs = single_regs ? BITS(0, 7) : BITS(0, 7)>>1; /* FSTMX if regs is odd */
653 571
654 DBG("VSTM :\n");
655
656 if (wback) { 572 if (wback) {
657 state->Reg[n] = (add ? state->Reg[n] + imm32 : state->Reg[n] - imm32); 573 state->Reg[n] = (add ? state->Reg[n] + imm32 : state->Reg[n] - imm32);
658 DBG("\twback r%d[%x]\n", n, state->Reg[n]);
659 } 574 }
660 575
661 i = 0; 576 i = 0;
@@ -667,7 +582,6 @@ int VSTM(ARMul_State* state, int type, ARMword instr, ARMword* value)
667 if (single_regs) 582 if (single_regs)
668 { 583 {
669 *value = state->ExtReg[d + i]; 584 *value = state->ExtReg[d + i];
670 DBG("\taddr[?] <= s%d=[%x]\n", d+i, state->ExtReg[d + i]);
671 i++; 585 i++;
672 if (i < regs) 586 if (i < regs)
673 return ARMul_INC; 587 return ARMul_INC;
@@ -678,7 +592,6 @@ int VSTM(ARMul_State* state, int type, ARMword instr, ARMword* value)
678 { 592 {
679 /* FIXME Careful of endianness, may need to rework this */ 593 /* FIXME Careful of endianness, may need to rework this */
680 *value = state->ExtReg[d*2 + i]; 594 *value = state->ExtReg[d*2 + i];
681 DBG("\taddr[?] <= s[%d]=[%x]\n", d*2 + i, state->ExtReg[d*2 + i]);
682 i++; 595 i++;
683 if (i < regs*2) 596 if (i < regs*2)
684 return ARMul_INC; 597 return ARMul_INC;
@@ -702,10 +615,7 @@ int VPOP(ARMul_State* state, int type, ARMword instr, ARMword value)
702 imm32 = BITS(0,7)<<2; /* may not be used */ 615 imm32 = BITS(0,7)<<2; /* may not be used */
703 regs = single_regs ? BITS(0, 7) : BITS(1, 7); /* FLDMX if regs is odd */ 616 regs = single_regs ? BITS(0, 7) : BITS(1, 7); /* FLDMX if regs is odd */
704 617
705 DBG("VPOP :\n");
706 DBG("\tsp[%x]", state->Reg[R13]);
707 state->Reg[R13] = state->Reg[R13] + imm32; 618 state->Reg[R13] = state->Reg[R13] + imm32;
708 DBG("=>[%x]\n", state->Reg[R13]);
709 619
710 i = 0; 620 i = 0;
711 621
@@ -720,7 +630,6 @@ int VPOP(ARMul_State* state, int type, ARMword instr, ARMword value)
720 if (single_regs) 630 if (single_regs)
721 { 631 {
722 state->ExtReg[d + i] = value; 632 state->ExtReg[d + i] = value;
723 DBG("\ts%d <= [%x]\n", d + i, value);
724 i++; 633 i++;
725 if (i < regs) 634 if (i < regs)
726 return ARMul_INC; 635 return ARMul_INC;
@@ -731,7 +640,6 @@ int VPOP(ARMul_State* state, int type, ARMword instr, ARMword value)
731 { 640 {
732 /* FIXME Careful of endianness, may need to rework this */ 641 /* FIXME Careful of endianness, may need to rework this */
733 state->ExtReg[d*2 + i] = value; 642 state->ExtReg[d*2 + i] = value;
734 DBG("\ts%d <= [%x]\n", d*2 + i, value);
735 i++; 643 i++;
736 if (i < regs*2) 644 if (i < regs*2)
737 return ARMul_INC; 645 return ARMul_INC;
@@ -754,11 +662,9 @@ int VLDR(ARMul_State* state, int type, ARMword instr, ARMword value)
754 d = single_reg ? BITS(12, 15)<<1|BIT(22) : BIT(22)<<4|BITS(12, 15); /* Base register */ 662 d = single_reg ? BITS(12, 15)<<1|BIT(22) : BIT(22)<<4|BITS(12, 15); /* Base register */
755 n = BITS(16, 19); /* destination register */ 663 n = BITS(16, 19); /* destination register */
756 664
757 DBG("VLDR :\n");
758
759 i = 0; 665 i = 0;
760 regs = 1; 666 regs = 1;
761 667
762 return ARMul_DONE; 668 return ARMul_DONE;
763 } 669 }
764 else if (type == ARMul_TRANSFER) 670 else if (type == ARMul_TRANSFER)
@@ -770,7 +676,6 @@ int VLDR(ARMul_State* state, int type, ARMword instr, ARMword value)
770 if (single_reg) 676 if (single_reg)
771 { 677 {
772 state->ExtReg[d+i] = value; 678 state->ExtReg[d+i] = value;
773 DBG("\ts%d <= [%x]\n", d+i, value);
774 i++; 679 i++;
775 if (i < regs) 680 if (i < regs)
776 return ARMul_INC; 681 return ARMul_INC;
@@ -781,7 +686,6 @@ int VLDR(ARMul_State* state, int type, ARMword instr, ARMword value)
781 { 686 {
782 /* FIXME Careful of endianness, may need to rework this */ 687 /* FIXME Careful of endianness, may need to rework this */
783 state->ExtReg[d*2+i] = value; 688 state->ExtReg[d*2+i] = value;
784 DBG("\ts[%d] <= [%x]\n", d*2+i, value);
785 i++; 689 i++;
786 if (i < regs*2) 690 if (i < regs*2)
787 return ARMul_INC; 691 return ARMul_INC;
@@ -805,12 +709,9 @@ int VLDM(ARMul_State* state, int type, ARMword instr, ARMword value)
805 n = BITS(16, 19); /* destination register */ 709 n = BITS(16, 19); /* destination register */
806 imm32 = BITS(0,7) * 4; /* may not be used */ 710 imm32 = BITS(0,7) * 4; /* may not be used */
807 regs = single_regs ? BITS(0, 7) : BITS(0, 7)>>1; /* FLDMX if regs is odd */ 711 regs = single_regs ? BITS(0, 7) : BITS(0, 7)>>1; /* FLDMX if regs is odd */
808 712
809 DBG("VLDM :\n");
810
811 if (wback) { 713 if (wback) {
812 state->Reg[n] = (add ? state->Reg[n] + imm32 : state->Reg[n] - imm32); 714 state->Reg[n] = (add ? state->Reg[n] + imm32 : state->Reg[n] - imm32);
813 DBG("\twback r%d[%x]\n", n, state->Reg[n]);
814 } 715 }
815 716
816 i = 0; 717 i = 0;
@@ -822,7 +723,6 @@ int VLDM(ARMul_State* state, int type, ARMword instr, ARMword value)
822 if (single_regs) 723 if (single_regs)
823 { 724 {
824 state->ExtReg[d + i] = value; 725 state->ExtReg[d + i] = value;
825 DBG("\ts%d <= [%x] addr[?]\n", d+i, state->ExtReg[d + i]);
826 i++; 726 i++;
827 if (i < regs) 727 if (i < regs)
828 return ARMul_INC; 728 return ARMul_INC;
@@ -833,7 +733,6 @@ int VLDM(ARMul_State* state, int type, ARMword instr, ARMword value)
833 { 733 {
834 /* FIXME Careful of endianness, may need to rework this */ 734 /* FIXME Careful of endianness, may need to rework this */
835 state->ExtReg[d*2 + i] = value; 735 state->ExtReg[d*2 + i] = value;
836 DBG("\ts[%d] <= [%x] addr[?]\n", d*2 + i, state->ExtReg[d*2 + i]);
837 i++; 736 i++;
838 if (i < regs*2) 737 if (i < regs*2)
839 return ARMul_INC; 738 return ARMul_INC;
@@ -841,41 +740,33 @@ int VLDM(ARMul_State* state, int type, ARMword instr, ARMword value)
841 return ARMul_DONE; 740 return ARMul_DONE;
842 } 741 }
843 } 742 }
844 743
845 return -1; 744 return -1;
846} 745}
847 746
848/* ----------- CDP ------------ */ 747/* ----------- CDP ------------ */
849void VMOVI(ARMul_State* state, ARMword single, ARMword d, ARMword imm) 748void VMOVI(ARMul_State* state, ARMword single, ARMword d, ARMword imm)
850{ 749{
851 DBG("VMOV(I) :\n");
852
853 if (single) 750 if (single)
854 { 751 {
855 DBG("\ts%d <= [%x]\n", d, imm);
856 state->ExtReg[d] = imm; 752 state->ExtReg[d] = imm;
857 } 753 }
858 else 754 else
859 { 755 {
860 /* Check endian please */ 756 /* Check endian please */
861 DBG("\ts[%d-%d] <= [%x-%x]\n", d*2+1, d*2, imm, 0);
862 state->ExtReg[d*2+1] = imm; 757 state->ExtReg[d*2+1] = imm;
863 state->ExtReg[d*2] = 0; 758 state->ExtReg[d*2] = 0;
864 } 759 }
865} 760}
866void VMOVR(ARMul_State* state, ARMword single, ARMword d, ARMword m) 761void VMOVR(ARMul_State* state, ARMword single, ARMword d, ARMword m)
867{ 762{
868 DBG("VMOV(R) :\n");
869
870 if (single) 763 if (single)
871 { 764 {
872 DBG("\ts%d <= s%d[%x]\n", d, m, state->ExtReg[m]);
873 state->ExtReg[d] = state->ExtReg[m]; 765 state->ExtReg[d] = state->ExtReg[m];
874 } 766 }
875 else 767 else
876 { 768 {
877 /* Check endian please */ 769 /* Check endian please */
878 DBG("\ts[%d-%d] <= s[%d-%d][%x-%x]\n", d*2+1, d*2, m*2+1, m*2, state->ExtReg[m*2+1], state->ExtReg[m*2]);
879 state->ExtReg[d*2+1] = state->ExtReg[m*2+1]; 770 state->ExtReg[d*2+1] = state->ExtReg[m*2+1];
880 state->ExtReg[d*2] = state->ExtReg[m*2]; 771 state->ExtReg[d*2] = state->ExtReg[m*2];
881 } 772 }
@@ -884,13 +775,13 @@ void VMOVR(ARMul_State* state, ARMword single, ARMword d, ARMword m)
884/* Miscellaneous functions */ 775/* Miscellaneous functions */
885int32_t vfp_get_float(arm_core_t* state, unsigned int reg) 776int32_t vfp_get_float(arm_core_t* state, unsigned int reg)
886{ 777{
887 DEBUG("VFP get float: s%d=[%08x]\n", reg, state->ExtReg[reg]); 778 LOG_TRACE(Core_ARM11, "VFP get float: s%d=[%08x]\n", reg, state->ExtReg[reg]);
888 return state->ExtReg[reg]; 779 return state->ExtReg[reg];
889} 780}
890 781
891void vfp_put_float(arm_core_t* state, int32_t val, unsigned int reg) 782void vfp_put_float(arm_core_t* state, int32_t val, unsigned int reg)
892{ 783{
893 DEBUG("VFP put float: s%d <= [%08x]\n", reg, val); 784 LOG_TRACE(Core_ARM11, "VFP put float: s%d <= [%08x]\n", reg, val);
894 state->ExtReg[reg] = val; 785 state->ExtReg[reg] = val;
895} 786}
896 787
@@ -898,13 +789,13 @@ uint64_t vfp_get_double(arm_core_t* state, unsigned int reg)
898{ 789{
899 uint64_t result; 790 uint64_t result;
900 result = ((uint64_t) state->ExtReg[reg*2+1])<<32 | state->ExtReg[reg*2]; 791 result = ((uint64_t) state->ExtReg[reg*2+1])<<32 | state->ExtReg[reg*2];
901 DEBUG("VFP get double: s[%d-%d]=[%016llx]\n", reg*2+1, reg*2, result); 792 LOG_TRACE(Core_ARM11, "VFP get double: s[%d-%d]=[%016llx]\n", reg * 2 + 1, reg * 2, result);
902 return result; 793 return result;
903} 794}
904 795
905void vfp_put_double(arm_core_t* state, uint64_t val, unsigned int reg) 796void vfp_put_double(arm_core_t* state, uint64_t val, unsigned int reg)
906{ 797{
907 DEBUG("VFP put double: s[%d-%d] <= [%08x-%08x]\n", reg*2+1, reg*2, (uint32_t) (val>>32), (uint32_t) (val & 0xffffffff)); 798 LOG_TRACE(Core_ARM11, "VFP put double: s[%d-%d] <= [%08x-%08x]\n", reg * 2 + 1, reg * 2, (uint32_t)(val >> 32), (uint32_t)(val & 0xffffffff));
908 state->ExtReg[reg*2] = (uint32_t) (val & 0xffffffff); 799 state->ExtReg[reg*2] = (uint32_t) (val & 0xffffffff);
909 state->ExtReg[reg*2+1] = (uint32_t) (val>>32); 800 state->ExtReg[reg*2+1] = (uint32_t) (val>>32);
910} 801}
@@ -916,10 +807,10 @@ void vfp_raise_exceptions(ARMul_State* state, u32 exceptions, u32 inst, u32 fpsc
916{ 807{
917 int si_code = 0; 808 int si_code = 0;
918 809
919 vfpdebug("VFP: raising exceptions %08x\n", exceptions); 810 LOG_DEBUG(Core_ARM11, "VFP: raising exceptions %08x\n", exceptions);
920 811
921 if (exceptions == VFP_EXCEPTION_ERROR) { 812 if (exceptions == VFP_EXCEPTION_ERROR) {
922 DEBUG("unhandled bounce %x\n", inst); 813 LOG_TRACE(Core_ARM11, "unhandled bounce %x\n", inst);
923 exit(-1); 814 exit(-1);
924 return; 815 return;
925 } 816 }
diff --git a/src/core/arm/skyeye_common/vfp/vfp.h b/src/core/arm/skyeye_common/vfp/vfp.h
index 539fb0131..5ff213e08 100644
--- a/src/core/arm/skyeye_common/vfp/vfp.h
+++ b/src/core/arm/skyeye_common/vfp/vfp.h
@@ -1,4 +1,4 @@
1/* 1/*
2 vfp/vfp.h - ARM VFPv3 emulation unit - vfp interface 2 vfp/vfp.h - ARM VFPv3 emulation unit - vfp interface
3 Copyright (C) 2003 Skyeye Develop Group 3 Copyright (C) 2003 Skyeye Develop Group
4 for help please send mail to <skyeye-developer@lists.gro.clinux.org> 4 for help please send mail to <skyeye-developer@lists.gro.clinux.org>
@@ -21,15 +21,10 @@
21#ifndef __VFP_H__ 21#ifndef __VFP_H__
22#define __VFP_H__ 22#define __VFP_H__
23 23
24#define DBG(...) //DEBUG_LOG(ARM11, __VA_ARGS__)
25
26#define vfpdebug //printf
27
28#include "core/arm/skyeye_common/vfp/vfp_helper.h" /* for references to cdp SoftFloat functions */ 24#include "core/arm/skyeye_common/vfp/vfp_helper.h" /* for references to cdp SoftFloat functions */
29 25
30#define VFP_DEBUG_TRANSLATE DBG("in func %s, %x\n", __FUNCTION__, inst); 26#define VFP_DEBUG_UNIMPLEMENTED(x) LOG_ERROR(Core_ARM11, "in func %s, " #x " unimplemented\n", __FUNCTION__); exit(-1);
31#define VFP_DEBUG_UNIMPLEMENTED(x) printf("in func %s, " #x " unimplemented\n", __FUNCTION__); exit(-1); 27#define VFP_DEBUG_UNTESTED(x) LOG_TRACE(Core_ARM11, "in func %s, " #x " untested\n", __FUNCTION__);
32#define VFP_DEBUG_UNTESTED(x) printf("in func %s, " #x " untested\n", __FUNCTION__);
33#define CHECK_VFP_ENABLED 28#define CHECK_VFP_ENABLED
34#define CHECK_VFP_CDP_RET vfp_raise_exceptions(cpu, ret, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); //if (ret == -1) {printf("VFP CDP FAILURE %x\n", inst_cream->instr); exit(-1);} 29#define CHECK_VFP_CDP_RET vfp_raise_exceptions(cpu, ret, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); //if (ret == -1) {printf("VFP CDP FAILURE %x\n", inst_cream->instr); exit(-1);}
35 30
diff --git a/src/core/arm/skyeye_common/vfp/vfpdouble.cpp b/src/core/arm/skyeye_common/vfp/vfpdouble.cpp
index a9df490ba..da7de6e65 100644
--- a/src/core/arm/skyeye_common/vfp/vfpdouble.cpp
+++ b/src/core/arm/skyeye_common/vfp/vfpdouble.cpp
@@ -50,7 +50,7 @@
50 * this code that are retained. 50 * this code that are retained.
51 * =========================================================================== 51 * ===========================================================================
52 */ 52 */
53 53
54#include "core/arm/skyeye_common/vfp/vfp.h" 54#include "core/arm/skyeye_common/vfp/vfp.h"
55#include "core/arm/skyeye_common/vfp/vfp_helper.h" 55#include "core/arm/skyeye_common/vfp/vfp_helper.h"
56#include "core/arm/skyeye_common/vfp/asm_vfp.h" 56#include "core/arm/skyeye_common/vfp/asm_vfp.h"
@@ -63,7 +63,7 @@ static struct vfp_double vfp_double_default_qnan = {
63 63
64static void vfp_double_dump(const char *str, struct vfp_double *d) 64static void vfp_double_dump(const char *str, struct vfp_double *d)
65{ 65{
66 pr_debug("VFP: %s: sign=%d exponent=%d significand=%016llx\n", 66 LOG_TRACE(Core_ARM11, "VFP: %s: sign=%d exponent=%d significand=%016llx\n",
67 str, d->sign != 0, d->exponent, d->significand); 67 str, d->sign != 0, d->exponent, d->significand);
68} 68}
69 69
@@ -155,7 +155,7 @@ u32 vfp_double_normaliseroundintern(ARMul_State* state, struct vfp_double *vd, u
155 else if ((rmode == FPSCR_ROUND_PLUSINF) ^ (vd->sign != 0)) 155 else if ((rmode == FPSCR_ROUND_PLUSINF) ^ (vd->sign != 0))
156 incr = (1ULL << (VFP_DOUBLE_LOW_BITS + 1)) - 1; 156 incr = (1ULL << (VFP_DOUBLE_LOW_BITS + 1)) - 1;
157 157
158 pr_debug("VFP: rounding increment = 0x%08llx\n", incr); 158 LOG_TRACE(Core_ARM11, "VFP: rounding increment = 0x%08llx\n", incr);
159 159
160 /* 160 /*
161 * Is our rounding going to overflow? 161 * Is our rounding going to overflow?
@@ -281,7 +281,7 @@ u32 vfp_double_normaliseround(ARMul_State* state, int dd, struct vfp_double *vd,
281 } else if ((rmode == FPSCR_ROUND_PLUSINF) ^ (vd->sign != 0)) 281 } else if ((rmode == FPSCR_ROUND_PLUSINF) ^ (vd->sign != 0))
282 incr = (1ULL << (VFP_DOUBLE_LOW_BITS + 1)) - 1; 282 incr = (1ULL << (VFP_DOUBLE_LOW_BITS + 1)) - 1;
283 283
284 pr_debug("VFP: rounding increment = 0x%08llx\n", incr); 284 LOG_TRACE(Core_ARM11, "VFP: rounding increment = 0x%08llx\n", incr);
285 285
286 /* 286 /*
287 * Is our rounding going to overflow? 287 * Is our rounding going to overflow?
@@ -336,7 +336,7 @@ pack:
336 vfp_double_dump("pack: final", vd); 336 vfp_double_dump("pack: final", vd);
337 { 337 {
338 s64 d = vfp_double_pack(vd); 338 s64 d = vfp_double_pack(vd);
339 pr_debug("VFP: %s: d(d%d)=%016llx exceptions=%08x\n", func, 339 LOG_TRACE(Core_ARM11, "VFP: %s: d(d%d)=%016llx exceptions=%08x\n", func,
340 dd, d, exceptions); 340 dd, d, exceptions);
341 vfp_put_double(state, d, dd); 341 vfp_put_double(state, d, dd);
342 } 342 }
@@ -393,28 +393,28 @@ vfp_propagate_nan(struct vfp_double *vdd, struct vfp_double *vdn,
393 */ 393 */
394static u32 vfp_double_fabs(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) 394static u32 vfp_double_fabs(ARMul_State* state, int dd, int unused, int dm, u32 fpscr)
395{ 395{
396 pr_debug("In %s\n", __FUNCTION__); 396 LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
397 vfp_put_double(state, vfp_double_packed_abs(vfp_get_double(state, dm)), dd); 397 vfp_put_double(state, vfp_double_packed_abs(vfp_get_double(state, dm)), dd);
398 return 0; 398 return 0;
399} 399}
400 400
401static u32 vfp_double_fcpy(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) 401static u32 vfp_double_fcpy(ARMul_State* state, int dd, int unused, int dm, u32 fpscr)
402{ 402{
403 pr_debug("In %s\n", __FUNCTION__); 403 LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
404 vfp_put_double(state, vfp_get_double(state, dm), dd); 404 vfp_put_double(state, vfp_get_double(state, dm), dd);
405 return 0; 405 return 0;
406} 406}
407 407
408static u32 vfp_double_fneg(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) 408static u32 vfp_double_fneg(ARMul_State* state, int dd, int unused, int dm, u32 fpscr)
409{ 409{
410 pr_debug("In %s\n", __FUNCTION__); 410 LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
411 vfp_put_double(state, vfp_double_packed_negate(vfp_get_double(state, dm)), dd); 411 vfp_put_double(state, vfp_double_packed_negate(vfp_get_double(state, dm)), dd);
412 return 0; 412 return 0;
413} 413}
414 414
415static u32 vfp_double_fsqrt(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) 415static u32 vfp_double_fsqrt(ARMul_State* state, int dd, int unused, int dm, u32 fpscr)
416{ 416{
417 pr_debug("In %s\n", __FUNCTION__); 417 LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
418 vfp_double vdm, vdd, *vdp; 418 vfp_double vdm, vdd, *vdp;
419 int ret, tm; 419 int ret, tm;
420 420
@@ -508,7 +508,7 @@ static u32 vfp_compare(ARMul_State* state, int dd, int signal_on_qnan, int dm, u
508 s64 d, m; 508 s64 d, m;
509 u32 ret = 0; 509 u32 ret = 0;
510 510
511 pr_debug("In %s, state=0x%x, fpscr=0x%x\n", __FUNCTION__, state, fpscr); 511 LOG_TRACE(Core_ARM11, "In %s, state=0x%x, fpscr=0x%x\n", __FUNCTION__, state, fpscr);
512 m = vfp_get_double(state, dm); 512 m = vfp_get_double(state, dm);
513 if (vfp_double_packed_exponent(m) == 2047 && vfp_double_packed_mantissa(m)) { 513 if (vfp_double_packed_exponent(m) == 2047 && vfp_double_packed_mantissa(m)) {
514 ret |= FPSCR_C | FPSCR_V; 514 ret |= FPSCR_C | FPSCR_V;
@@ -563,32 +563,32 @@ static u32 vfp_compare(ARMul_State* state, int dd, int signal_on_qnan, int dm, u
563 ret |= FPSCR_C; 563 ret |= FPSCR_C;
564 } 564 }
565 } 565 }
566 pr_debug("In %s, state=0x%x, ret=0x%x\n", __FUNCTION__, state, ret); 566 LOG_TRACE(Core_ARM11, "In %s, state=0x%x, ret=0x%x\n", __FUNCTION__, state, ret);
567 567
568 return ret; 568 return ret;
569} 569}
570 570
571static u32 vfp_double_fcmp(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) 571static u32 vfp_double_fcmp(ARMul_State* state, int dd, int unused, int dm, u32 fpscr)
572{ 572{
573 pr_debug("In %s\n", __FUNCTION__); 573 LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
574 return vfp_compare(state, dd, 0, dm, fpscr); 574 return vfp_compare(state, dd, 0, dm, fpscr);
575} 575}
576 576
577static u32 vfp_double_fcmpe(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) 577static u32 vfp_double_fcmpe(ARMul_State* state, int dd, int unused, int dm, u32 fpscr)
578{ 578{
579 pr_debug("In %s\n", __FUNCTION__); 579 LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
580 return vfp_compare(state, dd, 1, dm, fpscr); 580 return vfp_compare(state, dd, 1, dm, fpscr);
581} 581}
582 582
583static u32 vfp_double_fcmpz(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) 583static u32 vfp_double_fcmpz(ARMul_State* state, int dd, int unused, int dm, u32 fpscr)
584{ 584{
585 pr_debug("In %s\n", __FUNCTION__); 585 LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
586 return vfp_compare(state, dd, 0, VFP_REG_ZERO, fpscr); 586 return vfp_compare(state, dd, 0, VFP_REG_ZERO, fpscr);
587} 587}
588 588
589static u32 vfp_double_fcmpez(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) 589static u32 vfp_double_fcmpez(ARMul_State* state, int dd, int unused, int dm, u32 fpscr)
590{ 590{
591 pr_debug("In %s\n", __FUNCTION__); 591 LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
592 return vfp_compare(state, dd, 1, VFP_REG_ZERO, fpscr); 592 return vfp_compare(state, dd, 1, VFP_REG_ZERO, fpscr);
593} 593}
594 594
@@ -598,7 +598,7 @@ u32 vfp_double_fcvtsinterncutting(ARMul_State* state, int sd, struct vfp_double*
598 int tm; 598 int tm;
599 u32 exceptions = 0; 599 u32 exceptions = 0;
600 600
601 pr_debug("In %s\n", __FUNCTION__); 601 LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
602 602
603 tm = vfp_double_type(dm); 603 tm = vfp_double_type(dm);
604 604
@@ -642,7 +642,7 @@ static u32 vfp_double_fcvts(ARMul_State* state, int sd, int unused, int dm, u32
642 int tm; 642 int tm;
643 u32 exceptions = 0; 643 u32 exceptions = 0;
644 644
645 pr_debug("In %s\n", __FUNCTION__); 645 LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
646 vfp_double_unpack(&vdm, vfp_get_double(state, dm)); 646 vfp_double_unpack(&vdm, vfp_get_double(state, dm));
647 647
648 tm = vfp_double_type(&vdm); 648 tm = vfp_double_type(&vdm);
@@ -684,7 +684,7 @@ static u32 vfp_double_fuito(ARMul_State* state, int dd, int unused, int dm, u32
684 struct vfp_double vdm; 684 struct vfp_double vdm;
685 u32 m = vfp_get_float(state, dm); 685 u32 m = vfp_get_float(state, dm);
686 686
687 pr_debug("In %s\n", __FUNCTION__); 687 LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
688 vdm.sign = 0; 688 vdm.sign = 0;
689 vdm.exponent = 1023 + 63 - 1; 689 vdm.exponent = 1023 + 63 - 1;
690 vdm.significand = (u64)m; 690 vdm.significand = (u64)m;
@@ -697,7 +697,7 @@ static u32 vfp_double_fsito(ARMul_State* state, int dd, int unused, int dm, u32
697 struct vfp_double vdm; 697 struct vfp_double vdm;
698 u32 m = vfp_get_float(state, dm); 698 u32 m = vfp_get_float(state, dm);
699 699
700 pr_debug("In %s\n", __FUNCTION__); 700 LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
701 vdm.sign = (m & 0x80000000) >> 16; 701 vdm.sign = (m & 0x80000000) >> 16;
702 vdm.exponent = 1023 + 63 - 1; 702 vdm.exponent = 1023 + 63 - 1;
703 vdm.significand = vdm.sign ? -m : m; 703 vdm.significand = vdm.sign ? -m : m;
@@ -712,7 +712,7 @@ static u32 vfp_double_ftoui(ARMul_State* state, int sd, int unused, int dm, u32
712 int rmode = fpscr & FPSCR_RMODE_MASK; 712 int rmode = fpscr & FPSCR_RMODE_MASK;
713 int tm; 713 int tm;
714 714
715 pr_debug("In %s\n", __FUNCTION__); 715 LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
716 vfp_double_unpack(&vdm, vfp_get_double(state, dm)); 716 vfp_double_unpack(&vdm, vfp_get_double(state, dm));
717 717
718 /* 718 /*
@@ -773,7 +773,7 @@ static u32 vfp_double_ftoui(ARMul_State* state, int sd, int unused, int dm, u32
773 } 773 }
774 } 774 }
775 775
776 pr_debug("VFP: ftoui: d(s%d)=%08x exceptions=%08x\n", sd, d, exceptions); 776 LOG_TRACE(Core_ARM11, "VFP: ftoui: d(s%d)=%08x exceptions=%08x\n", sd, d, exceptions);
777 777
778 vfp_put_float(state, d, sd); 778 vfp_put_float(state, d, sd);
779 779
@@ -782,7 +782,7 @@ static u32 vfp_double_ftoui(ARMul_State* state, int sd, int unused, int dm, u32
782 782
783static u32 vfp_double_ftouiz(ARMul_State* state, int sd, int unused, int dm, u32 fpscr) 783static u32 vfp_double_ftouiz(ARMul_State* state, int sd, int unused, int dm, u32 fpscr)
784{ 784{
785 pr_debug("In %s\n", __FUNCTION__); 785 LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
786 return vfp_double_ftoui(state, sd, unused, dm, FPSCR_ROUND_TOZERO); 786 return vfp_double_ftoui(state, sd, unused, dm, FPSCR_ROUND_TOZERO);
787} 787}
788 788
@@ -793,7 +793,7 @@ static u32 vfp_double_ftosi(ARMul_State* state, int sd, int unused, int dm, u32
793 int rmode = fpscr & FPSCR_RMODE_MASK; 793 int rmode = fpscr & FPSCR_RMODE_MASK;
794 int tm; 794 int tm;
795 795
796 pr_debug("In %s\n", __FUNCTION__); 796 LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
797 vfp_double_unpack(&vdm, vfp_get_double(state, dm)); 797 vfp_double_unpack(&vdm, vfp_get_double(state, dm));
798 vfp_double_dump("VDM", &vdm); 798 vfp_double_dump("VDM", &vdm);
799 799
@@ -850,7 +850,7 @@ static u32 vfp_double_ftosi(ARMul_State* state, int sd, int unused, int dm, u32
850 } 850 }
851 } 851 }
852 852
853 pr_debug("VFP: ftosi: d(s%d)=%08x exceptions=%08x\n", sd, d, exceptions); 853 LOG_TRACE(Core_ARM11, "VFP: ftosi: d(s%d)=%08x exceptions=%08x\n", sd, d, exceptions);
854 854
855 vfp_put_float(state, (s32)d, sd); 855 vfp_put_float(state, (s32)d, sd);
856 856
@@ -859,7 +859,7 @@ static u32 vfp_double_ftosi(ARMul_State* state, int sd, int unused, int dm, u32
859 859
860static u32 vfp_double_ftosiz(ARMul_State* state, int dd, int unused, int dm, u32 fpscr) 860static u32 vfp_double_ftosiz(ARMul_State* state, int dd, int unused, int dm, u32 fpscr)
861{ 861{
862 pr_debug("In %s\n", __FUNCTION__); 862 LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
863 return vfp_double_ftosi(state, dd, unused, dm, FPSCR_ROUND_TOZERO); 863 return vfp_double_ftosi(state, dd, unused, dm, FPSCR_ROUND_TOZERO);
864} 864}
865 865
@@ -894,9 +894,6 @@ static struct op fops_ext[] = {
894 { vfp_double_ftosiz, OP_SCALAR }, //0x0000001B - FEXT_FTOSIZ 894 { vfp_double_ftosiz, OP_SCALAR }, //0x0000001B - FEXT_FTOSIZ
895}; 895};
896 896
897
898
899
900static u32 897static u32
901vfp_double_fadd_nonnumber(struct vfp_double *vdd, struct vfp_double *vdn, 898vfp_double_fadd_nonnumber(struct vfp_double *vdd, struct vfp_double *vdn,
902 struct vfp_double *vdm, u32 fpscr) 899 struct vfp_double *vdm, u32 fpscr)
@@ -946,7 +943,7 @@ u32 vfp_double_add(struct vfp_double *vdd, struct vfp_double *vdn,struct vfp_dou
946 943
947 if (vdn->significand & (1ULL << 63) || 944 if (vdn->significand & (1ULL << 63) ||
948 vdm->significand & (1ULL << 63)) { 945 vdm->significand & (1ULL << 63)) {
949 pr_info("VFP: bad FP values in %s\n", __func__); 946 LOG_INFO(Core_ARM11, "VFP: bad FP values in %s\n", __func__);
950 vfp_double_dump("VDN", vdn); 947 vfp_double_dump("VDN", vdn);
951 vfp_double_dump("VDM", vdm); 948 vfp_double_dump("VDM", vdm);
952 } 949 }
@@ -1018,7 +1015,7 @@ vfp_double_multiply(struct vfp_double *vdd, struct vfp_double *vdn,
1018 struct vfp_double *t = vdn; 1015 struct vfp_double *t = vdn;
1019 vdn = vdm; 1016 vdn = vdm;
1020 vdm = t; 1017 vdm = t;
1021 pr_debug("VFP: swapping M <-> N\n"); 1018 LOG_TRACE(Core_ARM11, "VFP: swapping M <-> N\n");
1022 } 1019 }
1023 1020
1024 vdd->sign = vdn->sign ^ vdm->sign; 1021 vdd->sign = vdn->sign ^ vdm->sign;
@@ -1099,7 +1096,7 @@ vfp_double_multiply_accumulate(ARMul_State* state, int dd, int dn, int dm, u32 f
1099 */ 1096 */
1100static u32 vfp_double_fmac(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) 1097static u32 vfp_double_fmac(ARMul_State* state, int dd, int dn, int dm, u32 fpscr)
1101{ 1098{
1102 pr_debug("In %s\n", __FUNCTION__); 1099 LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
1103 return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, 0, "fmac"); 1100 return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, 0, "fmac");
1104} 1101}
1105 1102
@@ -1108,7 +1105,7 @@ static u32 vfp_double_fmac(ARMul_State* state, int dd, int dn, int dm, u32 fpscr
1108 */ 1105 */
1109static u32 vfp_double_fnmac(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) 1106static u32 vfp_double_fnmac(ARMul_State* state, int dd, int dn, int dm, u32 fpscr)
1110{ 1107{
1111 pr_debug("In %s\n", __FUNCTION__); 1108 LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
1112 return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, NEG_MULTIPLY, "fnmac"); 1109 return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, NEG_MULTIPLY, "fnmac");
1113} 1110}
1114 1111
@@ -1117,7 +1114,7 @@ static u32 vfp_double_fnmac(ARMul_State* state, int dd, int dn, int dm, u32 fpsc
1117 */ 1114 */
1118static u32 vfp_double_fmsc(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) 1115static u32 vfp_double_fmsc(ARMul_State* state, int dd, int dn, int dm, u32 fpscr)
1119{ 1116{
1120 pr_debug("In %s\n", __FUNCTION__); 1117 LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
1121 return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, NEG_SUBTRACT, "fmsc"); 1118 return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, NEG_SUBTRACT, "fmsc");
1122} 1119}
1123 1120
@@ -1126,7 +1123,7 @@ static u32 vfp_double_fmsc(ARMul_State* state, int dd, int dn, int dm, u32 fpscr
1126 */ 1123 */
1127static u32 vfp_double_fnmsc(ARMul_State* state, int dd, int dn, int dm, u32 fpscr) 1124static u32 vfp_double_fnmsc(ARMul_State* state, int dd, int dn, int dm, u32 fpscr)
1128{ 1125{
1129 pr_debug("In %s\n", __FUNCTION__); 1126 LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
1130 return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, NEG_SUBTRACT | NEG_MULTIPLY, "fnmsc"); 1127 return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, NEG_SUBTRACT | NEG_MULTIPLY, "fnmsc");
1131} 1128}
1132 1129
@@ -1138,7 +1135,7 @@ static u32 vfp_double_fmul(ARMul_State* state, int dd, int dn, int dm, u32 fpscr
1138 struct vfp_double vdd, vdn, vdm; 1135 struct vfp_double vdd, vdn, vdm;
1139 u32 exceptions; 1136 u32 exceptions;
1140 1137
1141 pr_debug("In %s\n", __FUNCTION__); 1138 LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
1142 vfp_double_unpack(&vdn, vfp_get_double(state, dn)); 1139 vfp_double_unpack(&vdn, vfp_get_double(state, dn));
1143 if (vdn.exponent == 0 && vdn.significand) 1140 if (vdn.exponent == 0 && vdn.significand)
1144 vfp_double_normalise_denormal(&vdn); 1141 vfp_double_normalise_denormal(&vdn);
@@ -1159,7 +1156,7 @@ static u32 vfp_double_fnmul(ARMul_State* state, int dd, int dn, int dm, u32 fpsc
1159 struct vfp_double vdd, vdn, vdm; 1156 struct vfp_double vdd, vdn, vdm;
1160 u32 exceptions; 1157 u32 exceptions;
1161 1158
1162 pr_debug("In %s\n", __FUNCTION__); 1159 LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
1163 vfp_double_unpack(&vdn, vfp_get_double(state, dn)); 1160 vfp_double_unpack(&vdn, vfp_get_double(state, dn));
1164 if (vdn.exponent == 0 && vdn.significand) 1161 if (vdn.exponent == 0 && vdn.significand)
1165 vfp_double_normalise_denormal(&vdn); 1162 vfp_double_normalise_denormal(&vdn);
@@ -1182,7 +1179,7 @@ static u32 vfp_double_fadd(ARMul_State* state, int dd, int dn, int dm, u32 fpscr
1182 struct vfp_double vdd, vdn, vdm; 1179 struct vfp_double vdd, vdn, vdm;
1183 u32 exceptions; 1180 u32 exceptions;
1184 1181
1185 pr_debug("In %s\n", __FUNCTION__); 1182 LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
1186 vfp_double_unpack(&vdn, vfp_get_double(state, dn)); 1183 vfp_double_unpack(&vdn, vfp_get_double(state, dn));
1187 if (vdn.exponent == 0 && vdn.significand) 1184 if (vdn.exponent == 0 && vdn.significand)
1188 vfp_double_normalise_denormal(&vdn); 1185 vfp_double_normalise_denormal(&vdn);
@@ -1204,7 +1201,7 @@ static u32 vfp_double_fsub(ARMul_State* state, int dd, int dn, int dm, u32 fpscr
1204 struct vfp_double vdd, vdn, vdm; 1201 struct vfp_double vdd, vdn, vdm;
1205 u32 exceptions; 1202 u32 exceptions;
1206 1203
1207 pr_debug("In %s\n", __FUNCTION__); 1204 LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
1208 vfp_double_unpack(&vdn, vfp_get_double(state, dn)); 1205 vfp_double_unpack(&vdn, vfp_get_double(state, dn));
1209 if (vdn.exponent == 0 && vdn.significand) 1206 if (vdn.exponent == 0 && vdn.significand)
1210 vfp_double_normalise_denormal(&vdn); 1207 vfp_double_normalise_denormal(&vdn);
@@ -1232,7 +1229,7 @@ static u32 vfp_double_fdiv(ARMul_State* state, int dd, int dn, int dm, u32 fpscr
1232 u32 exceptions = 0; 1229 u32 exceptions = 0;
1233 int tm, tn; 1230 int tm, tn;
1234 1231
1235 pr_debug("In %s\n", __FUNCTION__); 1232 LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
1236 vfp_double_unpack(&vdn, vfp_get_double(state, dn)); 1233 vfp_double_unpack(&vdn, vfp_get_double(state, dn));
1237 vfp_double_unpack(&vdm, vfp_get_double(state, dm)); 1234 vfp_double_unpack(&vdm, vfp_get_double(state, dm));
1238 1235
@@ -1357,7 +1354,7 @@ u32 vfp_double_cpdo(ARMul_State* state, u32 inst, u32 fpscr)
1357 unsigned int vecitr, veclen, vecstride; 1354 unsigned int vecitr, veclen, vecstride;
1358 struct op *fop; 1355 struct op *fop;
1359 1356
1360 pr_debug("In %s\n", __FUNCTION__); 1357 LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
1361 vecstride = (1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK)); 1358 vecstride = (1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK));
1362 1359
1363 fop = (op == FOP_EXT) ? &fops_ext[FEXT_TO_IDX(inst)] : &fops[FOP_TO_IDX(op)]; 1360 fop = (op == FOP_EXT) ? &fops_ext[FEXT_TO_IDX(inst)] : &fops[FOP_TO_IDX(op)];
@@ -1388,7 +1385,7 @@ u32 vfp_double_cpdo(ARMul_State* state, u32 inst, u32 fpscr)
1388 else 1385 else
1389 veclen = fpscr & FPSCR_LENGTH_MASK; 1386 veclen = fpscr & FPSCR_LENGTH_MASK;
1390 1387
1391 pr_debug("VFP: vecstride=%u veclen=%u\n", vecstride, 1388 LOG_TRACE(Core_ARM11, "VFP: vecstride=%u veclen=%u\n", vecstride,
1392 (veclen >> FPSCR_LENGTH_BIT) + 1); 1389 (veclen >> FPSCR_LENGTH_BIT) + 1);
1393 1390
1394 if (!fop->fn) { 1391 if (!fop->fn) {
@@ -1402,16 +1399,16 @@ u32 vfp_double_cpdo(ARMul_State* state, u32 inst, u32 fpscr)
1402 1399
1403 type = fop->flags & OP_SD ? 's' : 'd'; 1400 type = fop->flags & OP_SD ? 's' : 'd';
1404 if (op == FOP_EXT) 1401 if (op == FOP_EXT)
1405 pr_debug("VFP: itr%d (%c%u) = op[%u] (d%u)\n", 1402 LOG_TRACE(Core_ARM11, "VFP: itr%d (%c%u) = op[%u] (d%u)\n",
1406 vecitr >> FPSCR_LENGTH_BIT, 1403 vecitr >> FPSCR_LENGTH_BIT,
1407 type, dest, dn, dm); 1404 type, dest, dn, dm);
1408 else 1405 else
1409 pr_debug("VFP: itr%d (%c%u) = (d%u) op[%u] (d%u)\n", 1406 LOG_TRACE(Core_ARM11, "VFP: itr%d (%c%u) = (d%u) op[%u] (d%u)\n",
1410 vecitr >> FPSCR_LENGTH_BIT, 1407 vecitr >> FPSCR_LENGTH_BIT,
1411 type, dest, dn, FOP_TO_IDX(op), dm); 1408 type, dest, dn, FOP_TO_IDX(op), dm);
1412 1409
1413 except = fop->fn(state, dest, dn, dm, fpscr); 1410 except = fop->fn(state, dest, dn, dm, fpscr);
1414 pr_debug("VFP: itr%d: exceptions=%08x\n", 1411 LOG_TRACE(Core_ARM11, "VFP: itr%d: exceptions=%08x\n",
1415 vecitr >> FPSCR_LENGTH_BIT, except); 1412 vecitr >> FPSCR_LENGTH_BIT, except);
1416 1413
1417 exceptions |= except; 1414 exceptions |= except;
diff --git a/src/core/arm/skyeye_common/vfp/vfpinstr.cpp b/src/core/arm/skyeye_common/vfp/vfpinstr.cpp
index 2c1218c30..cf459222c 100644
--- a/src/core/arm/skyeye_common/vfp/vfpinstr.cpp
+++ b/src/core/arm/skyeye_common/vfp/vfpinstr.cpp
@@ -21,8 +21,6 @@ typedef struct _vmla_inst {
21#ifdef VFP_INTERPRETER_TRANS 21#ifdef VFP_INTERPRETER_TRANS
22ARM_INST_PTR INTERPRETER_TRANSLATE(vmla)(unsigned int inst, int index) 22ARM_INST_PTR INTERPRETER_TRANSLATE(vmla)(unsigned int inst, int index)
23{ 23{
24 VFP_DEBUG_TRANSLATE;
25
26 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmla_inst)); 24 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmla_inst));
27 vmla_inst *inst_cream = (vmla_inst *)inst_base->component; 25 vmla_inst *inst_cream = (vmla_inst *)inst_base->component;
28 26
@@ -43,8 +41,6 @@ VMLA_INST:
43 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 41 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
44 CHECK_VFP_ENABLED; 42 CHECK_VFP_ENABLED;
45 43
46 DBG("VMLA :\n");
47
48 vmla_inst *inst_cream = (vmla_inst *)inst_base->component; 44 vmla_inst *inst_cream = (vmla_inst *)inst_base->component;
49 45
50 int ret; 46 int ret;
@@ -70,7 +66,6 @@ DYNCOM_FILL_ACTION(vmla),
70int DYNCOM_TAG(vmla)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc) 66int DYNCOM_TAG(vmla)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
71{ 67{
72 int instr_size = INSTR_SIZE; 68 int instr_size = INSTR_SIZE;
73 //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
74 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc); 69 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
75 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc); 70 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
76 return instr_size; 71 return instr_size;
@@ -78,7 +73,6 @@ int DYNCOM_TAG(vmla)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *
78#endif 73#endif
79#ifdef VFP_DYNCOM_TRANS 74#ifdef VFP_DYNCOM_TRANS
80int DYNCOM_TRANS(vmla)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){ 75int DYNCOM_TRANS(vmla)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
81 //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
82 //arch_arm_undef(cpu, bb, instr); 76 //arch_arm_undef(cpu, bb, instr);
83 int m; 77 int m;
84 int n; 78 int n;
@@ -124,7 +118,7 @@ int DYNCOM_TRANS(vmla)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
124 mm = FPBITCAST64(mm); 118 mm = FPBITCAST64(mm);
125 tmp = FPADD(mm,tmp); 119 tmp = FPADD(mm,tmp);
126 mm = TRUNC32(LSHR(IBITCAST64(tmp),CONST64(32))); 120 mm = TRUNC32(LSHR(IBITCAST64(tmp),CONST64(32)));
127 nn = TRUNC32(AND(IBITCAST64(tmp),CONST64(0xffffffff))); 121 nn = TRUNC32(AND(IBITCAST64(tmp),CONST64(0xffffffff)));
128 LETFPS(2*d ,FPBITCAST32(nn)); 122 LETFPS(2*d ,FPBITCAST32(nn));
129 LETFPS(d*2 + 1 , FPBITCAST32(mm)); 123 LETFPS(d*2 + 1 , FPBITCAST32(mm));
130 } 124 }
@@ -144,8 +138,6 @@ typedef struct _vmls_inst {
144#ifdef VFP_INTERPRETER_TRANS 138#ifdef VFP_INTERPRETER_TRANS
145ARM_INST_PTR INTERPRETER_TRANSLATE(vmls)(unsigned int inst, int index) 139ARM_INST_PTR INTERPRETER_TRANSLATE(vmls)(unsigned int inst, int index)
146{ 140{
147 VFP_DEBUG_TRANSLATE;
148
149 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmls_inst)); 141 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmls_inst));
150 vmls_inst *inst_cream = (vmls_inst *)inst_base->component; 142 vmls_inst *inst_cream = (vmls_inst *)inst_base->component;
151 143
@@ -166,8 +158,6 @@ VMLS_INST:
166 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 158 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
167 CHECK_VFP_ENABLED; 159 CHECK_VFP_ENABLED;
168 160
169 DBG("VMLS :\n");
170
171 vmls_inst *inst_cream = (vmls_inst *)inst_base->component; 161 vmls_inst *inst_cream = (vmls_inst *)inst_base->component;
172 162
173 int ret; 163 int ret;
@@ -193,7 +183,6 @@ DYNCOM_FILL_ACTION(vmls),
193int DYNCOM_TAG(vmls)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc) 183int DYNCOM_TAG(vmls)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
194{ 184{
195 int instr_size = INSTR_SIZE; 185 int instr_size = INSTR_SIZE;
196 //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
197 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc); 186 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
198 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc); 187 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
199 return instr_size; 188 return instr_size;
@@ -201,7 +190,7 @@ int DYNCOM_TAG(vmls)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *
201#endif 190#endif
202#ifdef VFP_DYNCOM_TRANS 191#ifdef VFP_DYNCOM_TRANS
203int DYNCOM_TRANS(vmls)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){ 192int DYNCOM_TRANS(vmls)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
204 DBG("\t\tin %s VMLS instruction is executed out of here.\n", __FUNCTION__); 193 LOG_TRACE(Core_ARM11, "\t\tin %s VMLS instruction is executed out of here.\n", __FUNCTION__);
205 //arch_arm_undef(cpu, bb, instr); 194 //arch_arm_undef(cpu, bb, instr);
206 int m; 195 int m;
207 int n; 196 int n;
@@ -247,10 +236,10 @@ int DYNCOM_TRANS(vmls)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
247 mm = FPBITCAST64(mm); 236 mm = FPBITCAST64(mm);
248 tmp = FPADD(mm,tmp); 237 tmp = FPADD(mm,tmp);
249 mm = TRUNC32(LSHR(IBITCAST64(tmp),CONST64(32))); 238 mm = TRUNC32(LSHR(IBITCAST64(tmp),CONST64(32)));
250 nn = TRUNC32(AND(IBITCAST64(tmp),CONST64(0xffffffff))); 239 nn = TRUNC32(AND(IBITCAST64(tmp),CONST64(0xffffffff)));
251 LETFPS(2*d ,FPBITCAST32(nn)); 240 LETFPS(2*d ,FPBITCAST32(nn));
252 LETFPS(d*2 + 1 , FPBITCAST32(mm)); 241 LETFPS(d*2 + 1 , FPBITCAST32(mm));
253 } 242 }
254 return No_exp; 243 return No_exp;
255} 244}
256#endif 245#endif
@@ -267,8 +256,6 @@ typedef struct _vnmla_inst {
267#ifdef VFP_INTERPRETER_TRANS 256#ifdef VFP_INTERPRETER_TRANS
268ARM_INST_PTR INTERPRETER_TRANSLATE(vnmla)(unsigned int inst, int index) 257ARM_INST_PTR INTERPRETER_TRANSLATE(vnmla)(unsigned int inst, int index)
269{ 258{
270 VFP_DEBUG_TRANSLATE;
271
272 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vnmla_inst)); 259 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vnmla_inst));
273 vnmla_inst *inst_cream = (vnmla_inst *)inst_base->component; 260 vnmla_inst *inst_cream = (vnmla_inst *)inst_base->component;
274 261
@@ -289,8 +276,6 @@ VNMLA_INST:
289 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 276 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
290 CHECK_VFP_ENABLED; 277 CHECK_VFP_ENABLED;
291 278
292 DBG("VNMLA :\n");
293
294 vnmla_inst *inst_cream = (vnmla_inst *)inst_base->component; 279 vnmla_inst *inst_cream = (vnmla_inst *)inst_base->component;
295 280
296 int ret; 281 int ret;
@@ -317,7 +302,6 @@ DYNCOM_FILL_ACTION(vnmla),
317int DYNCOM_TAG(vnmla)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc) 302int DYNCOM_TAG(vnmla)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
318{ 303{
319 int instr_size = INSTR_SIZE; 304 int instr_size = INSTR_SIZE;
320 //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
321 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc); 305 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
322 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc); 306 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
323 return instr_size; 307 return instr_size;
@@ -325,7 +309,7 @@ int DYNCOM_TAG(vnmla)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t
325#endif 309#endif
326#ifdef VFP_DYNCOM_TRANS 310#ifdef VFP_DYNCOM_TRANS
327int DYNCOM_TRANS(vnmla)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){ 311int DYNCOM_TRANS(vnmla)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
328 DBG("\t\tin %s VNMLA instruction is executed out of here.\n", __FUNCTION__); 312 LOG_TRACE(Core_ARM11, "\t\tin %s VNMLA instruction is executed out of here.\n", __FUNCTION__);
329 //arch_arm_undef(cpu, bb, instr); 313 //arch_arm_undef(cpu, bb, instr);
330 int m; 314 int m;
331 int n; 315 int n;
@@ -370,7 +354,7 @@ int DYNCOM_TRANS(vnmla)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
370 mm = OR(SHL(nn,CONST64(32)),mm); 354 mm = OR(SHL(nn,CONST64(32)),mm);
371 mm = FPBITCAST64(mm); 355 mm = FPBITCAST64(mm);
372 tmp = FPADD(FPNEG64(mm),tmp); 356 tmp = FPADD(FPNEG64(mm),tmp);
373 mm = TRUNC32(LSHR(IBITCAST64(tmp),CONST64(32))); 357 mm = TRUNC32(LSHR(IBITCAST64(tmp),CONST64(32)));
374 nn = TRUNC32(AND(IBITCAST64(tmp),CONST64(0xffffffff))); 358 nn = TRUNC32(AND(IBITCAST64(tmp),CONST64(0xffffffff)));
375 LETFPS(2*d ,FPBITCAST32(nn)); 359 LETFPS(2*d ,FPBITCAST32(nn));
376 LETFPS(d*2 + 1 , FPBITCAST32(mm)); 360 LETFPS(d*2 + 1 , FPBITCAST32(mm));
@@ -392,8 +376,6 @@ typedef struct _vnmls_inst {
392#ifdef VFP_INTERPRETER_TRANS 376#ifdef VFP_INTERPRETER_TRANS
393ARM_INST_PTR INTERPRETER_TRANSLATE(vnmls)(unsigned int inst, int index) 377ARM_INST_PTR INTERPRETER_TRANSLATE(vnmls)(unsigned int inst, int index)
394{ 378{
395 VFP_DEBUG_TRANSLATE;
396
397 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vnmls_inst)); 379 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vnmls_inst));
398 vnmls_inst *inst_cream = (vnmls_inst *)inst_base->component; 380 vnmls_inst *inst_cream = (vnmls_inst *)inst_base->component;
399 381
@@ -414,8 +396,6 @@ VNMLS_INST:
414 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 396 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
415 CHECK_VFP_ENABLED; 397 CHECK_VFP_ENABLED;
416 398
417 DBG("VNMLS :\n");
418
419 vnmls_inst *inst_cream = (vnmls_inst *)inst_base->component; 399 vnmls_inst *inst_cream = (vnmls_inst *)inst_base->component;
420 400
421 int ret; 401 int ret;
@@ -441,7 +421,7 @@ DYNCOM_FILL_ACTION(vnmls),
441int DYNCOM_TAG(vnmls)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc) 421int DYNCOM_TAG(vnmls)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
442{ 422{
443 int instr_size = INSTR_SIZE; 423 int instr_size = INSTR_SIZE;
444 DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__); 424 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
445 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc); 425 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
446 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc); 426 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
447 return instr_size; 427 return instr_size;
@@ -449,7 +429,7 @@ int DYNCOM_TAG(vnmls)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t
449#endif 429#endif
450#ifdef VFP_DYNCOM_TRANS 430#ifdef VFP_DYNCOM_TRANS
451int DYNCOM_TRANS(vnmls)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){ 431int DYNCOM_TRANS(vnmls)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
452 DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__); 432 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
453 //arch_arm_undef(cpu, bb, instr); 433 //arch_arm_undef(cpu, bb, instr);
454 int m; 434 int m;
455 int n; 435 int n;
@@ -495,10 +475,10 @@ int DYNCOM_TRANS(vnmls)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
495 mm = FPBITCAST64(mm); 475 mm = FPBITCAST64(mm);
496 tmp = FPADD(FPNEG64(mm),tmp); 476 tmp = FPADD(FPNEG64(mm),tmp);
497 mm = TRUNC32(LSHR(IBITCAST64(tmp),CONST64(32))); 477 mm = TRUNC32(LSHR(IBITCAST64(tmp),CONST64(32)));
498 nn = TRUNC32(AND(IBITCAST64(tmp),CONST64(0xffffffff))); 478 nn = TRUNC32(AND(IBITCAST64(tmp),CONST64(0xffffffff)));
499 LETFPS(2*d ,FPBITCAST32(nn)); 479 LETFPS(2*d ,FPBITCAST32(nn));
500 LETFPS(d*2 + 1 , FPBITCAST32(mm)); 480 LETFPS(d*2 + 1 , FPBITCAST32(mm));
501 } 481 }
502 return No_exp; 482 return No_exp;
503} 483}
504#endif 484#endif
@@ -515,8 +495,6 @@ typedef struct _vnmul_inst {
515#ifdef VFP_INTERPRETER_TRANS 495#ifdef VFP_INTERPRETER_TRANS
516ARM_INST_PTR INTERPRETER_TRANSLATE(vnmul)(unsigned int inst, int index) 496ARM_INST_PTR INTERPRETER_TRANSLATE(vnmul)(unsigned int inst, int index)
517{ 497{
518 VFP_DEBUG_TRANSLATE;
519
520 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vnmul_inst)); 498 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vnmul_inst));
521 vnmul_inst *inst_cream = (vnmul_inst *)inst_base->component; 499 vnmul_inst *inst_cream = (vnmul_inst *)inst_base->component;
522 500
@@ -537,8 +515,6 @@ VNMUL_INST:
537 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 515 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
538 CHECK_VFP_ENABLED; 516 CHECK_VFP_ENABLED;
539 517
540 DBG("VNMUL :\n");
541
542 vnmul_inst *inst_cream = (vnmul_inst *)inst_base->component; 518 vnmul_inst *inst_cream = (vnmul_inst *)inst_base->component;
543 519
544 int ret; 520 int ret;
@@ -564,15 +540,15 @@ DYNCOM_FILL_ACTION(vnmul),
564int DYNCOM_TAG(vnmul)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc) 540int DYNCOM_TAG(vnmul)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
565{ 541{
566 int instr_size = INSTR_SIZE; 542 int instr_size = INSTR_SIZE;
567 DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__); 543 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
568 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc); 544 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
569 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc); 545 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
570 return instr_size; 546 return instr_size;
571} 547}
572#endif 548#endif
573#ifdef VFP_DYNCOM_TRANS 549#ifdef VFP_DYNCOM_TRANS
574int DYNCOM_TRANS(vnmul)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){ 550int DYNCOM_TRANS(vnmul)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
575 DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__); 551 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
576 //arch_arm_undef(cpu, bb, instr); 552 //arch_arm_undef(cpu, bb, instr);
577 int m; 553 int m;
578 int n; 554 int n;
@@ -608,7 +584,7 @@ int DYNCOM_TRANS(vnmul)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
608 tmp = FPMUL(nn,mm); 584 tmp = FPMUL(nn,mm);
609 tmp = FPNEG64(tmp); 585 tmp = FPNEG64(tmp);
610 mm = TRUNC32(LSHR(IBITCAST64(tmp),CONST64(32))); 586 mm = TRUNC32(LSHR(IBITCAST64(tmp),CONST64(32)));
611 nn = TRUNC32(AND(IBITCAST64(tmp),CONST64(0xffffffff))); 587 nn = TRUNC32(AND(IBITCAST64(tmp),CONST64(0xffffffff)));
612 LETFPS(2*d ,FPBITCAST32(nn)); 588 LETFPS(2*d ,FPBITCAST32(nn));
613 LETFPS(d*2 + 1 , FPBITCAST32(mm)); 589 LETFPS(d*2 + 1 , FPBITCAST32(mm));
614 } 590 }
@@ -616,7 +592,6 @@ int DYNCOM_TRANS(vnmul)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
616} 592}
617#endif 593#endif
618 594
619
620/* ----------------------------------------------------------------------- */ 595/* ----------------------------------------------------------------------- */
621/* VMUL */ 596/* VMUL */
622/* cond 1110 0D10 Vn-- Vd-- 101X N0M0 Vm-- */ 597/* cond 1110 0D10 Vn-- Vd-- 101X N0M0 Vm-- */
@@ -629,8 +604,6 @@ typedef struct _vmul_inst {
629#ifdef VFP_INTERPRETER_TRANS 604#ifdef VFP_INTERPRETER_TRANS
630ARM_INST_PTR INTERPRETER_TRANSLATE(vmul)(unsigned int inst, int index) 605ARM_INST_PTR INTERPRETER_TRANSLATE(vmul)(unsigned int inst, int index)
631{ 606{
632 VFP_DEBUG_TRANSLATE;
633
634 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmul_inst)); 607 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmul_inst));
635 vmul_inst *inst_cream = (vmul_inst *)inst_base->component; 608 vmul_inst *inst_cream = (vmul_inst *)inst_base->component;
636 609
@@ -651,8 +624,6 @@ VMUL_INST:
651 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 624 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
652 CHECK_VFP_ENABLED; 625 CHECK_VFP_ENABLED;
653 626
654 DBG("VMUL :\n");
655
656 vmul_inst *inst_cream = (vmul_inst *)inst_base->component; 627 vmul_inst *inst_cream = (vmul_inst *)inst_base->component;
657 628
658 int ret; 629 int ret;
@@ -678,7 +649,6 @@ DYNCOM_FILL_ACTION(vmul),
678int DYNCOM_TAG(vmul)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc) 649int DYNCOM_TAG(vmul)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
679{ 650{
680 int instr_size = INSTR_SIZE; 651 int instr_size = INSTR_SIZE;
681 //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
682 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc); 652 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
683 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc); 653 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
684 return instr_size; 654 return instr_size;
@@ -686,8 +656,7 @@ int DYNCOM_TAG(vmul)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *
686#endif 656#endif
687#ifdef VFP_DYNCOM_TRANS 657#ifdef VFP_DYNCOM_TRANS
688int DYNCOM_TRANS(vmul)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){ 658int DYNCOM_TRANS(vmul)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
689 DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__); 659 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
690 //printf("\n\n\t\tin %s instruction is executed out.\n\n", __FUNCTION__);
691 //arch_arm_undef(cpu, bb, instr); 660 //arch_arm_undef(cpu, bb, instr);
692 int m; 661 int m;
693 int n; 662 int n;
@@ -728,7 +697,7 @@ int DYNCOM_TRANS(vmul)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
728 hi64 = ZEXT64(hi); 697 hi64 = ZEXT64(hi);
729 lo64 = ZEXT64(lo); 698 lo64 = ZEXT64(lo);
730 v64 = OR(SHL(hi64,CONST64(32)),lo64); 699 v64 = OR(SHL(hi64,CONST64(32)),lo64);
731 Value *n0 = FPBITCAST64(v64); 700 Value *n0 = FPBITCAST64(v64);
732 tmp = FPMUL(n0,m0); 701 tmp = FPMUL(n0,m0);
733 Value *val64 = IBITCAST64(tmp); 702 Value *val64 = IBITCAST64(tmp);
734 hi = LSHR(val64,CONST64(32)); 703 hi = LSHR(val64,CONST64(32));
@@ -736,7 +705,7 @@ int DYNCOM_TRANS(vmul)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
736 hi = TRUNC32(hi); 705 hi = TRUNC32(hi);
737 lo = TRUNC32(lo); 706 lo = TRUNC32(lo);
738 hi = FPBITCAST32(hi); 707 hi = FPBITCAST32(hi);
739 lo = FPBITCAST32(lo); 708 lo = FPBITCAST32(lo);
740 LETFPS(2*d ,lo); 709 LETFPS(2*d ,lo);
741 LETFPS(d*2 + 1 , hi); 710 LETFPS(d*2 + 1 , hi);
742 } 711 }
@@ -756,8 +725,6 @@ typedef struct _vadd_inst {
756#ifdef VFP_INTERPRETER_TRANS 725#ifdef VFP_INTERPRETER_TRANS
757ARM_INST_PTR INTERPRETER_TRANSLATE(vadd)(unsigned int inst, int index) 726ARM_INST_PTR INTERPRETER_TRANSLATE(vadd)(unsigned int inst, int index)
758{ 727{
759 VFP_DEBUG_TRANSLATE;
760
761 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vadd_inst)); 728 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vadd_inst));
762 vadd_inst *inst_cream = (vadd_inst *)inst_base->component; 729 vadd_inst *inst_cream = (vadd_inst *)inst_base->component;
763 730
@@ -778,8 +745,6 @@ VADD_INST:
778 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 745 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
779 CHECK_VFP_ENABLED; 746 CHECK_VFP_ENABLED;
780 747
781 DBG("VADD :\n");
782
783 vadd_inst *inst_cream = (vadd_inst *)inst_base->component; 748 vadd_inst *inst_cream = (vadd_inst *)inst_base->component;
784 749
785 int ret; 750 int ret;
@@ -805,7 +770,7 @@ DYNCOM_FILL_ACTION(vadd),
805int DYNCOM_TAG(vadd)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc) 770int DYNCOM_TAG(vadd)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
806{ 771{
807 int instr_size = INSTR_SIZE; 772 int instr_size = INSTR_SIZE;
808 DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__); 773 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
809 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc); 774 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
810 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc); 775 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
811 return instr_size; 776 return instr_size;
@@ -813,7 +778,7 @@ int DYNCOM_TAG(vadd)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *
813#endif 778#endif
814#ifdef VFP_DYNCOM_TRANS 779#ifdef VFP_DYNCOM_TRANS
815int DYNCOM_TRANS(vadd)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){ 780int DYNCOM_TRANS(vadd)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
816 DBG("\t\tin %s instruction will implement out of JIT.\n", __FUNCTION__); 781 LOG_TRACE(Core_ARM11, "\t\tin %s instruction will implement out of JIT.\n", __FUNCTION__);
817 //arch_arm_undef(cpu, bb, instr); 782 //arch_arm_undef(cpu, bb, instr);
818 int m; 783 int m;
819 int n; 784 int n;
@@ -849,7 +814,7 @@ int DYNCOM_TRANS(vadd)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
849 hi64 = ZEXT64(hi); 814 hi64 = ZEXT64(hi);
850 lo64 = ZEXT64(lo); 815 lo64 = ZEXT64(lo);
851 v64 = OR(SHL(hi64,CONST64(32)),lo64); 816 v64 = OR(SHL(hi64,CONST64(32)),lo64);
852 Value *n0 = FPBITCAST64(v64); 817 Value *n0 = FPBITCAST64(v64);
853 tmp = FPADD(n0,m0); 818 tmp = FPADD(n0,m0);
854 Value *val64 = IBITCAST64(tmp); 819 Value *val64 = IBITCAST64(tmp);
855 hi = LSHR(val64,CONST64(32)); 820 hi = LSHR(val64,CONST64(32));
@@ -857,7 +822,7 @@ int DYNCOM_TRANS(vadd)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
857 hi = TRUNC32(hi); 822 hi = TRUNC32(hi);
858 lo = TRUNC32(lo); 823 lo = TRUNC32(lo);
859 hi = FPBITCAST32(hi); 824 hi = FPBITCAST32(hi);
860 lo = FPBITCAST32(lo); 825 lo = FPBITCAST32(lo);
861 LETFPS(2*d ,lo); 826 LETFPS(2*d ,lo);
862 LETFPS(d*2 + 1 , hi); 827 LETFPS(d*2 + 1 , hi);
863 } 828 }
@@ -877,8 +842,6 @@ typedef struct _vsub_inst {
877#ifdef VFP_INTERPRETER_TRANS 842#ifdef VFP_INTERPRETER_TRANS
878ARM_INST_PTR INTERPRETER_TRANSLATE(vsub)(unsigned int inst, int index) 843ARM_INST_PTR INTERPRETER_TRANSLATE(vsub)(unsigned int inst, int index)
879{ 844{
880 VFP_DEBUG_TRANSLATE;
881
882 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vsub_inst)); 845 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vsub_inst));
883 vsub_inst *inst_cream = (vsub_inst *)inst_base->component; 846 vsub_inst *inst_cream = (vsub_inst *)inst_base->component;
884 847
@@ -899,8 +862,6 @@ VSUB_INST:
899 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 862 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
900 CHECK_VFP_ENABLED; 863 CHECK_VFP_ENABLED;
901 864
902 DBG("VSUB :\n");
903
904 vsub_inst *inst_cream = (vsub_inst *)inst_base->component; 865 vsub_inst *inst_cream = (vsub_inst *)inst_base->component;
905 866
906 int ret; 867 int ret;
@@ -932,7 +893,7 @@ int DYNCOM_TAG(vsub)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *
932#endif 893#endif
933#ifdef VFP_DYNCOM_TRANS 894#ifdef VFP_DYNCOM_TRANS
934int DYNCOM_TRANS(vsub)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){ 895int DYNCOM_TRANS(vsub)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
935 DBG("\t\tin %s instr=0x%x, instruction is executed out of JIT.\n", __FUNCTION__, instr); 896 LOG_TRACE(Core_ARM11, "\t\tin %s instr=0x%x, instruction is executed out of JIT.\n", __FUNCTION__, instr);
936 //arch_arm_undef(cpu, bb, instr); 897 //arch_arm_undef(cpu, bb, instr);
937 int m; 898 int m;
938 int n; 899 int n;
@@ -968,7 +929,7 @@ int DYNCOM_TRANS(vsub)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
968 hi64 = ZEXT64(hi); 929 hi64 = ZEXT64(hi);
969 lo64 = ZEXT64(lo); 930 lo64 = ZEXT64(lo);
970 v64 = OR(SHL(hi64,CONST64(32)),lo64); 931 v64 = OR(SHL(hi64,CONST64(32)),lo64);
971 Value *n0 = FPBITCAST64(v64); 932 Value *n0 = FPBITCAST64(v64);
972 tmp = FPSUB(n0,m0); 933 tmp = FPSUB(n0,m0);
973 Value *val64 = IBITCAST64(tmp); 934 Value *val64 = IBITCAST64(tmp);
974 hi = LSHR(val64,CONST64(32)); 935 hi = LSHR(val64,CONST64(32));
@@ -976,10 +937,10 @@ int DYNCOM_TRANS(vsub)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
976 hi = TRUNC32(hi); 937 hi = TRUNC32(hi);
977 lo = TRUNC32(lo); 938 lo = TRUNC32(lo);
978 hi = FPBITCAST32(hi); 939 hi = FPBITCAST32(hi);
979 lo = FPBITCAST32(lo); 940 lo = FPBITCAST32(lo);
980 LETFPS(2*d ,lo); 941 LETFPS(2*d ,lo);
981 LETFPS(d*2 + 1 , hi); 942 LETFPS(d*2 + 1 , hi);
982 } 943 }
983 return No_exp; 944 return No_exp;
984} 945}
985#endif 946#endif
@@ -996,8 +957,6 @@ typedef struct _vdiv_inst {
996#ifdef VFP_INTERPRETER_TRANS 957#ifdef VFP_INTERPRETER_TRANS
997ARM_INST_PTR INTERPRETER_TRANSLATE(vdiv)(unsigned int inst, int index) 958ARM_INST_PTR INTERPRETER_TRANSLATE(vdiv)(unsigned int inst, int index)
998{ 959{
999 VFP_DEBUG_TRANSLATE;
1000
1001 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vdiv_inst)); 960 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vdiv_inst));
1002 vdiv_inst *inst_cream = (vdiv_inst *)inst_base->component; 961 vdiv_inst *inst_cream = (vdiv_inst *)inst_base->component;
1003 962
@@ -1018,8 +977,6 @@ VDIV_INST:
1018 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 977 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
1019 CHECK_VFP_ENABLED; 978 CHECK_VFP_ENABLED;
1020 979
1021 DBG("VDIV :\n");
1022
1023 vdiv_inst *inst_cream = (vdiv_inst *)inst_base->component; 980 vdiv_inst *inst_cream = (vdiv_inst *)inst_base->component;
1024 981
1025 int ret; 982 int ret;
@@ -1045,7 +1002,7 @@ DYNCOM_FILL_ACTION(vdiv),
1045int DYNCOM_TAG(vdiv)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc) 1002int DYNCOM_TAG(vdiv)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
1046{ 1003{
1047 int instr_size = INSTR_SIZE; 1004 int instr_size = INSTR_SIZE;
1048 DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__); 1005 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
1049 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc); 1006 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
1050 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc); 1007 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
1051 return instr_size; 1008 return instr_size;
@@ -1053,7 +1010,7 @@ int DYNCOM_TAG(vdiv)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *
1053#endif 1010#endif
1054#ifdef VFP_DYNCOM_TRANS 1011#ifdef VFP_DYNCOM_TRANS
1055int DYNCOM_TRANS(vdiv)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){ 1012int DYNCOM_TRANS(vdiv)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
1056 DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__); 1013 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
1057 //arch_arm_undef(cpu, bb, instr); 1014 //arch_arm_undef(cpu, bb, instr);
1058 int m; 1015 int m;
1059 int n; 1016 int n;
@@ -1089,7 +1046,7 @@ int DYNCOM_TRANS(vdiv)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
1089 hi64 = ZEXT64(hi); 1046 hi64 = ZEXT64(hi);
1090 lo64 = ZEXT64(lo); 1047 lo64 = ZEXT64(lo);
1091 v64 = OR(SHL(hi64,CONST64(32)),lo64); 1048 v64 = OR(SHL(hi64,CONST64(32)),lo64);
1092 Value *n0 = FPBITCAST64(v64); 1049 Value *n0 = FPBITCAST64(v64);
1093 tmp = FPDIV(n0,m0); 1050 tmp = FPDIV(n0,m0);
1094 Value *val64 = IBITCAST64(tmp); 1051 Value *val64 = IBITCAST64(tmp);
1095 hi = LSHR(val64,CONST64(32)); 1052 hi = LSHR(val64,CONST64(32));
@@ -1097,10 +1054,10 @@ int DYNCOM_TRANS(vdiv)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
1097 hi = TRUNC32(hi); 1054 hi = TRUNC32(hi);
1098 lo = TRUNC32(lo); 1055 lo = TRUNC32(lo);
1099 hi = FPBITCAST32(hi); 1056 hi = FPBITCAST32(hi);
1100 lo = FPBITCAST32(lo); 1057 lo = FPBITCAST32(lo);
1101 LETFPS(2*d ,lo); 1058 LETFPS(2*d ,lo);
1102 LETFPS(d*2 + 1 , hi); 1059 LETFPS(d*2 + 1 , hi);
1103 } 1060 }
1104 return No_exp; 1061 return No_exp;
1105} 1062}
1106#endif 1063#endif
@@ -1119,8 +1076,6 @@ typedef struct _vmovi_inst {
1119#ifdef VFP_INTERPRETER_TRANS 1076#ifdef VFP_INTERPRETER_TRANS
1120ARM_INST_PTR INTERPRETER_TRANSLATE(vmovi)(unsigned int inst, int index) 1077ARM_INST_PTR INTERPRETER_TRANSLATE(vmovi)(unsigned int inst, int index)
1121{ 1078{
1122 VFP_DEBUG_TRANSLATE;
1123
1124 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmovi_inst)); 1079 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmovi_inst));
1125 vmovi_inst *inst_cream = (vmovi_inst *)inst_base->component; 1080 vmovi_inst *inst_cream = (vmovi_inst *)inst_base->component;
1126 1081
@@ -1163,14 +1118,14 @@ DYNCOM_FILL_ACTION(vmovi),
1163int DYNCOM_TAG(vmovi)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc) 1118int DYNCOM_TAG(vmovi)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
1164{ 1119{
1165 int instr_size = INSTR_SIZE; 1120 int instr_size = INSTR_SIZE;
1166 DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__); 1121 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
1167 arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc); 1122 arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
1168 return instr_size; 1123 return instr_size;
1169} 1124}
1170#endif 1125#endif
1171#ifdef VFP_DYNCOM_TRANS 1126#ifdef VFP_DYNCOM_TRANS
1172int DYNCOM_TRANS(vmovi)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){ 1127int DYNCOM_TRANS(vmovi)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
1173 DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__); 1128 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
1174 //arch_arm_undef(cpu, bb, instr); 1129 //arch_arm_undef(cpu, bb, instr);
1175 int single = (BIT(8) == 0); 1130 int single = (BIT(8) == 0);
1176 int d; 1131 int d;
@@ -1210,8 +1165,6 @@ typedef struct _vmovr_inst {
1210#ifdef VFP_INTERPRETER_TRANS 1165#ifdef VFP_INTERPRETER_TRANS
1211ARM_INST_PTR INTERPRETER_TRANSLATE(vmovr)(unsigned int inst, int index) 1166ARM_INST_PTR INTERPRETER_TRANSLATE(vmovr)(unsigned int inst, int index)
1212{ 1167{
1213 VFP_DEBUG_TRANSLATE;
1214
1215 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmovr_inst)); 1168 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmovr_inst));
1216 vmovr_inst *inst_cream = (vmovr_inst *)inst_base->component; 1169 vmovr_inst *inst_cream = (vmovr_inst *)inst_base->component;
1217 1170
@@ -1251,7 +1204,6 @@ int DYNCOM_TAG(vmovr)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t
1251{ 1204{
1252 int instr_size = INSTR_SIZE; 1205 int instr_size = INSTR_SIZE;
1253 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc); 1206 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
1254 DBG("In %s, pc=0x%x, next_pc=0x%x\n", __FUNCTION__, pc, *next_pc);
1255 if(instr >> 28 != 0xe) 1207 if(instr >> 28 != 0xe)
1256 *tag |= TAG_CONDITIONAL; 1208 *tag |= TAG_CONDITIONAL;
1257 1209
@@ -1260,7 +1212,6 @@ int DYNCOM_TAG(vmovr)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t
1260#endif 1212#endif
1261#ifdef VFP_DYNCOM_TRANS 1213#ifdef VFP_DYNCOM_TRANS
1262int DYNCOM_TRANS(vmovr)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){ 1214int DYNCOM_TRANS(vmovr)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
1263 DBG("\t\tin %s VMOV \n", __FUNCTION__);
1264 int single = BIT(8) == 0; 1215 int single = BIT(8) == 0;
1265 int d = (single ? BITS(12,15)<<1 | BIT(22) : BIT(22) << 4 | BITS(12,15)); 1216 int d = (single ? BITS(12,15)<<1 | BIT(22) : BIT(22) << 4 | BITS(12,15));
1266 int m = (single ? BITS(0, 3)<<1 | BIT(5) : BITS(0, 3) | BIT(5)<<4); 1217 int m = (single ? BITS(0, 3)<<1 | BIT(5) : BITS(0, 3) | BIT(5)<<4);
@@ -1311,8 +1262,6 @@ VABS_INST:
1311 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 1262 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
1312 CHECK_VFP_ENABLED; 1263 CHECK_VFP_ENABLED;
1313 1264
1314 DBG("VABS :\n");
1315
1316 vabs_inst *inst_cream = (vabs_inst *)inst_base->component; 1265 vabs_inst *inst_cream = (vabs_inst *)inst_base->component;
1317 1266
1318 int ret; 1267 int ret;
@@ -1338,7 +1287,6 @@ DYNCOM_FILL_ACTION(vabs),
1338int DYNCOM_TAG(vabs)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc) 1287int DYNCOM_TAG(vabs)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
1339{ 1288{
1340 int instr_size = INSTR_SIZE; 1289 int instr_size = INSTR_SIZE;
1341 //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
1342 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc); 1290 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
1343 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc); 1291 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
1344 return instr_size; 1292 return instr_size;
@@ -1346,7 +1294,6 @@ int DYNCOM_TAG(vabs)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *
1346#endif 1294#endif
1347#ifdef VFP_DYNCOM_TRANS 1295#ifdef VFP_DYNCOM_TRANS
1348int DYNCOM_TRANS(vabs)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){ 1296int DYNCOM_TRANS(vabs)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
1349 //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
1350 //arch_arm_undef(cpu, bb, instr); 1297 //arch_arm_undef(cpu, bb, instr);
1351 int single = BIT(8) == 0; 1298 int single = BIT(8) == 0;
1352 int d = (single ? BITS(12,15)<<1 | BIT(22) : BIT(22) << 4 | BITS(12,15)); 1299 int d = (single ? BITS(12,15)<<1 | BIT(22) : BIT(22) << 4 | BITS(12,15));
@@ -1376,7 +1323,7 @@ int DYNCOM_TRANS(vabs)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
1376 hi = TRUNC32(hi); 1323 hi = TRUNC32(hi);
1377 lo = TRUNC32(lo); 1324 lo = TRUNC32(lo);
1378 hi = FPBITCAST32(hi); 1325 hi = FPBITCAST32(hi);
1379 lo = FPBITCAST32(lo); 1326 lo = FPBITCAST32(lo);
1380 LETFPS(2*d ,lo); 1327 LETFPS(2*d ,lo);
1381 LETFPS(d*2 + 1 , hi); 1328 LETFPS(d*2 + 1 , hi);
1382 } 1329 }
@@ -1417,8 +1364,6 @@ VNEG_INST:
1417 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 1364 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
1418 CHECK_VFP_ENABLED; 1365 CHECK_VFP_ENABLED;
1419 1366
1420 DBG("VNEG :\n");
1421
1422 vneg_inst *inst_cream = (vneg_inst *)inst_base->component; 1367 vneg_inst *inst_cream = (vneg_inst *)inst_base->component;
1423 1368
1424 int ret; 1369 int ret;
@@ -1444,7 +1389,7 @@ DYNCOM_FILL_ACTION(vneg),
1444int DYNCOM_TAG(vneg)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc) 1389int DYNCOM_TAG(vneg)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
1445{ 1390{
1446 int instr_size = INSTR_SIZE; 1391 int instr_size = INSTR_SIZE;
1447 DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__); 1392 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
1448 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc); 1393 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
1449 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc); 1394 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
1450 return instr_size; 1395 return instr_size;
@@ -1452,7 +1397,7 @@ int DYNCOM_TAG(vneg)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *
1452#endif 1397#endif
1453#ifdef VFP_DYNCOM_TRANS 1398#ifdef VFP_DYNCOM_TRANS
1454int DYNCOM_TRANS(vneg)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){ 1399int DYNCOM_TRANS(vneg)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
1455 DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__); 1400 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
1456 //arch_arm_undef(cpu, bb, instr); 1401 //arch_arm_undef(cpu, bb, instr);
1457 int single = BIT(8) == 0; 1402 int single = BIT(8) == 0;
1458 int d = (single ? BITS(12,15)<<1 | BIT(22) : BIT(22) << 4 | BITS(12,15)); 1403 int d = (single ? BITS(12,15)<<1 | BIT(22) : BIT(22) << 4 | BITS(12,15));
@@ -1482,7 +1427,7 @@ int DYNCOM_TRANS(vneg)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
1482 hi = TRUNC32(hi); 1427 hi = TRUNC32(hi);
1483 lo = TRUNC32(lo); 1428 lo = TRUNC32(lo);
1484 hi = FPBITCAST32(hi); 1429 hi = FPBITCAST32(hi);
1485 lo = FPBITCAST32(lo); 1430 lo = FPBITCAST32(lo);
1486 LETFPS(2*d ,lo); 1431 LETFPS(2*d ,lo);
1487 LETFPS(d*2 + 1 , hi); 1432 LETFPS(d*2 + 1 , hi);
1488 } 1433 }
@@ -1502,8 +1447,6 @@ typedef struct _vsqrt_inst {
1502#ifdef VFP_INTERPRETER_TRANS 1447#ifdef VFP_INTERPRETER_TRANS
1503ARM_INST_PTR INTERPRETER_TRANSLATE(vsqrt)(unsigned int inst, int index) 1448ARM_INST_PTR INTERPRETER_TRANSLATE(vsqrt)(unsigned int inst, int index)
1504{ 1449{
1505 VFP_DEBUG_TRANSLATE;
1506
1507 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vsqrt_inst)); 1450 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vsqrt_inst));
1508 vsqrt_inst *inst_cream = (vsqrt_inst *)inst_base->component; 1451 vsqrt_inst *inst_cream = (vsqrt_inst *)inst_base->component;
1509 1452
@@ -1524,8 +1467,6 @@ VSQRT_INST:
1524 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 1467 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
1525 CHECK_VFP_ENABLED; 1468 CHECK_VFP_ENABLED;
1526 1469
1527 DBG("VSQRT :\n");
1528
1529 vsqrt_inst *inst_cream = (vsqrt_inst *)inst_base->component; 1470 vsqrt_inst *inst_cream = (vsqrt_inst *)inst_base->component;
1530 1471
1531 int ret; 1472 int ret;
@@ -1551,7 +1492,7 @@ DYNCOM_FILL_ACTION(vsqrt),
1551int DYNCOM_TAG(vsqrt)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc) 1492int DYNCOM_TAG(vsqrt)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
1552{ 1493{
1553 int instr_size = INSTR_SIZE; 1494 int instr_size = INSTR_SIZE;
1554 DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__); 1495 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
1555 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc); 1496 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
1556 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc); 1497 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
1557 return instr_size; 1498 return instr_size;
@@ -1559,7 +1500,7 @@ int DYNCOM_TAG(vsqrt)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t
1559#endif 1500#endif
1560#ifdef VFP_DYNCOM_TRANS 1501#ifdef VFP_DYNCOM_TRANS
1561int DYNCOM_TRANS(vsqrt)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){ 1502int DYNCOM_TRANS(vsqrt)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
1562 DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__); 1503 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
1563 //arch_arm_undef(cpu, bb, instr); 1504 //arch_arm_undef(cpu, bb, instr);
1564 int dp_op = (BIT(8) == 1); 1505 int dp_op = (BIT(8) == 1);
1565 int d = dp_op ? BITS(12,15) | BIT(22) << 4 : BIT(22) | BITS(12,15) << 1; 1506 int d = dp_op ? BITS(12,15) | BIT(22) << 4 : BIT(22) | BITS(12,15) << 1;
@@ -1572,7 +1513,7 @@ int DYNCOM_TRANS(vsqrt)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
1572 v = OR(v,tmp); 1513 v = OR(v,tmp);
1573 v = FPSQRT(FPBITCAST64(v)); 1514 v = FPSQRT(FPBITCAST64(v));
1574 tmp = TRUNC32(LSHR(IBITCAST64(v),CONST64(32))); 1515 tmp = TRUNC32(LSHR(IBITCAST64(v),CONST64(32)));
1575 v = TRUNC32(AND(IBITCAST64(v),CONST64( 0xffffffff))); 1516 v = TRUNC32(AND(IBITCAST64(v),CONST64( 0xffffffff)));
1576 LETFPS(2 * d , FPBITCAST32(v)); 1517 LETFPS(2 * d , FPBITCAST32(v));
1577 LETFPS(2 * d + 1, FPBITCAST32(tmp)); 1518 LETFPS(2 * d + 1, FPBITCAST32(tmp));
1578 }else { 1519 }else {
@@ -1597,8 +1538,6 @@ typedef struct _vcmp_inst {
1597#ifdef VFP_INTERPRETER_TRANS 1538#ifdef VFP_INTERPRETER_TRANS
1598ARM_INST_PTR INTERPRETER_TRANSLATE(vcmp)(unsigned int inst, int index) 1539ARM_INST_PTR INTERPRETER_TRANSLATE(vcmp)(unsigned int inst, int index)
1599{ 1540{
1600 VFP_DEBUG_TRANSLATE;
1601
1602 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vcmp_inst)); 1541 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vcmp_inst));
1603 vcmp_inst *inst_cream = (vcmp_inst *)inst_base->component; 1542 vcmp_inst *inst_cream = (vcmp_inst *)inst_base->component;
1604 1543
@@ -1619,8 +1558,6 @@ VCMP_INST:
1619 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 1558 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
1620 CHECK_VFP_ENABLED; 1559 CHECK_VFP_ENABLED;
1621 1560
1622 DBG("VCMP(1) :\n");
1623
1624 vcmp_inst *inst_cream = (vcmp_inst *)inst_base->component; 1561 vcmp_inst *inst_cream = (vcmp_inst *)inst_base->component;
1625 1562
1626 int ret; 1563 int ret;
@@ -1653,7 +1590,7 @@ int DYNCOM_TAG(vcmp)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *
1653#endif 1590#endif
1654#ifdef VFP_DYNCOM_TRANS 1591#ifdef VFP_DYNCOM_TRANS
1655int DYNCOM_TRANS(vcmp)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){ 1592int DYNCOM_TRANS(vcmp)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
1656 DBG("\t\tin %s instruction is executed out of JIT.\n", __FUNCTION__); 1593 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is executed out of JIT.\n", __FUNCTION__);
1657 //arch_arm_undef(cpu, bb, instr); 1594 //arch_arm_undef(cpu, bb, instr);
1658 int dp_op = (BIT(8) == 1); 1595 int dp_op = (BIT(8) == 1);
1659 int d = dp_op ? BITS(12,15) | BIT(22) << 4 : BIT(22) | BITS(12,15) << 1; 1596 int d = dp_op ? BITS(12,15) | BIT(22) << 4 : BIT(22) | BITS(12,15) << 1;
@@ -1675,7 +1612,7 @@ int DYNCOM_TRANS(vcmp)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
1675 v = OR(v,tmp); 1612 v = OR(v,tmp);
1676 z = FPCMP_OEQ(FPBITCAST64(v),FPBITCAST64(v1)); 1613 z = FPCMP_OEQ(FPBITCAST64(v),FPBITCAST64(v1));
1677 n = FPCMP_OLT(FPBITCAST64(v),FPBITCAST64(v1)); 1614 n = FPCMP_OLT(FPBITCAST64(v),FPBITCAST64(v1));
1678 c = FPCMP_OGE(FPBITCAST64(v),FPBITCAST64(v1)); 1615 c = FPCMP_OGE(FPBITCAST64(v),FPBITCAST64(v1));
1679 tmp = FPCMP_UNO(FPBITCAST64(v),FPBITCAST64(v1)); 1616 tmp = FPCMP_UNO(FPBITCAST64(v),FPBITCAST64(v1));
1680 v1 = tmp; 1617 v1 = tmp;
1681 c = OR(c,tmp); 1618 c = OR(c,tmp);
@@ -1683,14 +1620,14 @@ int DYNCOM_TRANS(vcmp)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
1683 z = SHL(ZEXT32(z),CONST32(30)); 1620 z = SHL(ZEXT32(z),CONST32(30));
1684 c = SHL(ZEXT32(c),CONST32(29)); 1621 c = SHL(ZEXT32(c),CONST32(29));
1685 v1 = SHL(ZEXT32(v1),CONST(28)); 1622 v1 = SHL(ZEXT32(v1),CONST(28));
1686 nzcv = OR(OR(OR(n,z),c),v1); 1623 nzcv = OR(OR(OR(n,z),c),v1);
1687 v = R(VFP_FPSCR); 1624 v = R(VFP_FPSCR);
1688 tmp = OR(nzcv,AND(v,CONST32(0x0fffffff))); 1625 tmp = OR(nzcv,AND(v,CONST32(0x0fffffff)));
1689 LET(VFP_FPSCR,tmp); 1626 LET(VFP_FPSCR,tmp);
1690 }else { 1627 }else {
1691 z = FPCMP_OEQ(FR32(d),FR32(m)); 1628 z = FPCMP_OEQ(FR32(d),FR32(m));
1692 n = FPCMP_OLT(FR32(d),FR32(m)); 1629 n = FPCMP_OLT(FR32(d),FR32(m));
1693 c = FPCMP_OGE(FR32(d),FR32(m)); 1630 c = FPCMP_OGE(FR32(d),FR32(m));
1694 tmp = FPCMP_UNO(FR32(d),FR32(m)); 1631 tmp = FPCMP_UNO(FR32(d),FR32(m));
1695 c = OR(c,tmp); 1632 c = OR(c,tmp);
1696 v1 = tmp; 1633 v1 = tmp;
@@ -1698,7 +1635,7 @@ int DYNCOM_TRANS(vcmp)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
1698 z = SHL(ZEXT32(z),CONST32(30)); 1635 z = SHL(ZEXT32(z),CONST32(30));
1699 c = SHL(ZEXT32(c),CONST32(29)); 1636 c = SHL(ZEXT32(c),CONST32(29));
1700 v1 = SHL(ZEXT32(v1),CONST(28)); 1637 v1 = SHL(ZEXT32(v1),CONST(28));
1701 nzcv = OR(OR(OR(n,z),c),v1); 1638 nzcv = OR(OR(OR(n,z),c),v1);
1702 v = R(VFP_FPSCR); 1639 v = R(VFP_FPSCR);
1703 tmp = OR(nzcv,AND(v,CONST32(0x0fffffff))); 1640 tmp = OR(nzcv,AND(v,CONST32(0x0fffffff)));
1704 LET(VFP_FPSCR,tmp); 1641 LET(VFP_FPSCR,tmp);
@@ -1719,8 +1656,6 @@ typedef struct _vcmp2_inst {
1719#ifdef VFP_INTERPRETER_TRANS 1656#ifdef VFP_INTERPRETER_TRANS
1720ARM_INST_PTR INTERPRETER_TRANSLATE(vcmp2)(unsigned int inst, int index) 1657ARM_INST_PTR INTERPRETER_TRANSLATE(vcmp2)(unsigned int inst, int index)
1721{ 1658{
1722 VFP_DEBUG_TRANSLATE;
1723
1724 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vcmp2_inst)); 1659 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vcmp2_inst));
1725 vcmp2_inst *inst_cream = (vcmp2_inst *)inst_base->component; 1660 vcmp2_inst *inst_cream = (vcmp2_inst *)inst_base->component;
1726 1661
@@ -1741,8 +1676,6 @@ VCMP2_INST:
1741 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 1676 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
1742 CHECK_VFP_ENABLED; 1677 CHECK_VFP_ENABLED;
1743 1678
1744 DBG("VCMP(2) :\n");
1745
1746 vcmp2_inst *inst_cream = (vcmp2_inst *)inst_base->component; 1679 vcmp2_inst *inst_cream = (vcmp2_inst *)inst_base->component;
1747 1680
1748 int ret; 1681 int ret;
@@ -1775,7 +1708,7 @@ int DYNCOM_TAG(vcmp2)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t
1775#endif 1708#endif
1776#ifdef VFP_DYNCOM_TRANS 1709#ifdef VFP_DYNCOM_TRANS
1777int DYNCOM_TRANS(vcmp2)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){ 1710int DYNCOM_TRANS(vcmp2)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
1778 DBG("\t\tin %s instruction will executed out of JIT.\n", __FUNCTION__); 1711 LOG_TRACE(Core_ARM11, "\t\tin %s instruction will executed out of JIT.\n", __FUNCTION__);
1779 //arch_arm_undef(cpu, bb, instr); 1712 //arch_arm_undef(cpu, bb, instr);
1780 int dp_op = (BIT(8) == 1); 1713 int dp_op = (BIT(8) == 1);
1781 int d = dp_op ? BITS(12,15) | BIT(22) << 4 : BIT(22) | BITS(12,15) << 1; 1714 int d = dp_op ? BITS(12,15) | BIT(22) << 4 : BIT(22) | BITS(12,15) << 1;
@@ -1795,7 +1728,7 @@ int DYNCOM_TRANS(vcmp2)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
1795 v = OR(v,tmp); 1728 v = OR(v,tmp);
1796 z = FPCMP_OEQ(FPBITCAST64(v),FPBITCAST64(v1)); 1729 z = FPCMP_OEQ(FPBITCAST64(v),FPBITCAST64(v1));
1797 n = FPCMP_OLT(FPBITCAST64(v),FPBITCAST64(v1)); 1730 n = FPCMP_OLT(FPBITCAST64(v),FPBITCAST64(v1));
1798 c = FPCMP_OGE(FPBITCAST64(v),FPBITCAST64(v1)); 1731 c = FPCMP_OGE(FPBITCAST64(v),FPBITCAST64(v1));
1799 tmp = FPCMP_UNO(FPBITCAST64(v),FPBITCAST64(v1)); 1732 tmp = FPCMP_UNO(FPBITCAST64(v),FPBITCAST64(v1));
1800 v1 = tmp; 1733 v1 = tmp;
1801 c = OR(c,tmp); 1734 c = OR(c,tmp);
@@ -1803,7 +1736,7 @@ int DYNCOM_TRANS(vcmp2)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
1803 z = SHL(ZEXT32(z),CONST32(30)); 1736 z = SHL(ZEXT32(z),CONST32(30));
1804 c = SHL(ZEXT32(c),CONST32(29)); 1737 c = SHL(ZEXT32(c),CONST32(29));
1805 v1 = SHL(ZEXT32(v1),CONST(28)); 1738 v1 = SHL(ZEXT32(v1),CONST(28));
1806 nzcv = OR(OR(OR(n,z),c),v1); 1739 nzcv = OR(OR(OR(n,z),c),v1);
1807 v = R(VFP_FPSCR); 1740 v = R(VFP_FPSCR);
1808 tmp = OR(nzcv,AND(v,CONST32(0x0fffffff))); 1741 tmp = OR(nzcv,AND(v,CONST32(0x0fffffff)));
1809 LET(VFP_FPSCR,tmp); 1742 LET(VFP_FPSCR,tmp);
@@ -1812,7 +1745,7 @@ int DYNCOM_TRANS(vcmp2)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
1812 v1 = FPBITCAST32(v1); 1745 v1 = FPBITCAST32(v1);
1813 z = FPCMP_OEQ(FR32(d),v1); 1746 z = FPCMP_OEQ(FR32(d),v1);
1814 n = FPCMP_OLT(FR32(d),v1); 1747 n = FPCMP_OLT(FR32(d),v1);
1815 c = FPCMP_OGE(FR32(d),v1); 1748 c = FPCMP_OGE(FR32(d),v1);
1816 tmp = FPCMP_UNO(FR32(d),v1); 1749 tmp = FPCMP_UNO(FR32(d),v1);
1817 c = OR(c,tmp); 1750 c = OR(c,tmp);
1818 v1 = tmp; 1751 v1 = tmp;
@@ -1820,7 +1753,7 @@ int DYNCOM_TRANS(vcmp2)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
1820 z = SHL(ZEXT32(z),CONST32(30)); 1753 z = SHL(ZEXT32(z),CONST32(30));
1821 c = SHL(ZEXT32(c),CONST32(29)); 1754 c = SHL(ZEXT32(c),CONST32(29));
1822 v1 = SHL(ZEXT32(v1),CONST(28)); 1755 v1 = SHL(ZEXT32(v1),CONST(28));
1823 nzcv = OR(OR(OR(n,z),c),v1); 1756 nzcv = OR(OR(OR(n,z),c),v1);
1824 v = R(VFP_FPSCR); 1757 v = R(VFP_FPSCR);
1825 tmp = OR(nzcv,AND(v,CONST32(0x0fffffff))); 1758 tmp = OR(nzcv,AND(v,CONST32(0x0fffffff)));
1826 LET(VFP_FPSCR,tmp); 1759 LET(VFP_FPSCR,tmp);
@@ -1841,8 +1774,6 @@ typedef struct _vcvtbds_inst {
1841#ifdef VFP_INTERPRETER_TRANS 1774#ifdef VFP_INTERPRETER_TRANS
1842ARM_INST_PTR INTERPRETER_TRANSLATE(vcvtbds)(unsigned int inst, int index) 1775ARM_INST_PTR INTERPRETER_TRANSLATE(vcvtbds)(unsigned int inst, int index)
1843{ 1776{
1844 VFP_DEBUG_TRANSLATE;
1845
1846 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vcvtbds_inst)); 1777 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vcvtbds_inst));
1847 vcvtbds_inst *inst_cream = (vcvtbds_inst *)inst_base->component; 1778 vcvtbds_inst *inst_cream = (vcvtbds_inst *)inst_base->component;
1848 1779
@@ -1863,8 +1794,6 @@ VCVTBDS_INST:
1863 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 1794 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
1864 CHECK_VFP_ENABLED; 1795 CHECK_VFP_ENABLED;
1865 1796
1866 DBG("VCVT(BDS) :\n");
1867
1868 vcvtbds_inst *inst_cream = (vcvtbds_inst *)inst_base->component; 1797 vcvtbds_inst *inst_cream = (vcvtbds_inst *)inst_base->component;
1869 1798
1870 int ret; 1799 int ret;
@@ -1897,7 +1826,7 @@ int DYNCOM_TAG(vcvtbds)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_
1897#endif 1826#endif
1898#ifdef VFP_DYNCOM_TRANS 1827#ifdef VFP_DYNCOM_TRANS
1899int DYNCOM_TRANS(vcvtbds)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){ 1828int DYNCOM_TRANS(vcvtbds)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
1900 DBG("\t\tin %s instruction is executed out.\n", __FUNCTION__); 1829 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is executed out.\n", __FUNCTION__);
1901 //arch_arm_undef(cpu, bb, instr); 1830 //arch_arm_undef(cpu, bb, instr);
1902 int dp_op = (BIT(8) == 1); 1831 int dp_op = (BIT(8) == 1);
1903 int d = dp_op ? BITS(12,15) << 1 | BIT(22) : BIT(22) << 4 | BITS(12,15); 1832 int d = dp_op ? BITS(12,15) << 1 | BIT(22) : BIT(22) << 4 | BITS(12,15);
@@ -1911,7 +1840,7 @@ int DYNCOM_TRANS(vcvtbds)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc)
1911 tmp = ZEXT64(IBITCAST32(FR32(2 * m))); 1840 tmp = ZEXT64(IBITCAST32(FR32(2 * m)));
1912 v1 = OR(v,tmp); 1841 v1 = OR(v,tmp);
1913 tmp = FPTRUNC(32,FPBITCAST64(v1)); 1842 tmp = FPTRUNC(32,FPBITCAST64(v1));
1914 LETFPS(d,tmp); 1843 LETFPS(d,tmp);
1915 }else { 1844 }else {
1916 v = FR32(m); 1845 v = FR32(m);
1917 tmp = FPEXT(64,v); 1846 tmp = FPEXT(64,v);
@@ -1937,7 +1866,7 @@ typedef struct _vcvtbff_inst {
1937#ifdef VFP_INTERPRETER_TRANS 1866#ifdef VFP_INTERPRETER_TRANS
1938ARM_INST_PTR INTERPRETER_TRANSLATE(vcvtbff)(unsigned int inst, int index) 1867ARM_INST_PTR INTERPRETER_TRANSLATE(vcvtbff)(unsigned int inst, int index)
1939{ 1868{
1940 VFP_DEBUG_TRANSLATE;VFP_DEBUG_UNTESTED(VCVTBFF); 1869 VFP_DEBUG_UNTESTED(VCVTBFF);
1941 1870
1942 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vcvtbff_inst)); 1871 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vcvtbff_inst));
1943 vcvtbff_inst *inst_cream = (vcvtbff_inst *)inst_base->component; 1872 vcvtbff_inst *inst_cream = (vcvtbff_inst *)inst_base->component;
@@ -1959,8 +1888,6 @@ VCVTBFF_INST:
1959 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 1888 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
1960 CHECK_VFP_ENABLED; 1889 CHECK_VFP_ENABLED;
1961 1890
1962 DBG("VCVT(BFF) :\n");
1963
1964 vcvtbff_inst *inst_cream = (vcvtbff_inst *)inst_base->component; 1891 vcvtbff_inst *inst_cream = (vcvtbff_inst *)inst_base->component;
1965 1892
1966 int ret; 1893 int ret;
@@ -1986,14 +1913,14 @@ DYNCOM_FILL_ACTION(vcvtbff),
1986int DYNCOM_TAG(vcvtbff)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc) 1913int DYNCOM_TAG(vcvtbff)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
1987{ 1914{
1988 int instr_size = INSTR_SIZE; 1915 int instr_size = INSTR_SIZE;
1989 DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__); 1916 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
1990 arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc); 1917 arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
1991 return instr_size; 1918 return instr_size;
1992} 1919}
1993#endif 1920#endif
1994#ifdef VFP_DYNCOM_TRANS 1921#ifdef VFP_DYNCOM_TRANS
1995int DYNCOM_TRANS(vcvtbff)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){ 1922int DYNCOM_TRANS(vcvtbff)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
1996 DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__); 1923 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
1997 arch_arm_undef(cpu, bb, instr); 1924 arch_arm_undef(cpu, bb, instr);
1998 return No_exp; 1925 return No_exp;
1999} 1926}
@@ -2011,8 +1938,6 @@ typedef struct _vcvtbfi_inst {
2011#ifdef VFP_INTERPRETER_TRANS 1938#ifdef VFP_INTERPRETER_TRANS
2012ARM_INST_PTR INTERPRETER_TRANSLATE(vcvtbfi)(unsigned int inst, int index) 1939ARM_INST_PTR INTERPRETER_TRANSLATE(vcvtbfi)(unsigned int inst, int index)
2013{ 1940{
2014 VFP_DEBUG_TRANSLATE;
2015
2016 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vcvtbfi_inst)); 1941 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vcvtbfi_inst));
2017 vcvtbfi_inst *inst_cream = (vcvtbfi_inst *)inst_base->component; 1942 vcvtbfi_inst *inst_cream = (vcvtbfi_inst *)inst_base->component;
2018 1943
@@ -2024,7 +1949,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(vcvtbfi)(unsigned int inst, int index)
2024 inst_cream->dp_operation = BIT(inst, 8); 1949 inst_cream->dp_operation = BIT(inst, 8);
2025 inst_cream->instr = inst; 1950 inst_cream->instr = inst;
2026 1951
2027
2028 return inst_base; 1952 return inst_base;
2029} 1953}
2030#endif 1954#endif
@@ -2034,8 +1958,6 @@ VCVTBFI_INST:
2034 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 1958 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
2035 CHECK_VFP_ENABLED; 1959 CHECK_VFP_ENABLED;
2036 1960
2037 DBG("VCVT(BFI) :\n");
2038
2039 vcvtbfi_inst *inst_cream = (vcvtbfi_inst *)inst_base->component; 1961 vcvtbfi_inst *inst_cream = (vcvtbfi_inst *)inst_base->component;
2040 1962
2041 int ret; 1963 int ret;
@@ -2061,8 +1983,7 @@ DYNCOM_FILL_ACTION(vcvtbfi),
2061int DYNCOM_TAG(vcvtbfi)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc) 1983int DYNCOM_TAG(vcvtbfi)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
2062{ 1984{
2063 int instr_size = INSTR_SIZE; 1985 int instr_size = INSTR_SIZE;
2064 //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__); 1986 LOG_TRACE(Core_ARM11, "\t\tin %s, instruction will be executed out of JIT.\n", __FUNCTION__);
2065 DBG("\t\tin %s, instruction will be executed out of JIT.\n", __FUNCTION__);
2066 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc); 1987 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
2067 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc); 1988 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
2068 return instr_size; 1989 return instr_size;
@@ -2070,17 +1991,17 @@ int DYNCOM_TAG(vcvtbfi)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_
2070#endif 1991#endif
2071#ifdef VFP_DYNCOM_TRANS 1992#ifdef VFP_DYNCOM_TRANS
2072int DYNCOM_TRANS(vcvtbfi)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){ 1993int DYNCOM_TRANS(vcvtbfi)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
2073 DBG("\t\tin %s, instruction will be executed out of JIT.\n", __FUNCTION__); 1994 LOG_TRACE(Core_ARM11, "\t\tin %s, instruction will be executed out of JIT.\n", __FUNCTION__);
2074 //arch_arm_undef(cpu, bb, instr); 1995 //arch_arm_undef(cpu, bb, instr);
2075 unsigned int opc2 = BITS(16,18); 1996 unsigned int opc2 = BITS(16,18);
2076 int to_integer = ((opc2 >> 2) == 1); 1997 int to_integer = ((opc2 >> 2) == 1);
2077 int dp_op = (BIT(8) == 1); 1998 int dp_op = (BIT(8) == 1);
2078 unsigned int op = BIT(7); 1999 unsigned int op = BIT(7);
2079 int m,d; 2000 int m,d;
2080 Value* v; 2001 Value* v;
2081 Value* hi; 2002 Value* hi;
2082 Value* lo; 2003 Value* lo;
2083 Value* v64; 2004 Value* v64;
2084 if(to_integer){ 2005 if(to_integer){
2085 d = BIT(22) | (BITS(12,15) << 1); 2006 d = BIT(22) | (BITS(12,15) << 1);
2086 if(dp_op) 2007 if(dp_op)
@@ -2092,15 +2013,15 @@ int DYNCOM_TRANS(vcvtbfi)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc)
2092 if(dp_op) 2013 if(dp_op)
2093 d = BITS(12,15) | BIT(22) << 4; 2014 d = BITS(12,15) | BIT(22) << 4;
2094 else 2015 else
2095 d = BIT(22) | BITS(12,15) << 1; 2016 d = BIT(22) | BITS(12,15) << 1;
2096 } 2017 }
2097 if(to_integer){ 2018 if(to_integer){
2098 if(dp_op){ 2019 if(dp_op){
2099 lo = FR32(m * 2); 2020 lo = FR32(m * 2);
2100 hi = FR32(m * 2 + 1); 2021 hi = FR32(m * 2 + 1);
2101 hi = ZEXT64(IBITCAST32(hi)); 2022 hi = ZEXT64(IBITCAST32(hi));
2102 lo = ZEXT64(IBITCAST32(lo)); 2023 lo = ZEXT64(IBITCAST32(lo));
2103 v64 = OR(SHL(hi,CONST64(32)),lo); 2024 v64 = OR(SHL(hi,CONST64(32)),lo);
2104 if(BIT(16)){ 2025 if(BIT(16)){
2105 v = FPTOSI(32,FPBITCAST64(v64)); 2026 v = FPTOSI(32,FPBITCAST64(v64));
2106 } 2027 }
@@ -2112,7 +2033,6 @@ int DYNCOM_TRANS(vcvtbfi)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc)
2112 }else { 2033 }else {
2113 v = FR32(m); 2034 v = FR32(m);
2114 if(BIT(16)){ 2035 if(BIT(16)){
2115
2116 v = FPTOSI(32,v); 2036 v = FPTOSI(32,v);
2117 } 2037 }
2118 else 2038 else
@@ -2120,10 +2040,10 @@ int DYNCOM_TRANS(vcvtbfi)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc)
2120 LETFPS(d,FPBITCAST32(v)); 2040 LETFPS(d,FPBITCAST32(v));
2121 } 2041 }
2122 }else { 2042 }else {
2123 if(dp_op){ 2043 if(dp_op){
2124 v = IBITCAST32(FR32(m)); 2044 v = IBITCAST32(FR32(m));
2125 if(BIT(7)) 2045 if(BIT(7))
2126 v64 = SITOFP(64,v); 2046 v64 = SITOFP(64,v);
2127 else 2047 else
2128 v64 = UITOFP(64,v); 2048 v64 = UITOFP(64,v);
2129 v = IBITCAST64(v64); 2049 v = IBITCAST64(v64);
@@ -2149,7 +2069,7 @@ int DYNCOM_TRANS(vcvtbfi)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc)
2149* @param cpu 2069* @param cpu
2150* @param instr 2070* @param instr
2151* 2071*
2152* @return 2072* @return
2153*/ 2073*/
2154int vcvtbfi_instr_impl(arm_core_t* cpu, uint32 instr){ 2074int vcvtbfi_instr_impl(arm_core_t* cpu, uint32 instr){
2155 int dp_operation = BIT(8); 2075 int dp_operation = BIT(8);
@@ -2183,8 +2103,6 @@ typedef struct _vmovbrs_inst {
2183#ifdef VFP_INTERPRETER_TRANS 2103#ifdef VFP_INTERPRETER_TRANS
2184ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbrs)(unsigned int inst, int index) 2104ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbrs)(unsigned int inst, int index)
2185{ 2105{
2186 VFP_DEBUG_TRANSLATE;
2187
2188 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmovbrs_inst)); 2106 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmovbrs_inst));
2189 vmovbrs_inst *inst_cream = (vmovbrs_inst *)inst_base->component; 2107 vmovbrs_inst *inst_cream = (vmovbrs_inst *)inst_base->component;
2190 2108
@@ -2224,26 +2142,22 @@ DYNCOM_FILL_ACTION(vmovbrs),
2224int DYNCOM_TAG(vmovbrs)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc) 2142int DYNCOM_TAG(vmovbrs)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
2225{ 2143{
2226 int instr_size = INSTR_SIZE; 2144 int instr_size = INSTR_SIZE;
2227 //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
2228 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc); 2145 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
2229 return instr_size; 2146 return instr_size;
2230} 2147}
2231#endif 2148#endif
2232#ifdef VFP_DYNCOM_TRANS 2149#ifdef VFP_DYNCOM_TRANS
2233int DYNCOM_TRANS(vmovbrs)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){ 2150int DYNCOM_TRANS(vmovbrs)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
2234 DBG("VMOV(BRS) :\n");
2235 int to_arm = BIT(20) == 1; 2151 int to_arm = BIT(20) == 1;
2236 int t = BITS(12, 15); 2152 int t = BITS(12, 15);
2237 int n = BIT(7) | BITS(16, 19)<<1; 2153 int n = BIT(7) | BITS(16, 19)<<1;
2238 2154
2239 if (to_arm) 2155 if (to_arm)
2240 { 2156 {
2241 DBG("\tr%d <= s%d\n", t, n);
2242 LET(t, IBITCAST32(FR32(n))); 2157 LET(t, IBITCAST32(FR32(n)));
2243 } 2158 }
2244 else 2159 else
2245 { 2160 {
2246 DBG("\ts%d <= r%d\n", n, t);
2247 LETFPS(n, FPBITCAST32(R(t))); 2161 LETFPS(n, FPBITCAST32(R(t)));
2248 } 2162 }
2249 return No_exp; 2163 return No_exp;
@@ -2263,8 +2177,6 @@ typedef struct _vmsr_inst {
2263#ifdef VFP_INTERPRETER_TRANS 2177#ifdef VFP_INTERPRETER_TRANS
2264ARM_INST_PTR INTERPRETER_TRANSLATE(vmsr)(unsigned int inst, int index) 2178ARM_INST_PTR INTERPRETER_TRANSLATE(vmsr)(unsigned int inst, int index)
2265{ 2179{
2266 VFP_DEBUG_TRANSLATE;
2267
2268 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmsr_inst)); 2180 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmsr_inst));
2269 vmsr_inst *inst_cream = (vmsr_inst *)inst_base->component; 2181 vmsr_inst *inst_cream = (vmsr_inst *)inst_base->component;
2270 2182
@@ -2306,7 +2218,6 @@ DYNCOM_FILL_ACTION(vmsr),
2306int DYNCOM_TAG(vmsr)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc) 2218int DYNCOM_TAG(vmsr)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
2307{ 2219{
2308 int instr_size = INSTR_SIZE; 2220 int instr_size = INSTR_SIZE;
2309 //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
2310 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc); 2221 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
2311 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc); 2222 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
2312 return instr_size; 2223 return instr_size;
@@ -2314,11 +2225,9 @@ int DYNCOM_TAG(vmsr)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *
2314#endif 2225#endif
2315#ifdef VFP_DYNCOM_TRANS 2226#ifdef VFP_DYNCOM_TRANS
2316int DYNCOM_TRANS(vmsr)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){ 2227int DYNCOM_TRANS(vmsr)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
2317 //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
2318 //arch_arm_undef(cpu, bb, instr); 2228 //arch_arm_undef(cpu, bb, instr);
2319 DBG("VMSR :");
2320 if(RD == 15) { 2229 if(RD == 15) {
2321 printf("in %s is not implementation.\n", __FUNCTION__); 2230 LOG_ERROR(Core_ARM11, "in %s is not implementation.\n", __FUNCTION__);
2322 exit(-1); 2231 exit(-1);
2323 } 2232 }
2324 2233
@@ -2328,7 +2237,6 @@ int DYNCOM_TRANS(vmsr)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
2328 if (reg == 1) 2237 if (reg == 1)
2329 { 2238 {
2330 LET(VFP_FPSCR, R(Rt)); 2239 LET(VFP_FPSCR, R(Rt));
2331 DBG("\tflags <= fpscr\n");
2332 } 2240 }
2333 else 2241 else
2334 { 2242 {
@@ -2336,10 +2244,8 @@ int DYNCOM_TRANS(vmsr)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
2336 { 2244 {
2337 case 8: 2245 case 8:
2338 LET(VFP_FPEXC, R(Rt)); 2246 LET(VFP_FPEXC, R(Rt));
2339 DBG("\tfpexc <= r%d \n", Rt);
2340 break; 2247 break;
2341 default: 2248 default:
2342 DBG("\tSUBARCHITECTURE DEFINED\n");
2343 break; 2249 break;
2344 } 2250 }
2345 } 2251 }
@@ -2362,8 +2268,6 @@ typedef struct _vmovbrc_inst {
2362#ifdef VFP_INTERPRETER_TRANS 2268#ifdef VFP_INTERPRETER_TRANS
2363ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbrc)(unsigned int inst, int index) 2269ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbrc)(unsigned int inst, int index)
2364{ 2270{
2365 VFP_DEBUG_TRANSLATE;
2366
2367 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmovbrc_inst)); 2271 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmovbrc_inst));
2368 vmovbrc_inst *inst_cream = (vmovbrc_inst *)inst_base->component; 2272 vmovbrc_inst *inst_cream = (vmovbrc_inst *)inst_base->component;
2369 2273
@@ -2405,14 +2309,14 @@ DYNCOM_FILL_ACTION(vmovbrc),
2405int DYNCOM_TAG(vmovbrc)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc) 2309int DYNCOM_TAG(vmovbrc)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
2406{ 2310{
2407 int instr_size = INSTR_SIZE; 2311 int instr_size = INSTR_SIZE;
2408 DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__); 2312 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
2409 arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc); 2313 arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
2410 return instr_size; 2314 return instr_size;
2411} 2315}
2412#endif 2316#endif
2413#ifdef VFP_DYNCOM_TRANS 2317#ifdef VFP_DYNCOM_TRANS
2414int DYNCOM_TRANS(vmovbrc)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){ 2318int DYNCOM_TRANS(vmovbrc)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
2415 DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__); 2319 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
2416 arch_arm_undef(cpu, bb, instr); 2320 arch_arm_undef(cpu, bb, instr);
2417 return No_exp; 2321 return No_exp;
2418} 2322}
@@ -2431,8 +2335,6 @@ typedef struct _vmrs_inst {
2431#ifdef VFP_INTERPRETER_TRANS 2335#ifdef VFP_INTERPRETER_TRANS
2432ARM_INST_PTR INTERPRETER_TRANSLATE(vmrs)(unsigned int inst, int index) 2336ARM_INST_PTR INTERPRETER_TRANSLATE(vmrs)(unsigned int inst, int index)
2433{ 2337{
2434 VFP_DEBUG_TRANSLATE;
2435
2436 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmrs_inst)); 2338 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmrs_inst));
2437 vmrs_inst *inst_cream = (vmrs_inst *)inst_base->component; 2339 vmrs_inst *inst_cream = (vmrs_inst *)inst_base->component;
2438 2340
@@ -2458,46 +2360,39 @@ VMRS_INST:
2458 2360
2459 vmrs_inst *inst_cream = (vmrs_inst *)inst_base->component; 2361 vmrs_inst *inst_cream = (vmrs_inst *)inst_base->component;
2460 2362
2461 DBG("VMRS :");
2462
2463 if (inst_cream->reg == 1) /* FPSCR */ 2363 if (inst_cream->reg == 1) /* FPSCR */
2464 { 2364 {
2465 if (inst_cream->Rt != 15) 2365 if (inst_cream->Rt != 15)
2466 { 2366 {
2467 cpu->Reg[inst_cream->Rt] = cpu->VFP[VFP_OFFSET(VFP_FPSCR)]; 2367 cpu->Reg[inst_cream->Rt] = cpu->VFP[VFP_OFFSET(VFP_FPSCR)];
2468 DBG("\tr%d <= fpscr[%08x]\n", inst_cream->Rt, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
2469 } 2368 }
2470 else 2369 else
2471 { 2370 {
2472 cpu->NFlag = (cpu->VFP[VFP_OFFSET(VFP_FPSCR)] >> 31) & 1; 2371 cpu->NFlag = (cpu->VFP[VFP_OFFSET(VFP_FPSCR)] >> 31) & 1;
2473 cpu->ZFlag = (cpu->VFP[VFP_OFFSET(VFP_FPSCR)] >> 30) & 1; 2372 cpu->ZFlag = (cpu->VFP[VFP_OFFSET(VFP_FPSCR)] >> 30) & 1;
2474 cpu->CFlag = (cpu->VFP[VFP_OFFSET(VFP_FPSCR)] >> 29) & 1; 2373 cpu->CFlag = (cpu->VFP[VFP_OFFSET(VFP_FPSCR)] >> 29) & 1;
2475 cpu->VFlag = (cpu->VFP[VFP_OFFSET(VFP_FPSCR)] >> 28) & 1; 2374 cpu->VFlag = (cpu->VFP[VFP_OFFSET(VFP_FPSCR)] >> 28) & 1;
2476 DBG("\tflags <= fpscr[%1xxxxxxxx]\n", cpu->VFP[VFP_OFFSET(VFP_FPSCR)]>>28);
2477 } 2375 }
2478 } 2376 }
2479 else 2377 else
2480 { 2378 {
2481 switch (inst_cream->reg) 2379 switch (inst_cream->reg)
2482 { 2380 {
2483 case 0: 2381 case 0:
2484 cpu->Reg[inst_cream->Rt] = cpu->VFP[VFP_OFFSET(VFP_FPSID)]; 2382 cpu->Reg[inst_cream->Rt] = cpu->VFP[VFP_OFFSET(VFP_FPSID)];
2485 DBG("\tr%d <= fpsid[%08x]\n", inst_cream->Rt, cpu->VFP[VFP_OFFSET(VFP_FPSID)]);
2486 break; 2383 break;
2487 case 6: 2384 case 6:
2488 /* MVFR1, VFPv3 only ? */ 2385 /* MVFR1, VFPv3 only ? */
2489 DBG("\tr%d <= MVFR1 unimplemented\n", inst_cream->Rt); 2386 LOG_TRACE(Core_ARM11, "\tr%d <= MVFR1 unimplemented\n", inst_cream->Rt);
2490 break; 2387 break;
2491 case 7: 2388 case 7:
2492 /* MVFR0, VFPv3 only? */ 2389 /* MVFR0, VFPv3 only? */
2493 DBG("\tr%d <= MVFR0 unimplemented\n", inst_cream->Rt); 2390 LOG_TRACE(Core_ARM11, "\tr%d <= MVFR0 unimplemented\n", inst_cream->Rt);
2494 break; 2391 break;
2495 case 8: 2392 case 8:
2496 cpu->Reg[inst_cream->Rt] = cpu->VFP[VFP_OFFSET(VFP_FPEXC)]; 2393 cpu->Reg[inst_cream->Rt] = cpu->VFP[VFP_OFFSET(VFP_FPEXC)];
2497 DBG("\tr%d <= fpexc[%08x]\n", inst_cream->Rt, cpu->VFP[VFP_OFFSET(VFP_FPEXC)]);
2498 break; 2394 break;
2499 default: 2395 default:
2500 DBG("\tSUBARCHITECTURE DEFINED\n");
2501 break; 2396 break;
2502 } 2397 }
2503 } 2398 }
@@ -2516,8 +2411,6 @@ DYNCOM_FILL_ACTION(vmrs),
2516int DYNCOM_TAG(vmrs)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc) 2411int DYNCOM_TAG(vmrs)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
2517{ 2412{
2518 int instr_size = INSTR_SIZE; 2413 int instr_size = INSTR_SIZE;
2519 //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
2520 DBG("\t\tin %s .\n", __FUNCTION__);
2521 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc); 2414 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
2522 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc); 2415 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
2523 return instr_size; 2416 return instr_size;
@@ -2525,25 +2418,21 @@ int DYNCOM_TAG(vmrs)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *
2525#endif 2418#endif
2526#ifdef VFP_DYNCOM_TRANS 2419#ifdef VFP_DYNCOM_TRANS
2527int DYNCOM_TRANS(vmrs)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){ 2420int DYNCOM_TRANS(vmrs)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
2528 //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
2529 //arch_arm_undef(cpu, bb, instr); 2421 //arch_arm_undef(cpu, bb, instr);
2530 2422
2531 Value *data = NULL; 2423 Value *data = NULL;
2532 int reg = BITS(16, 19);; 2424 int reg = BITS(16, 19);;
2533 int Rt = BITS(12, 15); 2425 int Rt = BITS(12, 15);
2534 DBG("VMRS : reg=%d, Rt=%d\n", reg, Rt);
2535 if (reg == 1) 2426 if (reg == 1)
2536 { 2427 {
2537 if (Rt != 15) 2428 if (Rt != 15)
2538 { 2429 {
2539 LET(Rt, R(VFP_FPSCR)); 2430 LET(Rt, R(VFP_FPSCR));
2540 DBG("\tr%d <= fpscr\n", Rt);
2541 } 2431 }
2542 else 2432 else
2543 { 2433 {
2544 //LET(Rt, R(VFP_FPSCR)); 2434 //LET(Rt, R(VFP_FPSCR));
2545 update_cond_from_fpscr(cpu, instr, bb, pc); 2435 update_cond_from_fpscr(cpu, instr, bb, pc);
2546 DBG("In %s, \tflags <= fpscr\n", __FUNCTION__);
2547 } 2436 }
2548 } 2437 }
2549 else 2438 else
@@ -2552,22 +2441,19 @@ int DYNCOM_TRANS(vmrs)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
2552 { 2441 {
2553 case 0: 2442 case 0:
2554 LET(Rt, R(VFP_FPSID)); 2443 LET(Rt, R(VFP_FPSID));
2555 DBG("\tr%d <= fpsid\n", Rt);
2556 break; 2444 break;
2557 case 6: 2445 case 6:
2558 /* MVFR1, VFPv3 only ? */ 2446 /* MVFR1, VFPv3 only ? */
2559 DBG("\tr%d <= MVFR1 unimplemented\n", Rt); 2447 LOG_TRACE(Core_ARM11, "\tr%d <= MVFR1 unimplemented\n", Rt);
2560 break; 2448 break;
2561 case 7: 2449 case 7:
2562 /* MVFR0, VFPv3 only? */ 2450 /* MVFR0, VFPv3 only? */
2563 DBG("\tr%d <= MVFR0 unimplemented\n", Rt); 2451 LOG_TRACE(Core_ARM11, "\tr%d <= MVFR0 unimplemented\n", Rt);
2564 break; 2452 break;
2565 case 8: 2453 case 8:
2566 LET(Rt, R(VFP_FPEXC)); 2454 LET(Rt, R(VFP_FPEXC));
2567 DBG("\tr%d <= fpexc\n", Rt);
2568 break; 2455 break;
2569 default: 2456 default:
2570 DBG("\tSUBARCHITECTURE DEFINED\n");
2571 break; 2457 break;
2572 } 2458 }
2573 } 2459 }
@@ -2591,8 +2477,6 @@ typedef struct _vmovbcr_inst {
2591#ifdef VFP_INTERPRETER_TRANS 2477#ifdef VFP_INTERPRETER_TRANS
2592ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbcr)(unsigned int inst, int index) 2478ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbcr)(unsigned int inst, int index)
2593{ 2479{
2594 VFP_DEBUG_TRANSLATE;
2595
2596 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmovbcr_inst)); 2480 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmovbcr_inst));
2597 vmovbcr_inst *inst_cream = (vmovbcr_inst *)inst_base->component; 2481 vmovbcr_inst *inst_cream = (vmovbcr_inst *)inst_base->component;
2598 2482
@@ -2634,14 +2518,14 @@ DYNCOM_FILL_ACTION(vmovbcr),
2634int DYNCOM_TAG(vmovbcr)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc) 2518int DYNCOM_TAG(vmovbcr)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
2635{ 2519{
2636 int instr_size = INSTR_SIZE; 2520 int instr_size = INSTR_SIZE;
2637 DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__); 2521 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
2638 arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc); 2522 arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
2639 return instr_size; 2523 return instr_size;
2640} 2524}
2641#endif 2525#endif
2642#ifdef VFP_DYNCOM_TRANS 2526#ifdef VFP_DYNCOM_TRANS
2643int DYNCOM_TRANS(vmovbcr)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){ 2527int DYNCOM_TRANS(vmovbcr)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
2644 DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__); 2528 LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
2645 arch_arm_undef(cpu, bb, instr); 2529 arch_arm_undef(cpu, bb, instr);
2646 return No_exp; 2530 return No_exp;
2647} 2531}
@@ -2667,8 +2551,6 @@ typedef struct _vmovbrrss_inst {
2667#ifdef VFP_INTERPRETER_TRANS 2551#ifdef VFP_INTERPRETER_TRANS
2668ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbrrss)(unsigned int inst, int index) 2552ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbrrss)(unsigned int inst, int index)
2669{ 2553{
2670 VFP_DEBUG_TRANSLATE;
2671
2672 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmovbrrss_inst)); 2554 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmovbrrss_inst));
2673 vmovbrrss_inst *inst_cream = (vmovbrrss_inst *)inst_base->component; 2555 vmovbrrss_inst *inst_cream = (vmovbrrss_inst *)inst_base->component;
2674 2556
@@ -2751,8 +2633,6 @@ typedef struct _vmovbrrd_inst {
2751#ifdef VFP_INTERPRETER_TRANS 2633#ifdef VFP_INTERPRETER_TRANS
2752ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbrrd)(unsigned int inst, int index) 2634ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbrrd)(unsigned int inst, int index)
2753{ 2635{
2754 VFP_DEBUG_TRANSLATE;
2755
2756 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmovbrrd_inst)); 2636 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmovbrrd_inst));
2757 vmovbrrd_inst *inst_cream = (vmovbrrd_inst *)inst_base->component; 2637 vmovbrrd_inst *inst_cream = (vmovbrrd_inst *)inst_base->component;
2758 2638
@@ -2777,7 +2657,7 @@ VMOVBRRD_INST:
2777 2657
2778 vmovbrrd_inst *inst_cream = (vmovbrrd_inst *)inst_base->component; 2658 vmovbrrd_inst *inst_cream = (vmovbrrd_inst *)inst_base->component;
2779 2659
2780 VMOVBRRD(cpu, inst_cream->to_arm, inst_cream->t, inst_cream->t2, inst_cream->m, 2660 VMOVBRRD(cpu, inst_cream->to_arm, inst_cream->t, inst_cream->t2, inst_cream->m,
2781 &(cpu->Reg[inst_cream->t]), &(cpu->Reg[inst_cream->t2])); 2661 &(cpu->Reg[inst_cream->t]), &(cpu->Reg[inst_cream->t2]));
2782 } 2662 }
2783 cpu->Reg[15] += GET_INST_SIZE(cpu); 2663 cpu->Reg[15] += GET_INST_SIZE(cpu);
@@ -2794,7 +2674,6 @@ DYNCOM_FILL_ACTION(vmovbrrd),
2794int DYNCOM_TAG(vmovbrrd)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc) 2674int DYNCOM_TAG(vmovbrrd)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
2795{ 2675{
2796 int instr_size = INSTR_SIZE; 2676 int instr_size = INSTR_SIZE;
2797 //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
2798 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc); 2677 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
2799 if(instr >> 28 != 0xe) 2678 if(instr >> 28 != 0xe)
2800 *tag |= TAG_CONDITIONAL; 2679 *tag |= TAG_CONDITIONAL;
@@ -2803,7 +2682,6 @@ int DYNCOM_TAG(vmovbrrd)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr
2803#endif 2682#endif
2804#ifdef VFP_DYNCOM_TRANS 2683#ifdef VFP_DYNCOM_TRANS
2805int DYNCOM_TRANS(vmovbrrd)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){ 2684int DYNCOM_TRANS(vmovbrrd)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
2806 //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
2807 //arch_arm_undef(cpu, bb, instr); 2685 //arch_arm_undef(cpu, bb, instr);
2808 int to_arm = BIT(20) == 1; 2686 int to_arm = BIT(20) == 1;
2809 int t = BITS(12, 15); 2687 int t = BITS(12, 15);
@@ -2841,8 +2719,6 @@ typedef struct _vstr_inst {
2841#ifdef VFP_INTERPRETER_TRANS 2719#ifdef VFP_INTERPRETER_TRANS
2842ARM_INST_PTR INTERPRETER_TRANSLATE(vstr)(unsigned int inst, int index) 2720ARM_INST_PTR INTERPRETER_TRANSLATE(vstr)(unsigned int inst, int index)
2843{ 2721{
2844 VFP_DEBUG_TRANSLATE;
2845
2846 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vstr_inst)); 2722 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vstr_inst));
2847 vstr_inst *inst_cream = (vstr_inst *)inst_base->component; 2723 vstr_inst *inst_cream = (vstr_inst *)inst_base->component;
2848 2724
@@ -2896,7 +2772,6 @@ int DYNCOM_TAG(vstr)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *
2896{ 2772{
2897 int instr_size = INSTR_SIZE; 2773 int instr_size = INSTR_SIZE;
2898 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc); 2774 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
2899 DBG("In %s, pc=0x%x, next_pc=0x%x\n", __FUNCTION__, pc, *next_pc);
2900 *tag |= TAG_NEW_BB; 2775 *tag |= TAG_NEW_BB;
2901 if(instr >> 28 != 0xe) 2776 if(instr >> 28 != 0xe)
2902 *tag |= TAG_CONDITIONAL; 2777 *tag |= TAG_CONDITIONAL;
@@ -2914,7 +2789,6 @@ int DYNCOM_TRANS(vstr)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
2914 2789
2915 Value* base = (n == 15) ? ADD(AND(R(n), CONST(0xFFFFFFFC)), CONST(8)): R(n); 2790 Value* base = (n == 15) ? ADD(AND(R(n), CONST(0xFFFFFFFC)), CONST(8)): R(n);
2916 Value* Addr = add ? ADD(base, CONST(imm32)) : SUB(base, CONST(imm32)); 2791 Value* Addr = add ? ADD(base, CONST(imm32)) : SUB(base, CONST(imm32));
2917 DBG("VSTR :\n");
2918 //if(single) 2792 //if(single)
2919 // bb = arch_check_mm(cpu, bb, Addr, 4, 0, cpu->dyncom_engine->bb_trap); 2793 // bb = arch_check_mm(cpu, bb, Addr, 4, 0, cpu->dyncom_engine->bb_trap);
2920 //else 2794 //else
@@ -2951,8 +2825,6 @@ typedef struct _vpush_inst {
2951#ifdef VFP_INTERPRETER_TRANS 2825#ifdef VFP_INTERPRETER_TRANS
2952ARM_INST_PTR INTERPRETER_TRANSLATE(vpush)(unsigned int inst, int index) 2826ARM_INST_PTR INTERPRETER_TRANSLATE(vpush)(unsigned int inst, int index)
2953{ 2827{
2954 VFP_DEBUG_TRANSLATE;
2955
2956 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vpush_inst)); 2828 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vpush_inst));
2957 vpush_inst *inst_cream = (vpush_inst *)inst_base->component; 2829 vpush_inst *inst_cream = (vpush_inst *)inst_base->component;
2958 2830
@@ -3010,7 +2882,6 @@ int DYNCOM_TAG(vpush)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t
3010{ 2882{
3011 int instr_size = INSTR_SIZE; 2883 int instr_size = INSTR_SIZE;
3012 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc); 2884 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
3013 DBG("In %s, pc=0x%x, next_pc=0x%x\n", __FUNCTION__, pc, *next_pc);
3014 *tag |= TAG_NEW_BB; 2885 *tag |= TAG_NEW_BB;
3015 if(instr >> 28 != 0xe) 2886 if(instr >> 28 != 0xe)
3016 *tag |= TAG_CONDITIONAL; 2887 *tag |= TAG_CONDITIONAL;
@@ -3025,7 +2896,6 @@ int DYNCOM_TRANS(vpush)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
3025 int imm32 = BITS(0, 7)<<2; 2896 int imm32 = BITS(0, 7)<<2;
3026 int regs = (single ? BITS(0, 7) : BITS(1, 7)); 2897 int regs = (single ? BITS(0, 7) : BITS(1, 7));
3027 2898
3028 DBG("\t\tin %s \n", __FUNCTION__);
3029 Value* Addr = SUB(R(13), CONST(imm32)); 2899 Value* Addr = SUB(R(13), CONST(imm32));
3030 //if(single) 2900 //if(single)
3031 // bb = arch_check_mm(cpu, bb, Addr, regs * 4, 0, cpu->dyncom_engine->bb_trap); 2901 // bb = arch_check_mm(cpu, bb, Addr, regs * 4, 0, cpu->dyncom_engine->bb_trap);
@@ -3079,8 +2949,6 @@ typedef struct _vstm_inst {
3079#ifdef VFP_INTERPRETER_TRANS 2949#ifdef VFP_INTERPRETER_TRANS
3080ARM_INST_PTR INTERPRETER_TRANSLATE(vstm)(unsigned int inst, int index) 2950ARM_INST_PTR INTERPRETER_TRANSLATE(vstm)(unsigned int inst, int index)
3081{ 2951{
3082 VFP_DEBUG_TRANSLATE;
3083
3084 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vstm_inst)); 2952 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vstm_inst));
3085 vstm_inst *inst_cream = (vstm_inst *)inst_base->component; 2953 vstm_inst *inst_cream = (vstm_inst *)inst_base->component;
3086 2954
@@ -3127,10 +2995,9 @@ VSTM_INST: /* encoding 1 */
3127 } 2995 }
3128 } 2996 }
3129 if (inst_cream->wback){ 2997 if (inst_cream->wback){
3130 cpu->Reg[inst_cream->n] = (inst_cream->add ? cpu->Reg[inst_cream->n] + inst_cream->imm32 : 2998 cpu->Reg[inst_cream->n] = (inst_cream->add ? cpu->Reg[inst_cream->n] + inst_cream->imm32 :
3131 cpu->Reg[inst_cream->n] - inst_cream->imm32); 2999 cpu->Reg[inst_cream->n] - inst_cream->imm32);
3132 } 3000 }
3133
3134 } 3001 }
3135 cpu->Reg[15] += 4; 3002 cpu->Reg[15] += 4;
3136 INC_PC(sizeof(vstm_inst)); 3003 INC_PC(sizeof(vstm_inst));
@@ -3147,10 +3014,8 @@ DYNCOM_FILL_ACTION(vstm),
3147int DYNCOM_TAG(vstm)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc) 3014int DYNCOM_TAG(vstm)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
3148{ 3015{
3149 int instr_size = INSTR_SIZE; 3016 int instr_size = INSTR_SIZE;
3150 //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
3151 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc); 3017 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
3152 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc); 3018 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
3153 DBG("In %s, pc=0x%x, next_pc=0x%x\n", __FUNCTION__, pc, *next_pc);
3154 *tag |= TAG_NEW_BB; 3019 *tag |= TAG_NEW_BB;
3155 if(instr >> 28 != 0xe) 3020 if(instr >> 28 != 0xe)
3156 *tag |= TAG_CONDITIONAL; 3021 *tag |= TAG_CONDITIONAL;
@@ -3170,30 +3035,26 @@ int DYNCOM_TRANS(vstm)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
3170 int regs = single ? BITS(0, 7) : BITS(1, 7); 3035 int regs = single ? BITS(0, 7) : BITS(1, 7);
3171 3036
3172 Value* Addr = SELECT(CONST1(add), R(n), SUB(R(n), CONST(imm32))); 3037 Value* Addr = SELECT(CONST1(add), R(n), SUB(R(n), CONST(imm32)));
3173 DBG("VSTM \n");
3174 //if(single) 3038 //if(single)
3175 // bb = arch_check_mm(cpu, bb, Addr, regs * 4, 0, cpu->dyncom_engine->bb_trap); 3039 // bb = arch_check_mm(cpu, bb, Addr, regs * 4, 0, cpu->dyncom_engine->bb_trap);
3176 //else 3040 //else
3177 // bb = arch_check_mm(cpu, bb, Addr, regs * 8, 0, cpu->dyncom_engine->bb_trap); 3041 // bb = arch_check_mm(cpu, bb, Addr, regs * 8, 0, cpu->dyncom_engine->bb_trap);
3178 3042
3179 int i; 3043 int i;
3180 Value* phys_addr; 3044 Value* phys_addr;
3181 for (i = 0; i < regs; i++) 3045 for (i = 0; i < regs; i++)
3182 { 3046 {
3183 if (single) 3047 if (single)
3184 { 3048 {
3185
3186 //Memory::Write32(addr, cpu->ExtReg[inst_cream->d+i]); 3049 //Memory::Write32(addr, cpu->ExtReg[inst_cream->d+i]);
3187 /* if R(i) is R15? */ 3050 /* if R(i) is R15? */
3188 //memory_write(cpu, bb, Addr, RSPR(d + i), 32); 3051 //memory_write(cpu, bb, Addr, RSPR(d + i), 32);
3189 memory_write(cpu, bb, Addr, IBITCAST32(FR32(d + i)),32); 3052 memory_write(cpu, bb, Addr, IBITCAST32(FR32(d + i)),32);
3190 bb = cpu->dyncom_engine->bb; 3053 bb = cpu->dyncom_engine->bb;
3191 //DBG("\taddr[%x] <= s%d=[%x]\n", addr, inst_cream->d+i, cpu->ExtReg[inst_cream->d+i]);
3192 Addr = ADD(Addr, CONST(4)); 3054 Addr = ADD(Addr, CONST(4));
3193 } 3055 }
3194 else 3056 else
3195 { 3057 {
3196
3197 //Memory::Write32(addr, cpu->ExtReg[(inst_cream->d+i)*2]); 3058 //Memory::Write32(addr, cpu->ExtReg[(inst_cream->d+i)*2]);
3198 //memory_write(cpu, bb, Addr, RSPR((d + i) * 2), 32); 3059 //memory_write(cpu, bb, Addr, RSPR((d + i) * 2), 32);
3199 memory_write(cpu, bb, Addr, IBITCAST32(FR32((d + i) * 2)),32); 3060 memory_write(cpu, bb, Addr, IBITCAST32(FR32((d + i) * 2)),32);
@@ -3203,16 +3064,14 @@ int DYNCOM_TRANS(vstm)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
3203 //memory_write(cpu, bb, ADD(Addr, CONST(4)), RSPR((d + i) * 2 + 1), 32); 3064 //memory_write(cpu, bb, ADD(Addr, CONST(4)), RSPR((d + i) * 2 + 1), 32);
3204 memory_write(cpu, bb, ADD(Addr, CONST(4)), IBITCAST32(FR32((d + i) * 2 + 1)), 32); 3065 memory_write(cpu, bb, ADD(Addr, CONST(4)), IBITCAST32(FR32((d + i) * 2 + 1)), 32);
3205 bb = cpu->dyncom_engine->bb; 3066 bb = cpu->dyncom_engine->bb;
3206 //DBG("\taddr[%x-%x] <= s[%d-%d]=[%x-%x]\n", addr+4, addr, (inst_cream->d+i)*2+1, (inst_cream->d+i)*2, cpu->ExtReg[(inst_cream->d+i)*2+1], cpu->ExtReg[(inst_cream->d+i)*2]);
3207 //addr += 8; 3067 //addr += 8;
3208 Addr = ADD(Addr, CONST(8)); 3068 Addr = ADD(Addr, CONST(8));
3209 } 3069 }
3210 } 3070 }
3211 if (wback){ 3071 if (wback){
3212 //cpu->Reg[n] = (add ? cpu->Reg[n] + imm32 : 3072 //cpu->Reg[n] = (add ? cpu->Reg[n] + imm32 :
3213 // cpu->Reg[n] - imm32); 3073 // cpu->Reg[n] - imm32);
3214 LET(n, SELECT(CONST1(add), ADD(R(n), CONST(imm32)), SUB(R(n), CONST(imm32)))); 3074 LET(n, SELECT(CONST1(add), ADD(R(n), CONST(imm32)), SUB(R(n), CONST(imm32))));
3215 DBG("\twback r%d, add=%d, imm32=%d\n", n, add, imm32);
3216 } 3075 }
3217 return No_exp; 3076 return No_exp;
3218} 3077}
@@ -3232,8 +3091,6 @@ typedef struct _vpop_inst {
3232#ifdef VFP_INTERPRETER_TRANS 3091#ifdef VFP_INTERPRETER_TRANS
3233ARM_INST_PTR INTERPRETER_TRANSLATE(vpop)(unsigned int inst, int index) 3092ARM_INST_PTR INTERPRETER_TRANSLATE(vpop)(unsigned int inst, int index)
3234{ 3093{
3235 VFP_DEBUG_TRANSLATE;
3236
3237 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vpop_inst)); 3094 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vpop_inst));
3238 vpop_inst *inst_cream = (vpop_inst *)inst_base->component; 3095 vpop_inst *inst_cream = (vpop_inst *)inst_base->component;
3239 3096
@@ -3296,11 +3153,9 @@ DYNCOM_FILL_ACTION(vpop),
3296int DYNCOM_TAG(vpop)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc) 3153int DYNCOM_TAG(vpop)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
3297{ 3154{
3298 int instr_size = INSTR_SIZE; 3155 int instr_size = INSTR_SIZE;
3299 //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
3300 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc); 3156 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
3301 /* Should check if PC is destination register */ 3157 /* Should check if PC is destination register */
3302 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc); 3158 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
3303 DBG("In %s, pc=0x%x, next_pc=0x%x\n", __FUNCTION__, pc, *next_pc);
3304 *tag |= TAG_NEW_BB; 3159 *tag |= TAG_NEW_BB;
3305 if(instr >> 28 != 0xe) 3160 if(instr >> 28 != 0xe)
3306 *tag |= TAG_CONDITIONAL; 3161 *tag |= TAG_CONDITIONAL;
@@ -3310,7 +3165,6 @@ int DYNCOM_TAG(vpop)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *
3310#endif 3165#endif
3311#ifdef VFP_DYNCOM_TRANS 3166#ifdef VFP_DYNCOM_TRANS
3312int DYNCOM_TRANS(vpop)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){ 3167int DYNCOM_TRANS(vpop)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
3313 DBG("\t\tin %s instruction .\n", __FUNCTION__);
3314 //arch_arm_undef(cpu, bb, instr); 3168 //arch_arm_undef(cpu, bb, instr);
3315 int single = BIT(8) == 0; 3169 int single = BIT(8) == 0;
3316 int d = (single ? BITS(12, 15)<<1|BIT(22) : BITS(12, 15)|(BIT(22)<<4)); 3170 int d = (single ? BITS(12, 15)<<1|BIT(22) : BITS(12, 15)|(BIT(22)<<4));
@@ -3320,15 +3174,13 @@ int DYNCOM_TRANS(vpop)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
3320 int i; 3174 int i;
3321 unsigned int value1, value2; 3175 unsigned int value1, value2;
3322 3176
3323 DBG("VPOP :\n");
3324
3325 Value* Addr = R(13); 3177 Value* Addr = R(13);
3326 Value* val; 3178 Value* val;
3327 //if(single) 3179 //if(single)
3328 // bb = arch_check_mm(cpu, bb, Addr, regs * 4, 1, cpu->dyncom_engine->bb_trap); 3180 // bb = arch_check_mm(cpu, bb, Addr, regs * 4, 1, cpu->dyncom_engine->bb_trap);
3329 //else 3181 //else
3330 // bb = arch_check_mm(cpu, bb, Addr, regs * 4, 1, cpu->dyncom_engine->bb_trap); 3182 // bb = arch_check_mm(cpu, bb, Addr, regs * 4, 1, cpu->dyncom_engine->bb_trap);
3331 //Value* phys_addr; 3183 //Value* phys_addr;
3332 for (i = 0; i < regs; i++) 3184 for (i = 0; i < regs; i++)
3333 { 3185 {
3334 if (single) 3186 if (single)
@@ -3374,8 +3226,6 @@ typedef struct _vldr_inst {
3374#ifdef VFP_INTERPRETER_TRANS 3226#ifdef VFP_INTERPRETER_TRANS
3375ARM_INST_PTR INTERPRETER_TRANSLATE(vldr)(unsigned int inst, int index) 3227ARM_INST_PTR INTERPRETER_TRANSLATE(vldr)(unsigned int inst, int index)
3376{ 3228{
3377 VFP_DEBUG_TRANSLATE;
3378
3379 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vldr_inst)); 3229 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vldr_inst));
3380 vldr_inst *inst_cream = (vldr_inst *)inst_base->component; 3230 vldr_inst *inst_cream = (vldr_inst *)inst_base->component;
3381 3231
@@ -3432,11 +3282,9 @@ DYNCOM_FILL_ACTION(vldr),
3432int DYNCOM_TAG(vldr)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc) 3282int DYNCOM_TAG(vldr)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
3433{ 3283{
3434 int instr_size = INSTR_SIZE; 3284 int instr_size = INSTR_SIZE;
3435 //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
3436 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc); 3285 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
3437 /* Should check if PC is destination register */ 3286 /* Should check if PC is destination register */
3438 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc); 3287 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
3439 DBG("In %s, pc=0x%x, next_pc=0x%x\n", __FUNCTION__, pc, *next_pc);
3440 *tag |= TAG_NEW_BB; 3288 *tag |= TAG_NEW_BB;
3441 if(instr >> 28 != 0xe) 3289 if(instr >> 28 != 0xe)
3442 *tag |= TAG_CONDITIONAL; 3290 *tag |= TAG_CONDITIONAL;
@@ -3454,7 +3302,6 @@ int DYNCOM_TRANS(vldr)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
3454 int imm32 = BITS(0, 7)<<2; 3302 int imm32 = BITS(0, 7)<<2;
3455 int regs = (single ? BITS(0, 7) : BITS(1, 7)); 3303 int regs = (single ? BITS(0, 7) : BITS(1, 7));
3456 Value* base = R(n); 3304 Value* base = R(n);
3457 DBG("\t\tin %s .\n", __FUNCTION__);
3458 if(n == 15){ 3305 if(n == 15){
3459 base = ADD(AND(base, CONST(0xFFFFFFFC)), CONST(8)); 3306 base = ADD(AND(base, CONST(0xFFFFFFFC)), CONST(8));
3460 } 3307 }
@@ -3506,8 +3353,6 @@ typedef struct _vldm_inst {
3506#ifdef VFP_INTERPRETER_TRANS 3353#ifdef VFP_INTERPRETER_TRANS
3507ARM_INST_PTR INTERPRETER_TRANSLATE(vldm)(unsigned int inst, int index) 3354ARM_INST_PTR INTERPRETER_TRANSLATE(vldm)(unsigned int inst, int index)
3508{ 3355{
3509 VFP_DEBUG_TRANSLATE;
3510
3511 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vldm_inst)); 3356 arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vldm_inst));
3512 vldm_inst *inst_cream = (vldm_inst *)inst_base->component; 3357 vldm_inst *inst_cream = (vldm_inst *)inst_base->component;
3513 3358
@@ -3554,11 +3399,9 @@ VLDM_INST:
3554 } 3399 }
3555 } 3400 }
3556 if (inst_cream->wback){ 3401 if (inst_cream->wback){
3557 cpu->Reg[inst_cream->n] = (inst_cream->add ? cpu->Reg[inst_cream->n] + inst_cream->imm32 : 3402 cpu->Reg[inst_cream->n] = (inst_cream->add ? cpu->Reg[inst_cream->n] + inst_cream->imm32 :
3558 cpu->Reg[inst_cream->n] - inst_cream->imm32); 3403 cpu->Reg[inst_cream->n] - inst_cream->imm32);
3559 DBG("\twback r%d[%x]\n", inst_cream->n, cpu->Reg[inst_cream->n]);
3560 } 3404 }
3561
3562 } 3405 }
3563 cpu->Reg[15] += GET_INST_SIZE(cpu); 3406 cpu->Reg[15] += GET_INST_SIZE(cpu);
3564 INC_PC(sizeof(vldm_inst)); 3407 INC_PC(sizeof(vldm_inst));
@@ -3574,10 +3417,8 @@ DYNCOM_FILL_ACTION(vldm),
3574int DYNCOM_TAG(vldm)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc) 3417int DYNCOM_TAG(vldm)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
3575{ 3418{
3576 int instr_size = INSTR_SIZE; 3419 int instr_size = INSTR_SIZE;
3577 //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
3578 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc); 3420 //arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
3579 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc); 3421 arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
3580 DBG("In %s, pc=0x%x, next_pc=0x%x\n", __FUNCTION__, pc, *next_pc);
3581 *tag |= TAG_NEW_BB; 3422 *tag |= TAG_NEW_BB;
3582 if(instr >> 28 != 0xe) 3423 if(instr >> 28 != 0xe)
3583 *tag |= TAG_CONDITIONAL; 3424 *tag |= TAG_CONDITIONAL;
@@ -3601,15 +3442,13 @@ int DYNCOM_TRANS(vldm)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
3601 //else 3442 //else
3602 // bb = arch_check_mm(cpu, bb, Addr, regs * 4, 1, cpu->dyncom_engine->bb_trap); 3443 // bb = arch_check_mm(cpu, bb, Addr, regs * 4, 1, cpu->dyncom_engine->bb_trap);
3603 3444
3604 DBG("VLDM \n"); 3445 int i;
3605 int i;
3606 //Value* phys_addr; 3446 //Value* phys_addr;
3607 Value* val; 3447 Value* val;
3608 for (i = 0; i < regs; i++) 3448 for (i = 0; i < regs; i++)
3609 { 3449 {
3610 if (single) 3450 if (single)
3611 { 3451 {
3612
3613 //Memory::Write32(addr, cpu->ExtReg[inst_cream->d+i]); 3452 //Memory::Write32(addr, cpu->ExtReg[inst_cream->d+i]);
3614 /* if R(i) is R15? */ 3453 /* if R(i) is R15? */
3615 memory_read(cpu, bb, Addr, 0, 32); 3454 memory_read(cpu, bb, Addr, 0, 32);
@@ -3617,7 +3456,6 @@ int DYNCOM_TRANS(vldm)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
3617 val = new LoadInst(cpu->dyncom_engine->read_value, "", false, bb); 3456 val = new LoadInst(cpu->dyncom_engine->read_value, "", false, bb);
3618 //LETS(d + i, val); 3457 //LETS(d + i, val);
3619 LETFPS(d + i, FPBITCAST32(val)); 3458 LETFPS(d + i, FPBITCAST32(val));
3620 //DBG("\taddr[%x] <= s%d=[%x]\n", addr, inst_cream->d+i, cpu->ExtReg[inst_cream->d+i]);
3621 Addr = ADD(Addr, CONST(4)); 3459 Addr = ADD(Addr, CONST(4));
3622 } 3460 }
3623 else 3461 else
@@ -3632,16 +3470,14 @@ int DYNCOM_TRANS(vldm)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
3632 LETFPS((d + i) * 2 + 1, FPBITCAST32(val)); 3470 LETFPS((d + i) * 2 + 1, FPBITCAST32(val));
3633 3471
3634 //Memory::Write(addr + 4, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2 + 1], 32); 3472 //Memory::Write(addr + 4, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2 + 1], 32);
3635 //DBG("\taddr[%x-%x] <= s[%d-%d]=[%x-%x]\n", addr+4, addr, (inst_cream->d+i)*2+1, (inst_cream->d+i)*2, cpu->ExtReg[(inst_cream->d+i)*2+1], cpu->ExtReg[(inst_cream->d+i)*2]);
3636 //addr += 8; 3473 //addr += 8;
3637 Addr = ADD(Addr, CONST(8)); 3474 Addr = ADD(Addr, CONST(8));
3638 } 3475 }
3639 } 3476 }
3640 if (wback){ 3477 if (wback){
3641 //cpu->Reg[n] = (add ? cpu->Reg[n] + imm32 : 3478 //cpu->Reg[n] = (add ? cpu->Reg[n] + imm32 :
3642 // cpu->Reg[n] - imm32); 3479 // cpu->Reg[n] - imm32);
3643 LET(n, SELECT(CONST1(add), ADD(R(n), CONST(imm32)), SUB(R(n), CONST(imm32)))); 3480 LET(n, SELECT(CONST1(add), ADD(R(n), CONST(imm32)), SUB(R(n), CONST(imm32))));
3644 DBG("\twback r%d, add=%d, imm32=%d\n", n, add, imm32);
3645 } 3481 }
3646 return No_exp; 3482 return No_exp;
3647} 3483}
HIC SVNT DRACONES