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| author | 2018-08-19 14:00:12 -0500 | |
|---|---|---|
| committer | 2018-08-19 14:00:12 -0500 | |
| commit | f7edbcd7a3e8f12b2db98220784c6f490e429a5f (patch) | |
| tree | 5b6582021e6dd47bb0f61fff89e40702538f0995 /src | |
| parent | Merge pull request #1109 from Subv/ldg_decode (diff) | |
| download | yuzu-f7edbcd7a3e8f12b2db98220784c6f490e429a5f.tar.gz yuzu-f7edbcd7a3e8f12b2db98220784c6f490e429a5f.tar.xz yuzu-f7edbcd7a3e8f12b2db98220784c6f490e429a5f.zip | |
Shaders/TEXS: Fixed the component mask in the TEXS instruction.
Previously we could end up with a TEXS that didn't write any outputs, this was wrong.
Diffstat (limited to 'src')
| -rw-r--r-- | src/video_core/engines/shader_bytecode.h | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h index 8ae0e6df2..096de9632 100644 --- a/src/video_core/engines/shader_bytecode.h +++ b/src/video_core/engines/shader_bytecode.h | |||
| @@ -12,6 +12,7 @@ | |||
| 12 | 12 | ||
| 13 | #include <boost/optional.hpp> | 13 | #include <boost/optional.hpp> |
| 14 | 14 | ||
| 15 | #include "common/assert.h" | ||
| 15 | #include "common/bit_field.h" | 16 | #include "common/bit_field.h" |
| 16 | #include "common/common_types.h" | 17 | #include "common/common_types.h" |
| 17 | 18 | ||
| @@ -446,16 +447,20 @@ union Instruction { | |||
| 446 | } | 447 | } |
| 447 | 448 | ||
| 448 | bool IsComponentEnabled(size_t component) const { | 449 | bool IsComponentEnabled(size_t component) const { |
| 449 | static constexpr std::array<std::array<u32, 8>, 4> mask_lut{ | 450 | static constexpr std::array<std::array<u32, 8>, 4> mask_lut{{ |
| 450 | {{}, | 451 | {}, |
| 451 | {0x1, 0x2, 0x4, 0x8, 0x3}, | 452 | {0x1, 0x2, 0x4, 0x8, 0x3, 0x9, 0xa, 0xc}, |
| 452 | {0x1, 0x2, 0x4, 0x8, 0x3, 0x9, 0xa, 0xc}, | 453 | {0x1, 0x2, 0x4, 0x8, 0x3, 0x9, 0xa, 0xc}, |
| 453 | {0x7, 0xb, 0xd, 0xe, 0xf}}}; | 454 | {0x7, 0xb, 0xd, 0xe, 0xf}, |
| 455 | }}; | ||
| 454 | 456 | ||
| 455 | size_t index{gpr0.Value() != Register::ZeroIndex ? 1U : 0U}; | 457 | size_t index{gpr0.Value() != Register::ZeroIndex ? 1U : 0U}; |
| 456 | index |= gpr28.Value() != Register::ZeroIndex ? 2 : 0; | 458 | index |= gpr28.Value() != Register::ZeroIndex ? 2 : 0; |
| 457 | 459 | ||
| 458 | return ((1ull << component) & mask_lut[index][component_mask_selector]) != 0; | 460 | u32 mask = mask_lut[index][component_mask_selector]; |
| 461 | // A mask of 0 means this instruction uses an unimplemented mask. | ||
| 462 | ASSERT(mask != 0); | ||
| 463 | return ((1ull << component) & mask) != 0; | ||
| 459 | } | 464 | } |
| 460 | } texs; | 465 | } texs; |
| 461 | 466 | ||