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| author | 2014-05-01 23:03:50 -0400 | |
|---|---|---|
| committer | 2014-05-01 23:03:50 -0400 | |
| commit | f7c6302009aa2453c37a6a7a3b1af4843f620078 (patch) | |
| tree | 59d429e36b9c3acd60a779ffbf063c59b2079e32 /src | |
| parent | fixed include in coprocessor.cpp (diff) | |
| download | yuzu-f7c6302009aa2453c37a6a7a3b1af4843f620078.tar.gz yuzu-f7c6302009aa2453c37a6a7a3b1af4843f620078.tar.xz yuzu-f7c6302009aa2453c37a6a7a3b1af4843f620078.zip | |
- added CallMCR function to coprocessor HLE module
- moved instruction decoding to coprocessor HLE module
Diffstat (limited to 'src')
| -rw-r--r-- | src/core/arm/interpreter/armsupp.cpp | 45 | ||||
| -rw-r--r-- | src/core/hle/coprocessor.cpp | 16 | ||||
| -rw-r--r-- | src/core/hle/coprocessor.h | 11 |
3 files changed, 43 insertions, 29 deletions
diff --git a/src/core/arm/interpreter/armsupp.cpp b/src/core/arm/interpreter/armsupp.cpp index d913c179c..e531dceda 100644 --- a/src/core/arm/interpreter/armsupp.cpp +++ b/src/core/arm/interpreter/armsupp.cpp | |||
| @@ -661,7 +661,8 @@ ARMul_STC (ARMul_State * state, ARMword instr, ARMword address) | |||
| 661 | void | 661 | void |
| 662 | ARMul_MCR (ARMul_State * state, ARMword instr, ARMword source) | 662 | ARMul_MCR (ARMul_State * state, ARMword instr, ARMword source) |
| 663 | { | 663 | { |
| 664 | unsigned cpab; | 664 | HLE::CallMCR(instr, source); |
| 665 | //unsigned cpab; | ||
| 665 | 666 | ||
| 666 | ////printf("SKYEYE ARMul_MCR, CPnum is %x, source %x\n",CPNum, source); | 667 | ////printf("SKYEYE ARMul_MCR, CPnum is %x, source %x\n",CPNum, source); |
| 667 | //if (!CP_ACCESS_ALLOWED (state, CPNum)) { | 668 | //if (!CP_ACCESS_ALLOWED (state, CPNum)) { |
| @@ -671,29 +672,29 @@ ARMul_MCR (ARMul_State * state, ARMword instr, ARMword source) | |||
| 671 | // return; | 672 | // return; |
| 672 | //} | 673 | //} |
| 673 | 674 | ||
| 674 | cpab = (state->MCR[CPNum]) (state, ARMul_FIRST, instr, source); | 675 | //cpab = (state->MCR[CPNum]) (state, ARMul_FIRST, instr, source); |
| 675 | 676 | ||
| 676 | while (cpab == ARMul_BUSY) { | 677 | //while (cpab == ARMul_BUSY) { |
| 677 | ARMul_Icycles (state, 1, 0); | 678 | // ARMul_Icycles (state, 1, 0); |
| 678 | 679 | ||
| 679 | if (IntPending (state)) { | 680 | // if (IntPending (state)) { |
| 680 | cpab = (state->MCR[CPNum]) (state, ARMul_INTERRUPT, | 681 | // cpab = (state->MCR[CPNum]) (state, ARMul_INTERRUPT, |
| 681 | instr, 0); | 682 | // instr, 0); |
| 682 | return; | 683 | // return; |
| 683 | } | 684 | // } |
| 684 | else | 685 | // else |
| 685 | cpab = (state->MCR[CPNum]) (state, ARMul_BUSY, instr, | 686 | // cpab = (state->MCR[CPNum]) (state, ARMul_BUSY, instr, |
| 686 | source); | 687 | // source); |
| 687 | } | 688 | //} |
| 688 | 689 | ||
| 689 | if (cpab == ARMul_CANT) { | 690 | //if (cpab == ARMul_CANT) { |
| 690 | printf ("SKYEYE ARMul_MCR, CANT, UndefinedInstr %x CPnum is %x, source %x\n", instr, CPNum, source); | 691 | // printf ("SKYEYE ARMul_MCR, CANT, UndefinedInstr %x CPnum is %x, source %x\n", instr, CPNum, source); |
| 691 | ARMul_Abort (state, ARMul_UndefinedInstrV); | 692 | // ARMul_Abort (state, ARMul_UndefinedInstrV); |
| 692 | } | 693 | //} |
| 693 | else { | 694 | //else { |
| 694 | BUSUSEDINCPCN; | 695 | // BUSUSEDINCPCN; |
| 695 | ARMul_Ccycles (state, 1, 0); | 696 | // ARMul_Ccycles (state, 1, 0); |
| 696 | } | 697 | //} |
| 697 | } | 698 | } |
| 698 | 699 | ||
| 699 | /* This function does the Busy-Waiting for an MCRR instruction. */ | 700 | /* This function does the Busy-Waiting for an MCRR instruction. */ |
| @@ -739,7 +740,7 @@ ARMul_MRC (ARMul_State * state, ARMword instr) | |||
| 739 | { | 740 | { |
| 740 | unsigned cpab; | 741 | unsigned cpab; |
| 741 | 742 | ||
| 742 | ARMword result = HLE::CallMRC((HLE::ARM11_MRC_OPERATION)BITS(20, 27)); | 743 | ARMword result = HLE::CallMRC(instr); |
| 743 | 744 | ||
| 744 | ////printf("SKYEYE ARMul_MRC, CPnum is %x, instr %x\n",CPNum, instr); | 745 | ////printf("SKYEYE ARMul_MRC, CPnum is %x, instr %x\n",CPNum, instr); |
| 745 | //if (!CP_ACCESS_ALLOWED (state, CPNum)) { | 746 | //if (!CP_ACCESS_ALLOWED (state, CPNum)) { |
diff --git a/src/core/hle/coprocessor.cpp b/src/core/hle/coprocessor.cpp index 5b412c586..df1362176 100644 --- a/src/core/hle/coprocessor.cpp +++ b/src/core/hle/coprocessor.cpp | |||
| @@ -44,8 +44,18 @@ Addr GetThreadCommandBuffer() { | |||
| 44 | return CMD_BUFFER_ADDR; | 44 | return CMD_BUFFER_ADDR; |
| 45 | } | 45 | } |
| 46 | 46 | ||
| 47 | /// Call an MRC operation in HLE | 47 | /// Call an MCR (move to coprocessor from ARM register) instruction in HLE |
| 48 | u32 CallMRC(ARM11_MRC_OPERATION operation) { | 48 | s32 CallMCR(u32 instruction, u32 value) { |
| 49 | CoprocessorOperation operation = (CoprocessorOperation)((instruction >> 20) & 0xFF); | ||
| 50 | ERROR_LOG(OSHLE, "unimplemented MCR instruction=0x%08X, operation=%02X, value=%08X", | ||
| 51 | instruction, operation, value); | ||
| 52 | return -1; | ||
| 53 | } | ||
| 54 | |||
| 55 | /// Call an MRC (move to ARM register from coprocessor) instruction in HLE | ||
| 56 | s32 CallMRC(u32 instruction) { | ||
| 57 | CoprocessorOperation operation = (CoprocessorOperation)((instruction >> 20) & 0xFF); | ||
| 58 | |||
| 49 | switch (operation) { | 59 | switch (operation) { |
| 50 | 60 | ||
| 51 | case DATA_SYNCHRONIZATION_BARRIER: | 61 | case DATA_SYNCHRONIZATION_BARRIER: |
| @@ -55,7 +65,7 @@ u32 CallMRC(ARM11_MRC_OPERATION operation) { | |||
| 55 | return GetThreadCommandBuffer(); | 65 | return GetThreadCommandBuffer(); |
| 56 | 66 | ||
| 57 | default: | 67 | default: |
| 58 | ERROR_LOG(OSHLE, "unimplemented MRC operation 0x%02X", operation); | 68 | ERROR_LOG(OSHLE, "unimplemented MRC instruction 0x%08X", instruction); |
| 59 | break; | 69 | break; |
| 60 | } | 70 | } |
| 61 | return -1; | 71 | return -1; |
diff --git a/src/core/hle/coprocessor.h b/src/core/hle/coprocessor.h index d6b9f162f..03822af13 100644 --- a/src/core/hle/coprocessor.h +++ b/src/core/hle/coprocessor.h | |||
| @@ -8,13 +8,16 @@ | |||
| 8 | 8 | ||
| 9 | namespace HLE { | 9 | namespace HLE { |
| 10 | 10 | ||
| 11 | /// MRC operations (ARM register from coprocessor), decoded as instr[20:27] | 11 | /// Coprocessor operations |
| 12 | enum ARM11_MRC_OPERATION { | 12 | enum CoprocessorOperation { |
| 13 | DATA_SYNCHRONIZATION_BARRIER = 0xE0, | 13 | DATA_SYNCHRONIZATION_BARRIER = 0xE0, |
| 14 | CALL_GET_THREAD_COMMAND_BUFFER = 0xE1, | 14 | CALL_GET_THREAD_COMMAND_BUFFER = 0xE1, |
| 15 | }; | 15 | }; |
| 16 | 16 | ||
| 17 | /// Call an MRC operation in HLE | 17 | /// Call an MCR (move to coprocessor from ARM register) instruction in HLE |
| 18 | u32 CallMRC(ARM11_MRC_OPERATION operation); | 18 | s32 CallMCR(u32 instruction, u32 value); |
| 19 | |||
| 20 | /// Call an MRC (move to ARM register from coprocessor) instruction in HLE | ||
| 21 | s32 CallMRC(u32 instruction); | ||
| 19 | 22 | ||
| 20 | } // namespace | 23 | } // namespace |