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| author | 2019-02-03 00:35:20 -0300 | |
|---|---|---|
| committer | 2019-02-03 00:35:34 -0300 | |
| commit | f61c1ed2466d209b5b1ff09c52c664fe1a8e5a60 (patch) | |
| tree | 707d21fd84f136fdf95797f1793fb1494331a0f1 /src | |
| parent | shader_bytecode: Rename BytesN enums to BitsN (diff) | |
| download | yuzu-f61c1ed2466d209b5b1ff09c52c664fe1a8e5a60.tar.gz yuzu-f61c1ed2466d209b5b1ff09c52c664fe1a8e5a60.tar.xz yuzu-f61c1ed2466d209b5b1ff09c52c664fe1a8e5a60.zip | |
shader_ir/memory: Add LD_L 128 bits loads
Diffstat (limited to 'src')
| -rw-r--r-- | src/video_core/shader/decode/memory.cpp | 26 |
1 files changed, 19 insertions, 7 deletions
diff --git a/src/video_core/shader/decode/memory.cpp b/src/video_core/shader/decode/memory.cpp index 2321a37a2..6eb36b1e7 100644 --- a/src/video_core/shader/decode/memory.cpp +++ b/src/video_core/shader/decode/memory.cpp | |||
| @@ -116,13 +116,25 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, const BasicBlock& code, u32 pc) { | |||
| 116 | 116 | ||
| 117 | switch (instr.ldst_sl.type.Value()) { | 117 | switch (instr.ldst_sl.type.Value()) { |
| 118 | case Tegra::Shader::StoreType::Bits32: | 118 | case Tegra::Shader::StoreType::Bits32: |
| 119 | SetRegister(bb, instr.gpr0, GetLmem(0)); | 119 | case Tegra::Shader::StoreType::Bits64: |
| 120 | break; | 120 | case Tegra::Shader::StoreType::Bits128: { |
| 121 | case Tegra::Shader::StoreType::Bits64: { | 121 | const u32 count = [&]() { |
| 122 | SetTemporal(bb, 0, GetLmem(0)); | 122 | switch (instr.ldst_sl.type.Value()) { |
| 123 | SetTemporal(bb, 1, GetLmem(4)); | 123 | case Tegra::Shader::StoreType::Bits32: |
| 124 | SetRegister(bb, instr.gpr0, GetTemporal(0)); | 124 | return 1; |
| 125 | SetRegister(bb, instr.gpr0.Value() + 1, GetTemporal(1)); | 125 | case Tegra::Shader::StoreType::Bits64: |
| 126 | return 2; | ||
| 127 | case Tegra::Shader::StoreType::Bits128: | ||
| 128 | return 4; | ||
| 129 | default: | ||
| 130 | UNREACHABLE(); | ||
| 131 | return 0; | ||
| 132 | } | ||
| 133 | }(); | ||
| 134 | for (u32 i = 0; i < count; ++i) | ||
| 135 | SetTemporal(bb, i, GetLmem(i * 4)); | ||
| 136 | for (u32 i = 0; i < count; ++i) | ||
| 137 | SetRegister(bb, instr.gpr0.Value() + i, GetTemporal(i)); | ||
| 126 | break; | 138 | break; |
| 127 | } | 139 | } |
| 128 | default: | 140 | default: |