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| author | 2019-04-23 11:21:00 -0400 | |
|---|---|---|
| committer | 2019-04-23 11:21:00 -0400 | |
| commit | f1e5314f1a57b09bd45e0db3ca91449e761c431a (patch) | |
| tree | d3b5d08f507572018a081a33607d0e70ef26f4f4 /src | |
| parent | Add Documentation Headers to all the GPU Engines (diff) | |
| download | yuzu-f1e5314f1a57b09bd45e0db3ca91449e761c431a.tar.gz yuzu-f1e5314f1a57b09bd45e0db3ca91449e761c431a.tar.xz yuzu-f1e5314f1a57b09bd45e0db3ca91449e761c431a.zip | |
Add Swizzle Parameters to the DMA engine
Diffstat (limited to 'src')
| -rw-r--r-- | src/video_core/engines/engine_upload.cpp | 2 | ||||
| -rw-r--r-- | src/video_core/engines/maxwell_dma.h | 27 |
2 files changed, 27 insertions, 2 deletions
diff --git a/src/video_core/engines/engine_upload.cpp b/src/video_core/engines/engine_upload.cpp index 663d5517a..867457f25 100644 --- a/src/video_core/engines/engine_upload.cpp +++ b/src/video_core/engines/engine_upload.cpp | |||
| @@ -25,7 +25,7 @@ void State::ProcessData(const u32 data, const bool is_last_call) { | |||
| 25 | write_offset += sub_copy_size; | 25 | write_offset += sub_copy_size; |
| 26 | if (is_last_call) { | 26 | if (is_last_call) { |
| 27 | const GPUVAddr address{regs.dest.Address()}; | 27 | const GPUVAddr address{regs.dest.Address()}; |
| 28 | if (linear) { | 28 | if (is_linear) { |
| 29 | memory_manager.WriteBlock(address, inner_buffer.data(), copy_size); | 29 | memory_manager.WriteBlock(address, inner_buffer.data(), copy_size); |
| 30 | } else { | 30 | } else { |
| 31 | UNIMPLEMENTED_IF(regs.dest.z != 0); | 31 | UNIMPLEMENTED_IF(regs.dest.z != 0); |
diff --git a/src/video_core/engines/maxwell_dma.h b/src/video_core/engines/maxwell_dma.h index 35b25e6b9..0b2e26199 100644 --- a/src/video_core/engines/maxwell_dma.h +++ b/src/video_core/engines/maxwell_dma.h | |||
| @@ -68,6 +68,16 @@ public: | |||
| 68 | 68 | ||
| 69 | static_assert(sizeof(Parameters) == 24, "Parameters has wrong size"); | 69 | static_assert(sizeof(Parameters) == 24, "Parameters has wrong size"); |
| 70 | 70 | ||
| 71 | enum class ComponentMode : u32 { | ||
| 72 | SRC0 = 0, | ||
| 73 | SRC1 = 1, | ||
| 74 | SRC2 = 2, | ||
| 75 | SRC3 = 3, | ||
| 76 | CONST0 = 4, | ||
| 77 | CONST1 = 5, | ||
| 78 | ZERO = 6, | ||
| 79 | }; | ||
| 80 | |||
| 71 | enum class CopyMode : u32 { | 81 | enum class CopyMode : u32 { |
| 72 | None = 0, | 82 | None = 0, |
| 73 | Unk1 = 1, | 83 | Unk1 = 1, |
| @@ -133,7 +143,19 @@ public: | |||
| 133 | u32 x_count; | 143 | u32 x_count; |
| 134 | u32 y_count; | 144 | u32 y_count; |
| 135 | 145 | ||
| 136 | INSERT_PADDING_WORDS(0xBB); | 146 | INSERT_PADDING_WORDS(0xB8); |
| 147 | |||
| 148 | u32 const0; | ||
| 149 | u32 const1; | ||
| 150 | union { | ||
| 151 | BitField<0, 4, ComponentMode> component0; | ||
| 152 | BitField<4, 4, ComponentMode> component1; | ||
| 153 | BitField<8, 4, ComponentMode> component2; | ||
| 154 | BitField<12, 4, ComponentMode> component3; | ||
| 155 | BitField<16, 2, u32> component_size; | ||
| 156 | BitField<20, 3, u32> src_num_components; | ||
| 157 | BitField<24, 3, u32> dst_num_components; | ||
| 158 | } swizzle_config; | ||
| 137 | 159 | ||
| 138 | Parameters dst_params; | 160 | Parameters dst_params; |
| 139 | 161 | ||
| @@ -170,6 +192,9 @@ ASSERT_REG_POSITION(src_pitch, 0x104); | |||
| 170 | ASSERT_REG_POSITION(dst_pitch, 0x105); | 192 | ASSERT_REG_POSITION(dst_pitch, 0x105); |
| 171 | ASSERT_REG_POSITION(x_count, 0x106); | 193 | ASSERT_REG_POSITION(x_count, 0x106); |
| 172 | ASSERT_REG_POSITION(y_count, 0x107); | 194 | ASSERT_REG_POSITION(y_count, 0x107); |
| 195 | ASSERT_REG_POSITION(const0, 0x1C0); | ||
| 196 | ASSERT_REG_POSITION(const1, 0x1C1); | ||
| 197 | ASSERT_REG_POSITION(swizzle_config, 0x1C2); | ||
| 173 | ASSERT_REG_POSITION(dst_params, 0x1C3); | 198 | ASSERT_REG_POSITION(dst_params, 0x1C3); |
| 174 | ASSERT_REG_POSITION(src_params, 0x1CA); | 199 | ASSERT_REG_POSITION(src_params, 0x1CA); |
| 175 | 200 | ||