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| author | 2014-06-01 00:22:40 +0200 | |
|---|---|---|
| committer | 2014-07-23 00:33:08 +0200 | |
| commit | ec9511e1db1f7ff0c2a8f86916937ea5736cdcf6 (patch) | |
| tree | 80ee4beb7fc5a569a40b3e8644a5c51f006b5938 /src | |
| parent | GSP: Implement ReadHWRegs and WriteHWRegs properly. (diff) | |
| download | yuzu-ec9511e1db1f7ff0c2a8f86916937ea5736cdcf6.tar.gz yuzu-ec9511e1db1f7ff0c2a8f86916937ea5736cdcf6.tar.xz yuzu-ec9511e1db1f7ff0c2a8f86916937ea5736cdcf6.zip | |
GSP: HLE GXCommandId::SET_DISPLAY_TRANSFER and GXCommandId::SET_TEXTURE_COPY.
Diffstat (limited to 'src')
| -rw-r--r-- | src/core/hle/service/gsp.cpp | 11 | ||||
| -rw-r--r-- | src/core/hw/gpu.h | 8 |
2 files changed, 17 insertions, 2 deletions
diff --git a/src/core/hle/service/gsp.cpp b/src/core/hle/service/gsp.cpp index cc111b0bb..fea521891 100644 --- a/src/core/hle/service/gsp.cpp +++ b/src/core/hle/service/gsp.cpp | |||
| @@ -176,10 +176,17 @@ void TriggerCmdReqQueue(Service::Interface* self) { | |||
| 176 | case GXCommandId::SET_MEMORY_FILL: | 176 | case GXCommandId::SET_MEMORY_FILL: |
| 177 | break; | 177 | break; |
| 178 | 178 | ||
| 179 | // TODO: Check if texture copies are implemented correctly.. | ||
| 179 | case GXCommandId::SET_DISPLAY_TRANSFER: | 180 | case GXCommandId::SET_DISPLAY_TRANSFER: |
| 180 | break; | ||
| 181 | |||
| 182 | case GXCommandId::SET_TEXTURE_COPY: | 181 | case GXCommandId::SET_TEXTURE_COPY: |
| 182 | GPU::Write<u32>(GPU::Registers::DisplayInputBufferAddr, cmd_buff[1] >> 3); | ||
| 183 | GPU::Write<u32>(GPU::Registers::DisplayOutputBufferAddr, cmd_buff[2] >> 3); | ||
| 184 | GPU::Write<u32>(GPU::Registers::DisplayInputBufferSize, cmd_buff[3]); | ||
| 185 | GPU::Write<u32>(GPU::Registers::DisplayOutputBufferSize, cmd_buff[4]); | ||
| 186 | GPU::Write<u32>(GPU::Registers::DisplayTransferFlags, cmd_buff[5]); | ||
| 187 | |||
| 188 | // TODO: GPU::Registers::DisplayTriggerTransfer should be ORed with 1 for texture copies? | ||
| 189 | GPU::Write<u32>(GPU::Registers::DisplayTriggerTransfer, 1); | ||
| 183 | break; | 190 | break; |
| 184 | 191 | ||
| 185 | case GXCommandId::SET_COMMAND_LIST_FIRST: | 192 | case GXCommandId::SET_COMMAND_LIST_FIRST: |
diff --git a/src/core/hw/gpu.h b/src/core/hw/gpu.h index 0c7dffec3..58058d732 100644 --- a/src/core/hw/gpu.h +++ b/src/core/hw/gpu.h | |||
| @@ -22,6 +22,14 @@ struct Registers { | |||
| 22 | FramebufferSubRight1 = 0x1EF00594, // Sub LCD, unused first framebuffer | 22 | FramebufferSubRight1 = 0x1EF00594, // Sub LCD, unused first framebuffer |
| 23 | FramebufferSubRight2 = 0x1EF00598, // Sub LCD, unused second framebuffer | 23 | FramebufferSubRight2 = 0x1EF00598, // Sub LCD, unused second framebuffer |
| 24 | 24 | ||
| 25 | DisplayInputBufferAddr = 0x1EF00C00, | ||
| 26 | DisplayOutputBufferAddr = 0x1EF00C04, | ||
| 27 | DisplayOutputBufferSize = 0x1EF00C08, | ||
| 28 | DisplayInputBufferSize = 0x1EF00C0C, | ||
| 29 | DisplayTransferFlags = 0x1EF00C10, | ||
| 30 | // Unknown?? | ||
| 31 | DisplayTriggerTransfer = 0x1EF00C18, | ||
| 32 | |||
| 25 | CommandListSize = 0x1EF018E0, | 33 | CommandListSize = 0x1EF018E0, |
| 26 | CommandListAddress = 0x1EF018E8, | 34 | CommandListAddress = 0x1EF018E8, |
| 27 | ProcessCommandList = 0x1EF018F0, | 35 | ProcessCommandList = 0x1EF018F0, |