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authorGravatar Yuri Kunde Schlesner2015-07-29 09:59:37 -0700
committerGravatar Yuri Kunde Schlesner2015-07-29 09:59:37 -0700
commitea1b04f5da2da0de2e6a11369dae256a2d4a246b (patch)
tree30542adf01ffb03b9064faa5b9af6ca9a7f8d36b /src
parentMerge pull request #1012 from lioncash/prototype (diff)
parentdyncom: Remove an unused variable (diff)
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Merge pull request #1013 from lioncash/unused
dyncom: Remove an unused variable
Diffstat (limited to 'src')
-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index 0c20c2bc3..bb0cbb4dc 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -3886,7 +3886,6 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
3886#endif 3886#endif
3887 arm_inst* inst_base; 3887 arm_inst* inst_base;
3888 unsigned int addr; 3888 unsigned int addr;
3889 unsigned int phys_addr;
3890 unsigned int num_instrs = 0; 3889 unsigned int num_instrs = 0;
3891 3890
3892 int ptr; 3891 int ptr;
@@ -3905,8 +3904,6 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
3905 else 3904 else
3906 cpu->Reg[15] &= 0xfffffffc; 3905 cpu->Reg[15] &= 0xfffffffc;
3907 3906
3908 phys_addr = cpu->Reg[15];
3909
3910 // Find the cached instruction cream, otherwise translate it... 3907 // Find the cached instruction cream, otherwise translate it...
3911 auto itr = cpu->instruction_cache.find(cpu->Reg[15]); 3908 auto itr = cpu->instruction_cache.find(cpu->Reg[15]);
3912 if (itr != cpu->instruction_cache.end()) { 3909 if (itr != cpu->instruction_cache.end()) {