arm: added option to prepare CPU core (while mid-instruction) for thread reschedule

3 files changed, 11 insertions, 0 deletions

diff --git a/src/core/arm/arm_interface.h b/src/core/arm/arm_interface.h
index b73786ccd..316b50fbb 100644
--- a/src/core/arm/arm_interface.h
+++ b/src/core/arm/arm_interface.h
@@ -89,6 +89,9 @@ public:
      */
     virtual void LoadContext(const ThreadContext& ctx) = 0;
 
+    /// Prepare core for thread reschedule (if needed to correctly handle state)
+    virtual void PrepareReschedule() = 0;
+
     /// Getter for num_instructions
     u64 GetNumInstructions() {
         return num_instructions;
diff --git a/src/core/arm/interpreter/arm_interpreter.cpp b/src/core/arm/interpreter/arm_interpreter.cpp
index 17f787b86..2aa100e86 100644
--- a/src/core/arm/interpreter/arm_interpreter.cpp
+++ b/src/core/arm/interpreter/arm_interpreter.cpp
@@ -140,3 +140,8 @@ void ARM_Interpreter::LoadContext(const ThreadContext& ctx) {
     state->Reg[15] = ctx.pc;
     state->NextInstr = RESUME;
 }
+
+/// Prepare core for thread reschedule (if needed to correctly handle state)
+void ARM_Interpreter::PrepareReschedule() {
+    state->NumInstrsToExecute = 0;
+}
diff --git a/src/core/arm/interpreter/arm_interpreter.h b/src/core/arm/interpreter/arm_interpreter.h
index 6a531e497..1e82883a2 100644
--- a/src/core/arm/interpreter/arm_interpreter.h
+++ b/src/core/arm/interpreter/arm_interpreter.h
@@ -72,6 +72,9 @@ public:
      */
     void LoadContext(const ThreadContext& ctx);
 
+    /// Prepare core for thread reschedule (if needed to correctly handle state)
+    void PrepareReschedule();
+
 protected:
 
     /**