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| author | 2014-12-17 14:54:24 -0500 | |
|---|---|---|
| committer | 2014-12-17 14:54:24 -0500 | |
| commit | e6f440ea7f4d5f8c075a5735747ef8facbb4699a (patch) | |
| tree | 5ceb3cb8409e6ca985134df9d8a95a6830c006e8 /src | |
| parent | Merge pull request #287 from lioncash/qaddsub16 (diff) | |
| parent | armemu: Fix SADD16 (diff) | |
| download | yuzu-e6f440ea7f4d5f8c075a5735747ef8facbb4699a.tar.gz yuzu-e6f440ea7f4d5f8c075a5735747ef8facbb4699a.tar.xz yuzu-e6f440ea7f4d5f8c075a5735747ef8facbb4699a.zip | |
Merge pull request #293 from lioncash/sops
armemu: Fix SADD16
Diffstat (limited to 'src')
| -rw-r--r-- | src/core/arm/interpreter/armemu.cpp | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp index 45714761a..1a589e39c 100644 --- a/src/core/arm/interpreter/armemu.cpp +++ b/src/core/arm/interpreter/armemu.cpp | |||
| @@ -5811,14 +5811,15 @@ L_stm_s_takeabort: | |||
| 5811 | state->Reg[tar] = ((a1 - a2) & 0xFFFF) | (((b1 - b2) & 0xFFFF) << 0x10); | 5811 | state->Reg[tar] = ((a1 - a2) & 0xFFFF) | (((b1 - b2) & 0xFFFF) << 0x10); |
| 5812 | return 1; | 5812 | return 1; |
| 5813 | } else if ((instr & 0xFF0) == 0xf10) { //sadd16 | 5813 | } else if ((instr & 0xFF0) == 0xf10) { //sadd16 |
| 5814 | u8 tar = BITS(12, 15); | 5814 | const u8 rd_idx = BITS(12, 15); |
| 5815 | u8 src1 = BITS(16, 19); | 5815 | const u8 rm_idx = BITS(0, 3); |
| 5816 | u8 src2 = BITS(0, 3); | 5816 | const u8 rn_idx = BITS(16, 19); |
| 5817 | s16 a1 = (state->Reg[src1] & 0xFFFF); | 5817 | const s16 rm_lo = (state->Reg[rm_idx] & 0xFFFF); |
| 5818 | s16 a2 = ((state->Reg[src1] >> 0x10) & 0xFFFF); | 5818 | const s16 rm_hi = ((state->Reg[rm_idx] >> 16) & 0xFFFF); |
| 5819 | s16 b1 = (state->Reg[src2] & 0xFFFF); | 5819 | const s16 rn_lo = (state->Reg[rn_idx] & 0xFFFF); |
| 5820 | s16 b2 = ((state->Reg[src2] >> 0x10) & 0xFFFF); | 5820 | const s16 rn_hi = ((state->Reg[rn_idx] >> 16) & 0xFFFF); |
| 5821 | state->Reg[tar] = ((a1 + a2) & 0xFFFF) | (((b1 + b2) & 0xFFFF) << 0x10); | 5821 | |
| 5822 | state->Reg[rd_idx] = ((rn_lo + rm_lo) & 0xFFFF) | (((rn_hi + rm_hi) & 0xFFFF) << 16); | ||
| 5822 | return 1; | 5823 | return 1; |
| 5823 | } else if ((instr & 0xFF0) == 0xf50) { //ssax | 5824 | } else if ((instr & 0xFF0) == 0xf50) { //ssax |
| 5824 | u8 tar = BITS(12, 15); | 5825 | u8 tar = BITS(12, 15); |