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authorGravatar Nguyen Dac Nam2020-03-22 10:33:55 +0700
committerGravatar namkazy2020-03-22 10:53:35 +0700
commitdbfbe352e0b4dfc618be31a58d37c3f3606cab6a (patch)
treee5868dacfeba5ea08b13c9f4b487fab03610cc89 /src
parentMerge pull request #3531 from makigumo/yuzu_master (diff)
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maxwell_3d: implement MME shadow RAM
Diffstat (limited to 'src')
-rw-r--r--src/video_core/engines/maxwell_3d.h15
1 files changed, 14 insertions, 1 deletions
diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h
index 8a9e9992e..5e531e21b 100644
--- a/src/video_core/engines/maxwell_3d.h
+++ b/src/video_core/engines/maxwell_3d.h
@@ -531,6 +531,13 @@ public:
531 Fill = 0x1b02, 531 Fill = 0x1b02,
532 }; 532 };
533 533
534 enum class ShadowRamControl : u32 {
535 Track = 0,
536 TrackWithFilter = 1,
537 Passthrough = 2,
538 Replay = 3,
539 };
540
534 struct RenderTargetConfig { 541 struct RenderTargetConfig {
535 u32 address_high; 542 u32 address_high;
536 u32 address_low; 543 u32 address_low;
@@ -674,7 +681,9 @@ public:
674 u32 bind; 681 u32 bind;
675 } macros; 682 } macros;
676 683
677 INSERT_UNION_PADDING_WORDS(0x17); 684 ShadowRamControl shadow_ram_control;
685
686 INSERT_UNION_PADDING_WORDS(0x16);
678 687
679 Upload::Registers upload; 688 Upload::Registers upload;
680 struct { 689 struct {
@@ -1265,6 +1274,9 @@ public:
1265 }; 1274 };
1266 } regs{}; 1275 } regs{};
1267 1276
1277 /// Store temporary hw register values, used by some calls to restore state after a operation
1278 Regs shadow_state;
1279
1268 static_assert(sizeof(Regs) == Regs::NUM_REGS * sizeof(u32), "Maxwell3D Regs has wrong size"); 1280 static_assert(sizeof(Regs) == Regs::NUM_REGS * sizeof(u32), "Maxwell3D Regs has wrong size");
1269 static_assert(std::is_trivially_copyable_v<Regs>, "Maxwell3D Regs must be trivially copyable"); 1281 static_assert(std::is_trivially_copyable_v<Regs>, "Maxwell3D Regs must be trivially copyable");
1270 1282
@@ -1458,6 +1470,7 @@ private:
1458 "Field " #field_name " has invalid position") 1470 "Field " #field_name " has invalid position")
1459 1471
1460ASSERT_REG_POSITION(macros, 0x45); 1472ASSERT_REG_POSITION(macros, 0x45);
1473ASSERT_REG_POSITION(shadow_ram_control, 0x49);
1461ASSERT_REG_POSITION(upload, 0x60); 1474ASSERT_REG_POSITION(upload, 0x60);
1462ASSERT_REG_POSITION(exec_upload, 0x6C); 1475ASSERT_REG_POSITION(exec_upload, 0x6C);
1463ASSERT_REG_POSITION(data_upload, 0x6D); 1476ASSERT_REG_POSITION(data_upload, 0x6D);