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| author | 2014-03-31 22:26:50 -0400 | |
|---|---|---|
| committer | 2014-03-31 22:26:50 -0400 | |
| commit | d4b529111afc27447b0557b9a89cdf35f104bf87 (patch) | |
| tree | 3a39babcea58e1d2e143f16f79f51706dc124e12 /src | |
| parent | added simple processing loop and ELF loading to main()... hackish, will clean... (diff) | |
| download | yuzu-d4b529111afc27447b0557b9a89cdf35f104bf87.tar.gz yuzu-d4b529111afc27447b0557b9a89cdf35f104bf87.tar.xz yuzu-d4b529111afc27447b0557b9a89cdf35f104bf87.zip | |
added very hackish ARMulator core initialization and CPU stepping
Diffstat (limited to 'src')
| -rw-r--r-- | src/core/src/core.cpp | 103 |
1 files changed, 97 insertions, 6 deletions
diff --git a/src/core/src/core.cpp b/src/core/src/core.cpp index 6ed7c5be8..523b860f6 100644 --- a/src/core/src/core.cpp +++ b/src/core/src/core.cpp | |||
| @@ -24,37 +24,128 @@ | |||
| 24 | 24 | ||
| 25 | #include "log.h" | 25 | #include "log.h" |
| 26 | #include "core.h" | 26 | #include "core.h" |
| 27 | #include "mem_map.h" | ||
| 28 | #include "arm/armdefs.h" | ||
| 29 | #include "arm/disassembler/arm_disasm.h" | ||
| 27 | 30 | ||
| 28 | namespace Core { | 31 | namespace Core { |
| 29 | 32 | ||
| 33 | typedef struct arm11_core{ | ||
| 34 | conf_object_t* obj; | ||
| 35 | ARMul_State* state; | ||
| 36 | memory_space_intf* space; | ||
| 37 | }arm11_core_t; | ||
| 38 | |||
| 39 | arm11_core* core = NULL; | ||
| 40 | |||
| 41 | Arm* disasm = NULL; | ||
| 42 | |||
| 43 | //ARMul_State* g_arm_state = NULL; | ||
| 44 | |||
| 30 | /// Start the core | 45 | /// Start the core |
| 31 | void Start() { | 46 | void Start() { |
| 32 | // TODO(ShizZy): ImplementMe | 47 | // TODO(ShizZy): ImplementMe |
| 33 | } | 48 | } |
| 34 | 49 | ||
| 35 | /// Run the core CPU loop | 50 | /// Run the core CPU loop |
| 36 | void RunLoop() { | 51 | void RunLoop() { |
| 37 | // TODO(ShizZy): ImplementMe | 52 | // TODO(ShizZy): ImplementMe |
| 38 | } | 53 | } |
| 39 | 54 | ||
| 40 | /// Step the CPU one instruction | 55 | /// Step the CPU one instruction |
| 41 | void SingleStep() { | 56 | void SingleStep() { |
| 57 | //arm11_core_t* core = (arm11_core_t*)opaque->obj; | ||
| 58 | ARMul_State *state = core->state; | ||
| 59 | //if (state->space.conf_obj == NULL){ | ||
| 60 | // state->space.conf_obj = core->space->conf_obj; | ||
| 61 | // state->space.read = core->space->read; | ||
| 62 | // state->space.write = core->space->write; | ||
| 63 | //} | ||
| 64 | |||
| 65 | char next_instr[255]; | ||
| 66 | |||
| 67 | disasm->disasm(state->pc, Memory::Read32(state->pc), next_instr); | ||
| 68 | |||
| 69 | NOTICE_LOG(ARM11, "0x%08X : %s", state->pc, next_instr); | ||
| 70 | |||
| 71 | |||
| 72 | for (int i = 0; i < 15; i++) { | ||
| 73 | NOTICE_LOG(ARM11, "Reg[%02d] = 0x%08X", i, state->Reg[i]); | ||
| 74 | } | ||
| 75 | |||
| 76 | |||
| 77 | state->step++; | ||
| 78 | state->cycle++; | ||
| 79 | state->EndCondition = 0; | ||
| 80 | state->stop_simulator = 0; | ||
| 81 | //state->NextInstr = RESUME; /* treat as PC change */ | ||
| 82 | state->last_pc = state->Reg[15]; | ||
| 83 | state->Reg[15] = ARMul_DoInstr(state); | ||
| 84 | state->Cpsr = (state->Cpsr & 0x0fffffdf) | \ | ||
| 85 | (state->NFlag << 31) | \ | ||
| 86 | (state->ZFlag << 30) | \ | ||
| 87 | (state->CFlag << 29) | \ | ||
| 88 | (state->VFlag << 28);// | \ | ||
| 89 | //(state->TFlag << 5); | ||
| 90 | |||
| 91 | //FLUSHPIPE; | ||
| 42 | } | 92 | } |
| 43 | 93 | ||
| 44 | /// Halt the core | 94 | /// Halt the core |
| 45 | void Halt(const char *msg) { | 95 | void Halt(const char *msg) { |
| 46 | // TODO(ShizZy): ImplementMe | 96 | // TODO(ShizZy): ImplementMe |
| 47 | } | 97 | } |
| 48 | 98 | ||
| 49 | /// Kill the core | 99 | /// Kill the core |
| 50 | void Stop() { | 100 | void Stop() { |
| 51 | // TODO(ShizZy): ImplementMe | 101 | // TODO(ShizZy): ImplementMe |
| 52 | } | 102 | } |
| 53 | 103 | ||
| 54 | /// Initialize the core | 104 | /// Initialize the core |
| 105 | const static cpu_config_t arm11_cpu_info = { "armv6", "arm11", 0x0007b000, 0x0007f000, NONCACHE }; | ||
| 55 | int Init() { | 106 | int Init() { |
| 56 | NOTICE_LOG(MASTER_LOG, "Core initialized OK"); | 107 | NOTICE_LOG(MASTER_LOG, "Core initialized OK"); |
| 57 | return 0; | 108 | |
| 109 | disasm = new Arm(); | ||
| 110 | core = (arm11_core_t*)malloc(sizeof(arm11_core_t)); | ||
| 111 | //core->obj = new_conf_object(obj_name, core); | ||
| 112 | ARMul_EmulateInit(); | ||
| 113 | ARMul_State* state = new ARMul_State; | ||
| 114 | ARMul_NewState(state); | ||
| 115 | state->abort_model = 0; | ||
| 116 | state->cpu = (cpu_config_t*)&arm11_cpu_info; | ||
| 117 | state->bigendSig = LOW; | ||
| 118 | |||
| 119 | ARMul_SelectProcessor(state, ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop); | ||
| 120 | state->lateabtSig = LOW; | ||
| 121 | mmu_init(state); | ||
| 122 | /* reset the core to initial state */ | ||
| 123 | ARMul_Reset(state); | ||
| 124 | state->NextInstr = 0; | ||
| 125 | state->Emulate = 3; | ||
| 126 | #if 0 | ||
| 127 | state->mmu.ops.read_byte = arm11_read_byte; | ||
| 128 | state->mmu.ops.read_halfword = arm11_read_halfword; | ||
| 129 | state->mmu.ops.read_word = arm11_read_word; | ||
| 130 | state->mmu.ops.write_byte = arm11_write_byte; | ||
| 131 | state->mmu.ops.write_halfword = arm11_write_halfword; | ||
| 132 | state->mmu.ops.write_word = arm11_write_word; | ||
| 133 | #endif | ||
| 134 | core->state = state; | ||
| 135 | |||
| 136 | state->pc = state->Reg[15] = 0x080c3ee0; // Hardcoded set PC to start address of a homebrew ROM | ||
| 137 | // this is where most launcher.dat code loads /bunnei | ||
| 138 | |||
| 139 | state->Reg[13] = 0x10000000; // Set stack pointer to the top of the stack, not sure if this is | ||
| 140 | // right? /bunnei | ||
| 141 | |||
| 142 | //state->s | ||
| 143 | return 0; | ||
| 144 | } | ||
| 145 | |||
| 146 | void Shutdown() { | ||
| 147 | //delete g_arm_state; | ||
| 148 | //g_arm_state = NULL; | ||
| 58 | } | 149 | } |
| 59 | 150 | ||
| 60 | } // namespace | 151 | } // namespace |