summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorGravatar Lioncash2015-01-11 22:11:45 -0500
committerGravatar Lioncash2015-01-11 22:27:09 -0500
commitd2a05bbbc6b737482e2f3be6f3cf60f0f9ee5ecc (patch)
treef2111d9e3d66d99be3e9f3fdc573aa7e8189bb44 /src
parentMerge pull request #456 from Subv/waitsync1 (diff)
downloadyuzu-d2a05bbbc6b737482e2f3be6f3cf60f0f9ee5ecc.tar.gz
yuzu-d2a05bbbc6b737482e2f3be6f3cf60f0f9ee5ecc.tar.xz
yuzu-d2a05bbbc6b737482e2f3be6f3cf60f0f9ee5ecc.zip
dyncom: Fix ADC overflow flag setting
Diffstat (limited to 'src')
-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp20
1 files changed, 12 insertions, 8 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index 4759c7653..bf864c7a7 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -4005,10 +4005,14 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
4005 { 4005 {
4006 adc_inst *inst_cream = (adc_inst *)inst_base->component; 4006 adc_inst *inst_cream = (adc_inst *)inst_base->component;
4007 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { 4007 if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
4008 lop = RN; 4008 u32 left = RN;
4009 unsigned int sht_op = SHIFTER_OPERAND; 4009 u32 right = SHIFTER_OPERAND;
4010 rop = SHIFTER_OPERAND + cpu->CFlag; 4010
4011 RD = dst = lop + rop; 4011 u64 unsigned_sum = (left + right + cpu->CFlag);
4012 s64 signed_sum = (s64)(s32)left + (s64)(s32)right + (s64)cpu->CFlag;
4013 u32 result = (unsigned_sum & 0xFFFFFFFF);
4014
4015 RD = result;
4012 if (inst_cream->S && (inst_cream->Rd == 15)) { 4016 if (inst_cream->S && (inst_cream->Rd == 15)) {
4013 if (CurrentModeHasSPSR) { 4017 if (CurrentModeHasSPSR) {
4014 cpu->Cpsr = cpu->Spsr_copy; 4018 cpu->Cpsr = cpu->Spsr_copy;
@@ -4016,10 +4020,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
4016 LOAD_NZCVT; 4020 LOAD_NZCVT;
4017 } 4021 }
4018 } else if (inst_cream->S) { 4022 } else if (inst_cream->S) {
4019 UPDATE_NFLAG(dst); 4023 UPDATE_NFLAG(result);
4020 UPDATE_ZFLAG(dst); 4024 UPDATE_ZFLAG(result);
4021 UPDATE_CFLAG_CARRY_FROM_ADD(lop, sht_op, cpu->CFlag); 4025 UPDATE_CFLAG_CARRY_FROM_ADD(left, right, cpu->CFlag);
4022 UPDATE_VFLAG((int)dst, (int)lop, (int)rop); 4026 cpu->VFlag = ((s64)(s32)result != signed_sum);
4023 } 4027 }
4024 if (inst_cream->Rd == 15) { 4028 if (inst_cream->Rd == 15) {
4025 INC_PC(sizeof(adc_inst)); 4029 INC_PC(sizeof(adc_inst));