diff options
| author | 2015-12-19 18:51:02 -0500 | |
|---|---|---|
| committer | 2015-12-20 21:19:02 -0500 | |
| commit | d09b7a3c127fdd97d73d0c10820c88c906bb59d1 (patch) | |
| tree | 0e13e89b46b99b3d814e0b7da4725a75c1e812e4 /src | |
| parent | dyncom: Handle unprivileged load/store variants correctly (diff) | |
| download | yuzu-d09b7a3c127fdd97d73d0c10820c88c906bb59d1.tar.gz yuzu-d09b7a3c127fdd97d73d0c10820c88c906bb59d1.tar.xz yuzu-d09b7a3c127fdd97d73d0c10820c88c906bb59d1.zip | |
dyncom: Remove PC dispatch from several instructions
These instructions aren't capable of using the PC as a destination
Diffstat (limited to 'src')
| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom_interpreter.cpp | 94 |
1 files changed, 0 insertions, 94 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp index 187aee702..459877eae 100644 --- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp +++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp | |||
| @@ -1623,9 +1623,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrb)(unsigned int inst, int index) | |||
| 1623 | inst_cream->inst = inst; | 1623 | inst_cream->inst = inst; |
| 1624 | inst_cream->get_addr = get_calc_addr_op(inst); | 1624 | inst_cream->get_addr = get_calc_addr_op(inst); |
| 1625 | 1625 | ||
| 1626 | if (BITS(inst, 12, 15) == 15) { | ||
| 1627 | inst_base->br = INDIRECT_BRANCH; | ||
| 1628 | } | ||
| 1629 | return inst_base; | 1626 | return inst_base; |
| 1630 | } | 1627 | } |
| 1631 | static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrbt)(unsigned int inst, int index) | 1628 | static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrbt)(unsigned int inst, int index) |
| @@ -1646,9 +1643,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrbt)(unsigned int inst, int index) | |||
| 1646 | DEBUG_MSG; | 1643 | DEBUG_MSG; |
| 1647 | } | 1644 | } |
| 1648 | 1645 | ||
| 1649 | if (BITS(inst, 12, 15) == 15) { | ||
| 1650 | inst_base->br = INDIRECT_BRANCH; | ||
| 1651 | } | ||
| 1652 | return inst_base; | 1646 | return inst_base; |
| 1653 | } | 1647 | } |
| 1654 | static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrd)(unsigned int inst, int index) | 1648 | static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrd)(unsigned int inst, int index) |
| @@ -1703,9 +1697,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrh)(unsigned int inst, int index) | |||
| 1703 | inst_cream->inst = inst; | 1697 | inst_cream->inst = inst; |
| 1704 | inst_cream->get_addr = get_calc_addr_op(inst); | 1698 | inst_cream->get_addr = get_calc_addr_op(inst); |
| 1705 | 1699 | ||
| 1706 | if (BITS(inst, 12, 15) == 15) { | ||
| 1707 | inst_base->br = INDIRECT_BRANCH; | ||
| 1708 | } | ||
| 1709 | return inst_base; | 1700 | return inst_base; |
| 1710 | } | 1701 | } |
| 1711 | static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrsb)(unsigned int inst, int index) | 1702 | static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrsb)(unsigned int inst, int index) |
| @@ -1720,9 +1711,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrsb)(unsigned int inst, int index) | |||
| 1720 | inst_cream->inst = inst; | 1711 | inst_cream->inst = inst; |
| 1721 | inst_cream->get_addr = get_calc_addr_op(inst); | 1712 | inst_cream->get_addr = get_calc_addr_op(inst); |
| 1722 | 1713 | ||
| 1723 | if (BITS(inst, 12, 15) == 15) { | ||
| 1724 | inst_base->br = INDIRECT_BRANCH; | ||
| 1725 | } | ||
| 1726 | return inst_base; | 1714 | return inst_base; |
| 1727 | } | 1715 | } |
| 1728 | static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrsh)(unsigned int inst, int index) | 1716 | static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrsh)(unsigned int inst, int index) |
| @@ -1737,9 +1725,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrsh)(unsigned int inst, int index) | |||
| 1737 | inst_cream->inst = inst; | 1725 | inst_cream->inst = inst; |
| 1738 | inst_cream->get_addr = get_calc_addr_op(inst); | 1726 | inst_cream->get_addr = get_calc_addr_op(inst); |
| 1739 | 1727 | ||
| 1740 | if (BITS(inst, 12, 15) == 15) { | ||
| 1741 | inst_base->br = INDIRECT_BRANCH; | ||
| 1742 | } | ||
| 1743 | return inst_base; | 1728 | return inst_base; |
| 1744 | } | 1729 | } |
| 1745 | static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrt)(unsigned int inst, int index) | 1730 | static ARM_INST_PTR INTERPRETER_TRANSLATE(ldrt)(unsigned int inst, int index) |
| @@ -2597,9 +2582,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(str)(unsigned int inst, int index) | |||
| 2597 | inst_cream->inst = inst; | 2582 | inst_cream->inst = inst; |
| 2598 | inst_cream->get_addr = get_calc_addr_op(inst); | 2583 | inst_cream->get_addr = get_calc_addr_op(inst); |
| 2599 | 2584 | ||
| 2600 | if (BITS(inst, 12, 15) == 15) { | ||
| 2601 | inst_base->br = INDIRECT_BRANCH; | ||
| 2602 | } | ||
| 2603 | return inst_base; | 2585 | return inst_base; |
| 2604 | } | 2586 | } |
| 2605 | static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtb)(unsigned int inst, int index) | 2587 | static ARM_INST_PTR INTERPRETER_TRANSLATE(uxtb)(unsigned int inst, int index) |
| @@ -2645,9 +2627,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(strb)(unsigned int inst, int index) | |||
| 2645 | inst_cream->inst = inst; | 2627 | inst_cream->inst = inst; |
| 2646 | inst_cream->get_addr = get_calc_addr_op(inst); | 2628 | inst_cream->get_addr = get_calc_addr_op(inst); |
| 2647 | 2629 | ||
| 2648 | if (BITS(inst, 12, 15) == 15) { | ||
| 2649 | inst_base->br = INDIRECT_BRANCH; | ||
| 2650 | } | ||
| 2651 | return inst_base; | 2630 | return inst_base; |
| 2652 | } | 2631 | } |
| 2653 | static ARM_INST_PTR INTERPRETER_TRANSLATE(strbt)(unsigned int inst, int index) | 2632 | static ARM_INST_PTR INTERPRETER_TRANSLATE(strbt)(unsigned int inst, int index) |
| @@ -2669,9 +2648,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(strbt)(unsigned int inst, int index) | |||
| 2669 | DEBUG_MSG; | 2648 | DEBUG_MSG; |
| 2670 | } | 2649 | } |
| 2671 | 2650 | ||
| 2672 | if (BITS(inst, 12, 15) == 15) { | ||
| 2673 | inst_base->br = INDIRECT_BRANCH; | ||
| 2674 | } | ||
| 2675 | return inst_base; | 2651 | return inst_base; |
| 2676 | } | 2652 | } |
| 2677 | static ARM_INST_PTR INTERPRETER_TRANSLATE(strd)(unsigned int inst, int index){ | 2653 | static ARM_INST_PTR INTERPRETER_TRANSLATE(strd)(unsigned int inst, int index){ |
| @@ -2685,9 +2661,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(strd)(unsigned int inst, int index){ | |||
| 2685 | inst_cream->inst = inst; | 2661 | inst_cream->inst = inst; |
| 2686 | inst_cream->get_addr = get_calc_addr_op(inst); | 2662 | inst_cream->get_addr = get_calc_addr_op(inst); |
| 2687 | 2663 | ||
| 2688 | if (BITS(inst, 12, 15) == 15) { | ||
| 2689 | inst_base->br = INDIRECT_BRANCH; | ||
| 2690 | } | ||
| 2691 | return inst_base; | 2664 | return inst_base; |
| 2692 | } | 2665 | } |
| 2693 | static ARM_INST_PTR INTERPRETER_TRANSLATE(strex)(unsigned int inst, int index) | 2666 | static ARM_INST_PTR INTERPRETER_TRANSLATE(strex)(unsigned int inst, int index) |
| @@ -2729,9 +2702,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(strh)(unsigned int inst, int index) | |||
| 2729 | inst_cream->inst = inst; | 2702 | inst_cream->inst = inst; |
| 2730 | inst_cream->get_addr = get_calc_addr_op(inst); | 2703 | inst_cream->get_addr = get_calc_addr_op(inst); |
| 2731 | 2704 | ||
| 2732 | if (BITS(inst, 12, 15) == 15) { | ||
| 2733 | inst_base->br = INDIRECT_BRANCH; | ||
| 2734 | } | ||
| 2735 | return inst_base; | 2705 | return inst_base; |
| 2736 | } | 2706 | } |
| 2737 | static ARM_INST_PTR INTERPRETER_TRANSLATE(strt)(unsigned int inst, int index) | 2707 | static ARM_INST_PTR INTERPRETER_TRANSLATE(strt)(unsigned int inst, int index) |
| @@ -2757,9 +2727,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(strt)(unsigned int inst, int index) | |||
| 2757 | DEBUG_MSG; | 2727 | DEBUG_MSG; |
| 2758 | } | 2728 | } |
| 2759 | 2729 | ||
| 2760 | if (BITS(inst, 12, 15) == 15) { | ||
| 2761 | inst_base->br = INDIRECT_BRANCH; | ||
| 2762 | } | ||
| 2763 | return inst_base; | 2730 | return inst_base; |
| 2764 | } | 2731 | } |
| 2765 | static ARM_INST_PTR INTERPRETER_TRANSLATE(sub)(unsigned int inst, int index) | 2732 | static ARM_INST_PTR INTERPRETER_TRANSLATE(sub)(unsigned int inst, int index) |
| @@ -2808,9 +2775,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(swp)(unsigned int inst, int index) | |||
| 2808 | inst_cream->Rd = BITS(inst, 12, 15); | 2775 | inst_cream->Rd = BITS(inst, 12, 15); |
| 2809 | inst_cream->Rm = BITS(inst, 0, 3); | 2776 | inst_cream->Rm = BITS(inst, 0, 3); |
| 2810 | 2777 | ||
| 2811 | if (inst_cream->Rd == 15) { | ||
| 2812 | inst_base->br = INDIRECT_BRANCH; | ||
| 2813 | } | ||
| 2814 | return inst_base; | 2778 | return inst_base; |
| 2815 | } | 2779 | } |
| 2816 | static ARM_INST_PTR INTERPRETER_TRANSLATE(swpb)(unsigned int inst, int index){ | 2780 | static ARM_INST_PTR INTERPRETER_TRANSLATE(swpb)(unsigned int inst, int index){ |
| @@ -2825,9 +2789,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(swpb)(unsigned int inst, int index){ | |||
| 2825 | inst_cream->Rd = BITS(inst, 12, 15); | 2789 | inst_cream->Rd = BITS(inst, 12, 15); |
| 2826 | inst_cream->Rm = BITS(inst, 0, 3); | 2790 | inst_cream->Rm = BITS(inst, 0, 3); |
| 2827 | 2791 | ||
| 2828 | if (inst_cream->Rd == 15) { | ||
| 2829 | inst_base->br = INDIRECT_BRANCH; | ||
| 2830 | } | ||
| 2831 | return inst_base; | 2792 | return inst_base; |
| 2832 | } | 2793 | } |
| 2833 | static ARM_INST_PTR INTERPRETER_TRANSLATE(sxtab)(unsigned int inst, int index){ | 2794 | static ARM_INST_PTR INTERPRETER_TRANSLATE(sxtab)(unsigned int inst, int index){ |
| @@ -2915,9 +2876,6 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(tst)(unsigned int inst, int index) | |||
| 2915 | inst_cream->shifter_operand = BITS(inst, 0, 11); | 2876 | inst_cream->shifter_operand = BITS(inst, 0, 11); |
| 2916 | inst_cream->shtop_func = get_shtop(inst); | 2877 | inst_cream->shtop_func = get_shtop(inst); |
| 2917 | 2878 | ||
| 2918 | if (inst_cream->Rd == 15) | ||
| 2919 | inst_base->br = INDIRECT_BRANCH; | ||
| 2920 | |||
| 2921 | return inst_base; | 2879 | return inst_base; |
| 2922 | } | 2880 | } |
| 2923 | 2881 | ||
| @@ -4477,11 +4435,6 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) { | |||
| 4477 | inst_cream->get_addr(cpu, inst_cream->inst, addr); | 4435 | inst_cream->get_addr(cpu, inst_cream->inst, addr); |
| 4478 | 4436 | ||
| 4479 | cpu->Reg[BITS(inst_cream->inst, 12, 15)] = cpu->ReadMemory8(addr); | 4437 | cpu->Reg[BITS(inst_cream->inst, 12, 15)] = cpu->ReadMemory8(addr); |
| 4480 | |||
| 4481 | if (BITS(inst_cream->inst, 12, 15) == 15) { | ||
| 4482 | INC_PC(sizeof(ldst_inst)); | ||
| 4483 | goto DISPATCH; | ||
| 4484 | } | ||
| 4485 | } | 4438 | } |
| 4486 | cpu->Reg[15] += cpu->GetInstructionSize(); | 4439 | cpu->Reg[15] += cpu->GetInstructionSize(); |
| 4487 | INC_PC(sizeof(ldst_inst)); | 4440 | INC_PC(sizeof(ldst_inst)); |
| @@ -4502,11 +4455,6 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) { | |||
| 4502 | cpu->ChangePrivilegeMode(previous_mode); | 4455 | cpu->ChangePrivilegeMode(previous_mode); |
| 4503 | 4456 | ||
| 4504 | cpu->Reg[dest_index] = value; | 4457 | cpu->Reg[dest_index] = value; |
| 4505 | |||
| 4506 | if (dest_index == 15) { | ||
| 4507 | INC_PC(sizeof(ldst_inst)); | ||
| 4508 | goto DISPATCH; | ||
| 4509 | } | ||
| 4510 | } | 4458 | } |
| 4511 | cpu->Reg[15] += cpu->GetInstructionSize(); | 4459 | cpu->Reg[15] += cpu->GetInstructionSize(); |
| 4512 | INC_PC(sizeof(ldst_inst)); | 4460 | INC_PC(sizeof(ldst_inst)); |
| @@ -4542,10 +4490,6 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) { | |||
| 4542 | cpu->SetExclusiveMemoryAddress(read_addr); | 4490 | cpu->SetExclusiveMemoryAddress(read_addr); |
| 4543 | 4491 | ||
| 4544 | RD = cpu->ReadMemory32(read_addr); | 4492 | RD = cpu->ReadMemory32(read_addr); |
| 4545 | if (inst_cream->Rd == 15) { | ||
| 4546 | INC_PC(sizeof(generic_arm_inst)); | ||
| 4547 | goto DISPATCH; | ||
| 4548 | } | ||
| 4549 | } | 4493 | } |
| 4550 | cpu->Reg[15] += cpu->GetInstructionSize(); | 4494 | cpu->Reg[15] += cpu->GetInstructionSize(); |
| 4551 | INC_PC(sizeof(generic_arm_inst)); | 4495 | INC_PC(sizeof(generic_arm_inst)); |
| @@ -4561,10 +4505,6 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) { | |||
| 4561 | cpu->SetExclusiveMemoryAddress(read_addr); | 4505 | cpu->SetExclusiveMemoryAddress(read_addr); |
| 4562 | 4506 | ||
| 4563 | RD = cpu->ReadMemory8(read_addr); | 4507 | RD = cpu->ReadMemory8(read_addr); |
| 4564 | if (inst_cream->Rd == 15) { | ||
| 4565 | INC_PC(sizeof(generic_arm_inst)); | ||
| 4566 | goto DISPATCH; | ||
| 4567 | } | ||
| 4568 | } | 4508 | } |
| 4569 | cpu->Reg[15] += cpu->GetInstructionSize(); | 4509 | cpu->Reg[15] += cpu->GetInstructionSize(); |
| 4570 | INC_PC(sizeof(generic_arm_inst)); | 4510 | INC_PC(sizeof(generic_arm_inst)); |
| @@ -4580,10 +4520,6 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) { | |||
| 4580 | cpu->SetExclusiveMemoryAddress(read_addr); | 4520 | cpu->SetExclusiveMemoryAddress(read_addr); |
| 4581 | 4521 | ||
| 4582 | RD = cpu->ReadMemory16(read_addr); | 4522 | RD = cpu->ReadMemory16(read_addr); |
| 4583 | if (inst_cream->Rd == 15) { | ||
| 4584 | INC_PC(sizeof(generic_arm_inst)); | ||
| 4585 | goto DISPATCH; | ||
| 4586 | } | ||
| 4587 | } | 4523 | } |
| 4588 | cpu->Reg[15] += cpu->GetInstructionSize(); | 4524 | cpu->Reg[15] += cpu->GetInstructionSize(); |
| 4589 | INC_PC(sizeof(generic_arm_inst)); | 4525 | INC_PC(sizeof(generic_arm_inst)); |
| @@ -4600,11 +4536,6 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) { | |||
| 4600 | 4536 | ||
| 4601 | RD = cpu->ReadMemory32(read_addr); | 4537 | RD = cpu->ReadMemory32(read_addr); |
| 4602 | RD2 = cpu->ReadMemory32(read_addr + 4); | 4538 | RD2 = cpu->ReadMemory32(read_addr + 4); |
| 4603 | |||
| 4604 | if (inst_cream->Rd == 15) { | ||
| 4605 | INC_PC(sizeof(generic_arm_inst)); | ||
| 4606 | goto DISPATCH; | ||
| 4607 | } | ||
| 4608 | } | 4539 | } |
| 4609 | cpu->Reg[15] += cpu->GetInstructionSize(); | 4540 | cpu->Reg[15] += cpu->GetInstructionSize(); |
| 4610 | INC_PC(sizeof(generic_arm_inst)); | 4541 | INC_PC(sizeof(generic_arm_inst)); |
| @@ -4618,10 +4549,6 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) { | |||
| 4618 | inst_cream->get_addr(cpu, inst_cream->inst, addr); | 4549 | inst_cream->get_addr(cpu, inst_cream->inst, addr); |
| 4619 | 4550 | ||
| 4620 | cpu->Reg[BITS(inst_cream->inst, 12, 15)] = cpu->ReadMemory16(addr); | 4551 | cpu->Reg[BITS(inst_cream->inst, 12, 15)] = cpu->ReadMemory16(addr); |
| 4621 | if (BITS(inst_cream->inst, 12, 15) == 15) { | ||
| 4622 | INC_PC(sizeof(ldst_inst)); | ||
| 4623 | goto DISPATCH; | ||
| 4624 | } | ||
| 4625 | } | 4552 | } |
| 4626 | cpu->Reg[15] += cpu->GetInstructionSize(); | 4553 | cpu->Reg[15] += cpu->GetInstructionSize(); |
| 4627 | INC_PC(sizeof(ldst_inst)); | 4554 | INC_PC(sizeof(ldst_inst)); |
| @@ -4638,10 +4565,6 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) { | |||
| 4638 | value |= 0xffffff00; | 4565 | value |= 0xffffff00; |
| 4639 | } | 4566 | } |
| 4640 | cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; | 4567 | cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; |
| 4641 | if (BITS(inst_cream->inst, 12, 15) == 15) { | ||
| 4642 | INC_PC(sizeof(ldst_inst)); | ||
| 4643 | goto DISPATCH; | ||
| 4644 | } | ||
| 4645 | } | 4568 | } |
| 4646 | cpu->Reg[15] += cpu->GetInstructionSize(); | 4569 | cpu->Reg[15] += cpu->GetInstructionSize(); |
| 4647 | INC_PC(sizeof(ldst_inst)); | 4570 | INC_PC(sizeof(ldst_inst)); |
| @@ -4659,10 +4582,6 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) { | |||
| 4659 | value |= 0xffff0000; | 4582 | value |= 0xffff0000; |
| 4660 | } | 4583 | } |
| 4661 | cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; | 4584 | cpu->Reg[BITS(inst_cream->inst, 12, 15)] = value; |
| 4662 | if (BITS(inst_cream->inst, 12, 15) == 15) { | ||
| 4663 | INC_PC(sizeof(ldst_inst)); | ||
| 4664 | goto DISPATCH; | ||
| 4665 | } | ||
| 4666 | } | 4585 | } |
| 4667 | cpu->Reg[15] += cpu->GetInstructionSize(); | 4586 | cpu->Reg[15] += cpu->GetInstructionSize(); |
| 4668 | INC_PC(sizeof(ldst_inst)); | 4587 | INC_PC(sizeof(ldst_inst)); |
| @@ -4683,11 +4602,6 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) { | |||
| 4683 | cpu->ChangePrivilegeMode(previous_mode); | 4602 | cpu->ChangePrivilegeMode(previous_mode); |
| 4684 | 4603 | ||
| 4685 | cpu->Reg[dest_index] = value; | 4604 | cpu->Reg[dest_index] = value; |
| 4686 | |||
| 4687 | if (dest_index == 15) { | ||
| 4688 | INC_PC(sizeof(ldst_inst)); | ||
| 4689 | goto DISPATCH; | ||
| 4690 | } | ||
| 4691 | } | 4605 | } |
| 4692 | cpu->Reg[15] += cpu->GetInstructionSize(); | 4606 | cpu->Reg[15] += cpu->GetInstructionSize(); |
| 4693 | INC_PC(sizeof(ldst_inst)); | 4607 | INC_PC(sizeof(ldst_inst)); |
| @@ -4744,10 +4658,6 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) { | |||
| 4744 | UPDATE_NFLAG(RD); | 4658 | UPDATE_NFLAG(RD); |
| 4745 | UPDATE_ZFLAG(RD); | 4659 | UPDATE_ZFLAG(RD); |
| 4746 | } | 4660 | } |
| 4747 | if (inst_cream->Rd == 15) { | ||
| 4748 | INC_PC(sizeof(mla_inst)); | ||
| 4749 | goto DISPATCH; | ||
| 4750 | } | ||
| 4751 | } | 4661 | } |
| 4752 | cpu->Reg[15] += cpu->GetInstructionSize(); | 4662 | cpu->Reg[15] += cpu->GetInstructionSize(); |
| 4753 | INC_PC(sizeof(mla_inst)); | 4663 | INC_PC(sizeof(mla_inst)); |
| @@ -4896,10 +4806,6 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) { | |||
| 4896 | UPDATE_NFLAG(RD); | 4806 | UPDATE_NFLAG(RD); |
| 4897 | UPDATE_ZFLAG(RD); | 4807 | UPDATE_ZFLAG(RD); |
| 4898 | } | 4808 | } |
| 4899 | if (inst_cream->Rd == 15) { | ||
| 4900 | INC_PC(sizeof(mul_inst)); | ||
| 4901 | goto DISPATCH; | ||
| 4902 | } | ||
| 4903 | } | 4809 | } |
| 4904 | cpu->Reg[15] += cpu->GetInstructionSize(); | 4810 | cpu->Reg[15] += cpu->GetInstructionSize(); |
| 4905 | INC_PC(sizeof(mul_inst)); | 4811 | INC_PC(sizeof(mul_inst)); |