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| author | 2018-12-18 03:16:09 -0300 | |
|---|---|---|
| committer | 2019-01-15 17:54:52 -0300 | |
| commit | cf4a08d95098370868fb631a0436f2a4968df9af (patch) | |
| tree | 201a43fd7dd59d69678716bf941d134b5e2da938 /src | |
| parent | shader_decode: Implement MOV_SYS (diff) | |
| download | yuzu-cf4a08d95098370868fb631a0436f2a4968df9af.tar.gz yuzu-cf4a08d95098370868fb631a0436f2a4968df9af.tar.xz yuzu-cf4a08d95098370868fb631a0436f2a4968df9af.zip | |
shader_decode: Implement HADD2_IMM and HMUL2_IMM
Diffstat (limited to 'src')
| -rw-r--r-- | src/video_core/shader/decode/arithmetic_half_immediate.cpp | 29 |
1 files changed, 28 insertions, 1 deletions
diff --git a/src/video_core/shader/decode/arithmetic_half_immediate.cpp b/src/video_core/shader/decode/arithmetic_half_immediate.cpp index 8d8a2dad9..5c280a1a6 100644 --- a/src/video_core/shader/decode/arithmetic_half_immediate.cpp +++ b/src/video_core/shader/decode/arithmetic_half_immediate.cpp | |||
| @@ -16,7 +16,34 @@ u32 ShaderIR::DecodeArithmeticHalfImmediate(BasicBlock& bb, u32 pc) { | |||
| 16 | const Instruction instr = {program_code[pc]}; | 16 | const Instruction instr = {program_code[pc]}; |
| 17 | const auto opcode = OpCode::Decode(instr); | 17 | const auto opcode = OpCode::Decode(instr); |
| 18 | 18 | ||
| 19 | UNIMPLEMENTED(); | 19 | if (opcode->get().GetId() == OpCode::Id::HADD2_IMM) { |
| 20 | UNIMPLEMENTED_IF(instr.alu_half_imm.ftz != 0); | ||
| 21 | } else { | ||
| 22 | UNIMPLEMENTED_IF(instr.alu_half_imm.precision != Tegra::Shader::HalfPrecision::None); | ||
| 23 | } | ||
| 24 | UNIMPLEMENTED_IF_MSG(instr.alu_half_imm.saturate != 0, | ||
| 25 | "Half float immediate saturation not implemented"); | ||
| 26 | |||
| 27 | Node op_a = GetRegister(instr.gpr8); | ||
| 28 | op_a = GetOperandAbsNegHalf(op_a, instr.alu_half_imm.abs_a, instr.alu_half_imm.negate_a); | ||
| 29 | |||
| 30 | const Node op_b = UnpackHalfImmediate(instr, true); | ||
| 31 | |||
| 32 | Node value = [&]() { | ||
| 33 | MetaHalfArithmetic meta{true, {instr.alu_half_imm.type_a}}; | ||
| 34 | switch (opcode->get().GetId()) { | ||
| 35 | case OpCode::Id::HADD2_IMM: | ||
| 36 | return Operation(OperationCode::HAdd, meta, op_a, op_b); | ||
| 37 | case OpCode::Id::HMUL2_IMM: | ||
| 38 | return Operation(OperationCode::HMul, meta, op_a, op_b); | ||
| 39 | default: | ||
| 40 | UNREACHABLE(); | ||
| 41 | return Immediate(0); | ||
| 42 | } | ||
| 43 | }(); | ||
| 44 | value = HalfMerge(GetRegister(instr.gpr0), value, instr.alu_half_imm.merge); | ||
| 45 | |||
| 46 | SetRegister(bb, instr.gpr0, value); | ||
| 20 | 47 | ||
| 21 | return pc; | 48 | return pc; |
| 22 | } | 49 | } |