diff options
| author | 2014-04-03 22:06:42 -0400 | |
|---|---|---|
| committer | 2014-04-03 22:07:07 -0400 | |
| commit | c2d4c7d4f4cf41ec7be5600bea929dbde6d5edb7 (patch) | |
| tree | 7895ea620721dcd46d4379d291f82fdb2c479cc3 /src | |
| parent | added hack to allow physical mem read/writes (diff) | |
| download | yuzu-c2d4c7d4f4cf41ec7be5600bea929dbde6d5edb7.tar.gz yuzu-c2d4c7d4f4cf41ec7be5600bea929dbde6d5edb7.tar.xz yuzu-c2d4c7d4f4cf41ec7be5600bea929dbde6d5edb7.zip | |
added some commented out ARMulator functions
Diffstat (limited to 'src')
| -rw-r--r-- | src/core/src/core.cpp | 23 |
1 files changed, 3 insertions, 20 deletions
diff --git a/src/core/src/core.cpp b/src/core/src/core.cpp index 800a2a3fb..edae66b9f 100644 --- a/src/core/src/core.cpp +++ b/src/core/src/core.cpp | |||
| @@ -26,6 +26,7 @@ | |||
| 26 | #include "core.h" | 26 | #include "core.h" |
| 27 | #include "mem_map.h" | 27 | #include "mem_map.h" |
| 28 | #include "arm/armdefs.h" | 28 | #include "arm/armdefs.h" |
| 29 | #include "arm/armemu.h" | ||
| 29 | #include "arm/disassembler/arm_disasm.h" | 30 | #include "arm/disassembler/arm_disasm.h" |
| 30 | 31 | ||
| 31 | namespace Core { | 32 | namespace Core { |
| @@ -54,31 +55,13 @@ void RunLoop() { | |||
| 54 | 55 | ||
| 55 | /// Step the CPU one instruction | 56 | /// Step the CPU one instruction |
| 56 | void SingleStep() { | 57 | void SingleStep() { |
| 57 | //arm11_core_t* core = (arm11_core_t*)opaque->obj; | ||
| 58 | ARMul_State *state = core->state; | 58 | ARMul_State *state = core->state; |
| 59 | //if (state->space.conf_obj == NULL){ | ||
| 60 | // state->space.conf_obj = core->space->conf_obj; | ||
| 61 | // state->space.read = core->space->read; | ||
| 62 | // state->space.write = core->space->write; | ||
| 63 | //} | ||
| 64 | |||
| 65 | char next_instr[255]; | ||
| 66 | |||
| 67 | disasm->disasm(state->pc, Memory::Read32(state->pc), next_instr); | ||
| 68 | |||
| 69 | NOTICE_LOG(ARM11, "0x%08X : %s", state->pc, next_instr); | ||
| 70 | |||
| 71 | |||
| 72 | for (int i = 0; i < 15; i++) { | ||
| 73 | NOTICE_LOG(ARM11, "Reg[%02d] = 0x%08X", i, state->Reg[i]); | ||
| 74 | } | ||
| 75 | |||
| 76 | 59 | ||
| 77 | state->step++; | 60 | state->step++; |
| 78 | state->cycle++; | 61 | state->cycle++; |
| 79 | state->EndCondition = 0; | 62 | state->EndCondition = 0; |
| 80 | state->stop_simulator = 0; | 63 | state->stop_simulator = 0; |
| 81 | //state->NextInstr = RESUME; /* treat as PC change */ | 64 | state->NextInstr = RESUME; /* treat as PC change */ |
| 82 | state->last_pc = state->Reg[15]; | 65 | state->last_pc = state->Reg[15]; |
| 83 | state->Reg[15] = ARMul_DoInstr(state); | 66 | state->Reg[15] = ARMul_DoInstr(state); |
| 84 | state->Cpsr = (state->Cpsr & 0x0fffffdf) | \ | 67 | state->Cpsr = (state->Cpsr & 0x0fffffdf) | \ |
| @@ -88,7 +71,7 @@ void SingleStep() { | |||
| 88 | (state->VFlag << 28);// | \ | 71 | (state->VFlag << 28);// | \ |
| 89 | //(state->TFlag << 5); | 72 | //(state->TFlag << 5); |
| 90 | 73 | ||
| 91 | //FLUSHPIPE; | 74 | FLUSHPIPE; |
| 92 | } | 75 | } |
| 93 | 76 | ||
| 94 | /// Halt the core | 77 | /// Halt the core |