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authorGravatar Subv2018-07-02 13:31:20 -0500
committerGravatar Subv2018-07-02 13:31:20 -0500
commitc1f55c32c8d8f05d6190da6f574592567e288e05 (patch)
tree78984e3ea649296c5060e35bc005c0cec7735f8e /src
parentGPU: Implemented the Z24S8 depth format and load the depth framebuffer. (diff)
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GPU: Added registers for depth test and cull mode.
Diffstat (limited to 'src')
-rw-r--r--src/video_core/engines/maxwell_3d.h54
1 files changed, 51 insertions, 3 deletions
diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h
index a15ca9e43..b8fb49ddf 100644
--- a/src/video_core/engines/maxwell_3d.h
+++ b/src/video_core/engines/maxwell_3d.h
@@ -280,6 +280,34 @@ public:
280 UnsignedInt = 0x2, 280 UnsignedInt = 0x2,
281 }; 281 };
282 282
283 enum class ComparisonOp : u32 {
284 Never = 0x200,
285 Less = 0x201,
286 Equal = 0x202,
287 LessEqual = 0x203,
288 Greater = 0x204,
289 NotEqual = 0x205,
290 GreaterEqual = 0x206,
291 Always = 0x207,
292 };
293
294 struct Cull {
295 enum class FrontFace : u32 {
296 ClockWise = 0x0900,
297 CounterClockWise = 0x0901,
298 };
299
300 enum class CullFace : u32 {
301 Front = 0x0404,
302 Back = 0x0405,
303 FrontAndBack = 0x0408,
304 };
305
306 u32 enabled;
307 FrontFace front_face;
308 CullFace cull_face;
309 };
310
283 struct Blend { 311 struct Blend {
284 enum class Equation : u32 { 312 enum class Equation : u32 {
285 Add = 1, 313 Add = 1,
@@ -435,11 +463,21 @@ public:
435 }; 463 };
436 } rt_control; 464 } rt_control;
437 465
438 INSERT_PADDING_WORDS(0x31); 466 INSERT_PADDING_WORDS(0x2B);
467
468 u32 depth_test_enable;
469
470 INSERT_PADDING_WORDS(0x5);
439 471
440 u32 independent_blend_enable; 472 u32 independent_blend_enable;
441 473
442 INSERT_PADDING_WORDS(0x15); 474 u32 depth_write_enabled;
475
476 INSERT_PADDING_WORDS(0x8);
477
478 ComparisonOp depth_test_func;
479
480 INSERT_PADDING_WORDS(0xB);
443 481
444 struct { 482 struct {
445 u32 separate_alpha; 483 u32 separate_alpha;
@@ -536,7 +574,13 @@ public:
536 } 574 }
537 } index_array; 575 } index_array;
538 576
539 INSERT_PADDING_WORDS(0xC7); 577 INSERT_PADDING_WORDS(0x7);
578
579 INSERT_PADDING_WORDS(0x46);
580
581 Cull cull;
582
583 INSERT_PADDING_WORDS(0x77);
540 584
541 struct { 585 struct {
542 u32 query_address_high; 586 u32 query_address_high;
@@ -743,13 +787,17 @@ ASSERT_REG_POSITION(vertex_buffer, 0x35D);
743ASSERT_REG_POSITION(zeta, 0x3F8); 787ASSERT_REG_POSITION(zeta, 0x3F8);
744ASSERT_REG_POSITION(vertex_attrib_format[0], 0x458); 788ASSERT_REG_POSITION(vertex_attrib_format[0], 0x458);
745ASSERT_REG_POSITION(rt_control, 0x487); 789ASSERT_REG_POSITION(rt_control, 0x487);
790ASSERT_REG_POSITION(depth_test_enable, 0x4B3);
746ASSERT_REG_POSITION(independent_blend_enable, 0x4B9); 791ASSERT_REG_POSITION(independent_blend_enable, 0x4B9);
792ASSERT_REG_POSITION(depth_write_enabled, 0x4BA);
793ASSERT_REG_POSITION(depth_test_func, 0x4C3);
747ASSERT_REG_POSITION(blend, 0x4CF); 794ASSERT_REG_POSITION(blend, 0x4CF);
748ASSERT_REG_POSITION(tsc, 0x557); 795ASSERT_REG_POSITION(tsc, 0x557);
749ASSERT_REG_POSITION(tic, 0x55D); 796ASSERT_REG_POSITION(tic, 0x55D);
750ASSERT_REG_POSITION(code_address, 0x582); 797ASSERT_REG_POSITION(code_address, 0x582);
751ASSERT_REG_POSITION(draw, 0x585); 798ASSERT_REG_POSITION(draw, 0x585);
752ASSERT_REG_POSITION(index_array, 0x5F2); 799ASSERT_REG_POSITION(index_array, 0x5F2);
800ASSERT_REG_POSITION(cull, 0x646);
753ASSERT_REG_POSITION(query, 0x6C0); 801ASSERT_REG_POSITION(query, 0x6C0);
754ASSERT_REG_POSITION(vertex_array[0], 0x700); 802ASSERT_REG_POSITION(vertex_array[0], 0x700);
755ASSERT_REG_POSITION(independent_blend, 0x780); 803ASSERT_REG_POSITION(independent_blend, 0x780);