summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorGravatar ShizZy2013-09-19 23:13:33 -0400
committerGravatar ShizZy2013-09-19 23:13:33 -0400
commitbf3938d56e05dd45a43d7355523340c1e8146b9c (patch)
treee5e6e140c6d37fefa2d2d2422754eeb26e6f7f4f /src
parentadded hw R/W/ memory functions (diff)
downloadyuzu-bf3938d56e05dd45a43d7355523340c1e8146b9c.tar.gz
yuzu-bf3938d56e05dd45a43d7355523340c1e8146b9c.tar.xz
yuzu-bf3938d56e05dd45a43d7355523340c1e8146b9c.zip
added mem_map hardware writing
Diffstat (limited to 'src')
-rw-r--r--src/core/src/mem_map.cpp25
-rw-r--r--src/core/src/mem_map.h3
-rw-r--r--src/core/src/mem_map_funcs.cpp123
3 files changed, 76 insertions, 75 deletions
diff --git a/src/core/src/mem_map.cpp b/src/core/src/mem_map.cpp
index 7bab1d4bd..eab4051ec 100644
--- a/src/core/src/mem_map.cpp
+++ b/src/core/src/mem_map.cpp
@@ -75,27 +75,6 @@ static MemoryView g_views[] =
75 75
76static const int kNumMemViews = sizeof(g_views) / sizeof(MemoryView); ///< Number of mem views 76static const int kNumMemViews = sizeof(g_views) / sizeof(MemoryView); ///< Number of mem views
77 77
78u8 Read8(const u32 addr) {
79 return 0xDE;
80}
81
82u16 Read16(const u32 addr) {
83 return 0xDEAD;
84}
85
86u32 Read32(const u32 addr) {
87 return 0xDEADBEEF;
88}
89
90void Write8(const u32 addr, const u32 data) {
91}
92
93void Write16(const u32 addr, const u32 data) {
94}
95
96void Write32(const u32 addr, const u32 data) {
97}
98
99void Init() { 78void Init() {
100 int flags = 0; 79 int flags = 0;
101 80
@@ -104,7 +83,7 @@ void Init() {
104 g_views[i].size = MEM_FCRAM_SIZE; 83 g_views[i].size = MEM_FCRAM_SIZE;
105 } 84 }
106 85
107 INFO_LOG(MEMMAP, "Memory system initialized. RAM at %p (mirror at 0 @ %p)", g_fcram, 86 NOTICE_LOG(MEMMAP, "Memory system initialized. RAM at %p (mirror at 0 @ %p)", g_fcram,
108 g_physical_fcram); 87 g_physical_fcram);
109} 88}
110 89
@@ -113,7 +92,7 @@ void Shutdown() {
113 MemoryMap_Shutdown(g_views, kNumMemViews, flags, &g_arena); 92 MemoryMap_Shutdown(g_views, kNumMemViews, flags, &g_arena);
114 g_arena.ReleaseSpace(); 93 g_arena.ReleaseSpace();
115 g_base = NULL; 94 g_base = NULL;
116 INFO_LOG(MEMMAP, "Memory system shut down."); 95 NOTICE_LOG(MEMMAP, "Memory system shut down.");
117} 96}
118 97
119 98
diff --git a/src/core/src/mem_map.h b/src/core/src/mem_map.h
index 08380ab3a..38004042e 100644
--- a/src/core/src/mem_map.h
+++ b/src/core/src/mem_map.h
@@ -67,6 +67,9 @@ u8 Read8(const u32 addr);
67u16 Read16(const u32 addr); 67u16 Read16(const u32 addr);
68u32 Read32(const u32 addr); 68u32 Read32(const u32 addr);
69 69
70u32 Read8_ZX(const u32 addr);
71u32 Read16_ZX(const u32 addr);
72
70void Write8(const u32 addr, const u32 data); 73void Write8(const u32 addr, const u32 data);
71void Write16(const u32 addr, const u32 data); 74void Write16(const u32 addr, const u32 data);
72void Write32(const u32 addr, const u32 data); 75void Write32(const u32 addr, const u32 data);
diff --git a/src/core/src/mem_map_funcs.cpp b/src/core/src/mem_map_funcs.cpp
index ed367e01f..d1739d726 100644
--- a/src/core/src/mem_map_funcs.cpp
+++ b/src/core/src/mem_map_funcs.cpp
@@ -29,22 +29,22 @@
29namespace Memory { 29namespace Memory {
30 30
31/* 31/*
32u8 *GetPointer(const u32 address) 32u8 *GetPointer(const u32 addr)
33{ 33{
34 if ((address & 0x3E000000) == 0x08000000) { 34 if ((addr & 0x3E000000) == 0x08000000) {
35 return g_fcram + (address & MEM_FCRAM_MASK); 35 return g_fcram + (addr & MEM_FCRAM_MASK);
36 } 36 }
37 else if ((address & 0x3F800000) == 0x04000000) { 37 else if ((addr & 0x3F800000) == 0x04000000) {
38 return m_pVRAM + (address & VRAM_MASK); 38 return m_pVRAM + (addr & VRAM_MASK);
39 } 39 }
40 else if ((address & 0x3F000000) >= 0x08000000 && (address & 0x3F000000) < 0x08000000 + g_MemorySize) { 40 else if ((addr & 0x3F000000) >= 0x08000000 && (addr & 0x3F000000) < 0x08000000 + g_MemorySize) {
41 return m_pRAM + (address & g_MemoryMask); 41 return m_pRAM + (addr & g_MemoryMask);
42 } 42 }
43 else { 43 else {
44 ERROR_LOG(MEMMAP, "Unknown GetPointer %08x PC %08x LR %08x", address, currentMIPS->pc, currentMIPS->r[MIPS_REG_RA]); 44 ERROR_LOG(MEMMAP, "Unknown GetPointer %08x PC %08x LR %08x", addr, currentMIPS->pc, currentMIPS->r[MIPS_REG_RA]);
45 static bool reported = false; 45 static bool reported = false;
46 if (!reported) { 46 if (!reported) {
47 Reporting::ReportMessage("Unknown GetPointer %08x PC %08x LR %08x", address, currentMIPS->pc, currentMIPS->r[MIPS_REG_RA]); 47 Reporting::ReportMessage("Unknown GetPointer %08x PC %08x LR %08x", addr, currentMIPS->pc, currentMIPS->r[MIPS_REG_RA]);
48 reported = true; 48 reported = true;
49 } 49 }
50 if (!g_Config.bIgnoreBadMemAccess) { 50 if (!g_Config.bIgnoreBadMemAccess) {
@@ -56,102 +56,121 @@ u8 *GetPointer(const u32 address)
56}*/ 56}*/
57 57
58template <typename T> 58template <typename T>
59inline void ReadFromHardware(T &var, const u32 address) 59inline void ReadFromHardware(T &var, const u32 addr)
60{ 60{
61 // TODO: Figure out the fastest order of tests for both read and write (they are probably different). 61 // TODO: Figure out the fastest order of tests for both read and write (they are probably different).
62 // TODO: Make sure this represents the mirrors in a correct way. 62 // TODO: Make sure this represents the mirrors in a correct way.
63 63
64 // Could just do a base-relative read, too.... TODO 64 // Could just do a base-relative read, too.... TODO
65 65
66 if ((address & 0x3E000000) == 0x08000000) { 66 if ((addr & 0x3E000000) == 0x08000000) {
67 var = *((const T*)&g_fcram[address & MEM_FCRAM_MASK]); 67 var = *((const T*)&g_fcram[addr & MEM_FCRAM_MASK]);
68 } 68 }
69 /*else if ((address & 0x3F800000) == 0x04000000) { 69 /*else if ((addr & 0x3F800000) == 0x04000000) {
70 var = *((const T*)&m_pVRAM[address & VRAM_MASK]); 70 var = *((const T*)&m_pVRAM[addr & VRAM_MASK]);
71 }*/ 71 }*/
72 else { 72 else {
73 _assert_msg_(MEMMAP, false, "unknown hardware read"); 73 _assert_msg_(MEMMAP, false, "unknown hardware read");
74 // WARN_LOG(MEMMAP, "ReadFromHardware: Invalid address %08x PC %08x LR %08x", address, currentMIPS->pc, currentMIPS->r[MIPS_REG_RA]); 74 // WARN_LOG(MEMMAP, "ReadFromHardware: Invalid addr %08x PC %08x LR %08x", addr, currentMIPS->pc, currentMIPS->r[MIPS_REG_RA]);
75 } 75 }
76} 76}
77 77
78template <typename T> 78template <typename T>
79inline void WriteToHardware(u32 address, const T data) 79inline void WriteToHardware(u32 addr, const T data) {
80{ 80 NOTICE_LOG(MEMMAP, "Test1 %08X", addr);
81 // Could just do a base-relative write, too.... TODO 81 // ExeFS:/.code is loaded here:
82 82 if ((addr & 0xFFF00000) == 0x00100000) {
83 if ((address & 0x3E000000) == 0x08000000) { 83 // TODO(ShizZy): This is dumb... handle correctly. From 3DBrew:
84 *(T*)&g_fcram[address & MEM_FCRAM_MASK] = data; 84 // http://3dbrew.org/wiki/Memory_layout#ARM11_User-land_memory_regions
85 } 85 // The ExeFS:/.code is loaded here, executables must be loaded to the 0x00100000 region when
86 /*else if ((address & 0x3F800000) == 0x04000000) { 86 // the exheader "special memory" flag is clear. The 0x03F00000-byte size restriction only
87 *(T*)&m_pVRAM[address & VRAM_MASK] = data; 87 // applies when this flag is clear. Executables are usually loaded to 0x14000000 when the
88 }*/ 88 // exheader "special memory" flag is set, however this address can be arbitrary.
89 else { 89 *(T*)&g_fcram[addr & MEM_FCRAM_MASK] = data;
90 NOTICE_LOG(MEMMAP, "Test2");
91 // Heap mapped by ControlMemory:
92 } else if ((addr & 0x3E000000) == 0x08000000) {
93 // TODO(ShizZy): Writes to this virtual address should be put in physical memory at FCRAM + GSP
94 // heap size... the following is writing to FCRAM + 0, which is actually supposed to be the
95 // application's GSP heap
96 *(T*)&g_fcram[addr & MEM_FCRAM_MASK] = data;
97 } else if ((addr & 0xFF000000) == 0x14000000) {
98 _assert_msg_(MEMMAP, false, "umimplemented write to GSP heap");
99 } else if ((addr & 0xFFF00000) == 0x1EC00000) {
100 _assert_msg_(MEMMAP, false, "umimplemented write to IO registers");
101 } else if ((addr & 0xFF000000) == 0x1F000000) {
102 _assert_msg_(MEMMAP, false, "umimplemented write to VRAM");
103 } else if ((addr & 0xFFF00000) == 0x1FF00000) {
104 _assert_msg_(MEMMAP, false, "umimplemented write to DSP memory");
105 } else if ((addr & 0xFFFF0000) == 0x1FF80000) {
106 _assert_msg_(MEMMAP, false, "umimplemented write to Configuration Memory");
107 } else if ((addr & 0xFFFFF000) == 0x1FF81000) {
108 _assert_msg_(MEMMAP, false, "umimplemented write to shared page");
109 } else {
90 _assert_msg_(MEMMAP, false, "unknown hardware write"); 110 _assert_msg_(MEMMAP, false, "unknown hardware write");
91 // WARN_LOG(MEMMAP, "WriteToHardware: Invalid address %08x PC %08x LR %08x", address, currentMIPS->pc, currentMIPS->r[MIPS_REG_RA]);
92 } 111 }
93} 112}
94 113
95bool IsValidAddress(const u32 address) { 114bool IsValidAddress(const u32 addr) {
96 if ((address & 0x3E000000) == 0x08000000) { 115 if ((addr & 0x3E000000) == 0x08000000) {
97 return true; 116 return true;
98 } else if ((address & 0x3F800000) == 0x04000000) { 117 } else if ((addr & 0x3F800000) == 0x04000000) {
99 return true; 118 return true;
100 } else if ((address & 0xBFFF0000) == 0x00010000) { 119 } else if ((addr & 0xBFFF0000) == 0x00010000) {
101 return true; 120 return true;
102 } else if ((address & 0x3F000000) >= 0x08000000 && (address & 0x3F000000) < 0x08000000 + MEM_FCRAM_MASK) { 121 } else if ((addr & 0x3F000000) >= 0x08000000 && (addr & 0x3F000000) < 0x08000000 + MEM_FCRAM_MASK) {
103 return true; 122 return true;
104 } else { 123 } else {
105 return false; 124 return false;
106 } 125 }
107} 126}
108 127
109u8 Read_U8(const u32 _Address) { 128u8 Read8(const u32 addr) {
110 u8 _var = 0; 129 u8 _var = 0;
111 ReadFromHardware<u8>(_var, _Address); 130 ReadFromHardware<u8>(_var, addr);
112 return (u8)_var; 131 return (u8)_var;
113} 132}
114 133
115u16 Read_U16(const u32 _Address) { 134u16 Read16(const u32 addr) {
116 u16_le _var = 0; 135 u16_le _var = 0;
117 ReadFromHardware<u16_le>(_var, _Address); 136 ReadFromHardware<u16_le>(_var, addr);
118 return (u16)_var; 137 return (u16)_var;
119} 138}
120 139
121u32 Read_U32(const u32 _Address) { 140u32 Read32(const u32 addr) {
122 u32_le _var = 0; 141 u32_le _var = 0;
123 ReadFromHardware<u32_le>(_var, _Address); 142 ReadFromHardware<u32_le>(_var, addr);
124 return _var; 143 return _var;
125} 144}
126 145
127u64 Read_U64(const u32 _Address) { 146u64 Read64(const u32 addr) {
128 u64_le _var = 0; 147 u64_le _var = 0;
129 ReadFromHardware<u64_le>(_var, _Address); 148 ReadFromHardware<u64_le>(_var, addr);
130 return _var; 149 return _var;
131} 150}
132 151
133u32 Read_U8_ZX(const u32 _Address) { 152u32 Read8_ZX(const u32 addr) {
134 return (u32)Read_U8(_Address); 153 return (u32)Read8(addr);
135} 154}
136 155
137u32 Read_U16_ZX(const u32 _Address) { 156u32 Read16_ZX(const u32 addr) {
138 return (u32)Read_U16(_Address); 157 return (u32)Read16(addr);
139} 158}
140 159
141void Write_U8(const u8 _Data, const u32 _Address) { 160void Write8(const u32 addr, const u8 data) {
142 WriteToHardware<u8>(_Address, _Data); 161 WriteToHardware<u8>(addr, data);
143} 162}
144 163
145void Write_U16(const u16 _Data, const u32 _Address) { 164void Write16(const u32 addr, const u16 data) {
146 WriteToHardware<u16_le>(_Address, _Data); 165 WriteToHardware<u16_le>(addr, data);
147} 166}
148 167
149void Write_U32(const u32 _Data, const u32 _Address) { 168void Write32(const u32 addr, const u32 data) {
150 WriteToHardware<u32_le>(_Address, _Data); 169 WriteToHardware<u32_le>(addr, data);
151} 170}
152 171
153void Write_U64(const u64 _Data, const u32 _Address) { 172void Write64(const u32 addr, const u64 data) {
154 WriteToHardware<u64_le>(_Address, _Data); 173 WriteToHardware<u64_le>(addr, data);
155} 174}
156 175
157} // namespace 176} // namespace