diff options
| author | 2019-12-11 18:12:29 -0400 | |
|---|---|---|
| committer | 2019-12-11 19:53:17 -0400 | |
| commit | af89723fa3d4ca13fc2ce7be545170d093eb4c31 (patch) | |
| tree | 584e8189da320a63c6bce2d91dae547f49d2826c /src | |
| parent | Gl_Shader_compiler: Correct Depth Compare for Texture Gather operations. (diff) | |
| download | yuzu-af89723fa3d4ca13fc2ce7be545170d093eb4c31.tar.gz yuzu-af89723fa3d4ca13fc2ce7be545170d093eb4c31.tar.xz yuzu-af89723fa3d4ca13fc2ce7be545170d093eb4c31.zip | |
Shader_Ir: Correct TLD4S encoding and implement f16 flag.
Diffstat (limited to 'src')
| -rw-r--r-- | src/video_core/engines/shader_bytecode.h | 3 | ||||
| -rw-r--r-- | src/video_core/shader/decode/texture.cpp | 21 | ||||
| -rw-r--r-- | src/video_core/shader/shader_ir.h | 2 |
3 files changed, 15 insertions, 11 deletions
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h index 290d929df..d6a2cc8b8 100644 --- a/src/video_core/engines/shader_bytecode.h +++ b/src/video_core/engines/shader_bytecode.h | |||
| @@ -1292,6 +1292,7 @@ union Instruction { | |||
| 1292 | BitField<50, 1, u64> dc_flag; | 1292 | BitField<50, 1, u64> dc_flag; |
| 1293 | BitField<51, 1, u64> aoffi_flag; | 1293 | BitField<51, 1, u64> aoffi_flag; |
| 1294 | BitField<52, 2, u64> component; | 1294 | BitField<52, 2, u64> component; |
| 1295 | BitField<55, 1, u64> fp16_flag; | ||
| 1295 | 1296 | ||
| 1296 | bool UsesMiscMode(TextureMiscMode mode) const { | 1297 | bool UsesMiscMode(TextureMiscMode mode) const { |
| 1297 | switch (mode) { | 1298 | switch (mode) { |
| @@ -1972,7 +1973,7 @@ private: | |||
| 1972 | INST("1101-01---------", Id::TLDS, Type::Texture, "TLDS"), | 1973 | INST("1101-01---------", Id::TLDS, Type::Texture, "TLDS"), |
| 1973 | INST("110010----111---", Id::TLD4, Type::Texture, "TLD4"), | 1974 | INST("110010----111---", Id::TLD4, Type::Texture, "TLD4"), |
| 1974 | INST("1101111011111---", Id::TLD4_B, Type::Texture, "TLD4_B"), | 1975 | INST("1101111011111---", Id::TLD4_B, Type::Texture, "TLD4_B"), |
| 1975 | INST("1101111100------", Id::TLD4S, Type::Texture, "TLD4S"), | 1976 | INST("11011111--00----", Id::TLD4S, Type::Texture, "TLD4S"), |
| 1976 | INST("110111110110----", Id::TMML_B, Type::Texture, "TMML_B"), | 1977 | INST("110111110110----", Id::TMML_B, Type::Texture, "TMML_B"), |
| 1977 | INST("1101111101011---", Id::TMML, Type::Texture, "TMML"), | 1978 | INST("1101111101011---", Id::TMML, Type::Texture, "TMML"), |
| 1978 | INST("11011110011110--", Id::TXD_B, Type::Texture, "TXD_B"), | 1979 | INST("11011110011110--", Id::TXD_B, Type::Texture, "TXD_B"), |
diff --git a/src/video_core/shader/decode/texture.cpp b/src/video_core/shader/decode/texture.cpp index 67926afcb..9aef5ddd5 100644 --- a/src/video_core/shader/decode/texture.cpp +++ b/src/video_core/shader/decode/texture.cpp | |||
| @@ -138,7 +138,11 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) { | |||
| 138 | values[element] = Operation(OperationCode::TextureGather, meta, std::move(coords_copy)); | 138 | values[element] = Operation(OperationCode::TextureGather, meta, std::move(coords_copy)); |
| 139 | } | 139 | } |
| 140 | 140 | ||
| 141 | WriteTexsInstructionFloat(bb, instr, values, true); | 141 | if (instr.tld4s.fp16_flag) { |
| 142 | WriteTexsInstructionHalfFloat(bb, instr, values, true); | ||
| 143 | } else { | ||
| 144 | WriteTexsInstructionFloat(bb, instr, values, true); | ||
| 145 | } | ||
| 142 | break; | 146 | break; |
| 143 | } | 147 | } |
| 144 | case OpCode::Id::TXD_B: | 148 | case OpCode::Id::TXD_B: |
| @@ -155,8 +159,8 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) { | |||
| 155 | const auto coord_count = GetCoordCount(texture_type); | 159 | const auto coord_count = GetCoordCount(texture_type); |
| 156 | 160 | ||
| 157 | const Sampler* sampler = is_bindless | 161 | const Sampler* sampler = is_bindless |
| 158 | ? GetBindlessSampler(base_reg, {{texture_type, false, false}}) | 162 | ? GetBindlessSampler(base_reg, {{texture_type, false, false}}) |
| 159 | : GetSampler(instr.sampler, {{texture_type, false, false}}); | 163 | : GetSampler(instr.sampler, {{texture_type, false, false}}); |
| 160 | Node4 values; | 164 | Node4 values; |
| 161 | if (sampler == nullptr) { | 165 | if (sampler == nullptr) { |
| 162 | for (u32 element = 0; element < values.size(); ++element) { | 166 | for (u32 element = 0; element < values.size(); ++element) { |
| @@ -362,7 +366,7 @@ const Sampler* ShaderIR::GetSampler(const Tegra::Shader::Sampler& sampler, | |||
| 362 | // Otherwise create a new mapping for this sampler | 366 | // Otherwise create a new mapping for this sampler |
| 363 | const auto next_index = static_cast<u32>(used_samplers.size()); | 367 | const auto next_index = static_cast<u32>(used_samplers.size()); |
| 364 | return &used_samplers.emplace_back(next_index, offset, info.type, info.is_array, info.is_shadow, | 368 | return &used_samplers.emplace_back(next_index, offset, info.type, info.is_array, info.is_shadow, |
| 365 | info.is_buffer); | 369 | info.is_buffer); |
| 366 | } | 370 | } |
| 367 | 371 | ||
| 368 | const Sampler* ShaderIR::GetBindlessSampler(Tegra::Shader::Register reg, | 372 | const Sampler* ShaderIR::GetBindlessSampler(Tegra::Shader::Register reg, |
| @@ -392,7 +396,7 @@ const Sampler* ShaderIR::GetBindlessSampler(Tegra::Shader::Register reg, | |||
| 392 | // Otherwise create a new mapping for this sampler | 396 | // Otherwise create a new mapping for this sampler |
| 393 | const auto next_index = static_cast<u32>(used_samplers.size()); | 397 | const auto next_index = static_cast<u32>(used_samplers.size()); |
| 394 | return &used_samplers.emplace_back(next_index, offset, buffer, info.type, info.is_array, | 398 | return &used_samplers.emplace_back(next_index, offset, buffer, info.type, info.is_array, |
| 395 | info.is_shadow, info.is_buffer); | 399 | info.is_shadow, info.is_buffer); |
| 396 | } | 400 | } |
| 397 | 401 | ||
| 398 | void ShaderIR::WriteTexInstructionFloat(NodeBlock& bb, Instruction instr, const Node4& components) { | 402 | void ShaderIR::WriteTexInstructionFloat(NodeBlock& bb, Instruction instr, const Node4& components) { |
| @@ -435,14 +439,14 @@ void ShaderIR::WriteTexsInstructionFloat(NodeBlock& bb, Instruction instr, const | |||
| 435 | } | 439 | } |
| 436 | 440 | ||
| 437 | void ShaderIR::WriteTexsInstructionHalfFloat(NodeBlock& bb, Instruction instr, | 441 | void ShaderIR::WriteTexsInstructionHalfFloat(NodeBlock& bb, Instruction instr, |
| 438 | const Node4& components) { | 442 | const Node4& components, bool ignore_mask) { |
| 439 | // TEXS.F16 destionation registers are packed in two registers in pairs (just like any half | 443 | // TEXS.F16 destionation registers are packed in two registers in pairs (just like any half |
| 440 | // float instruction). | 444 | // float instruction). |
| 441 | 445 | ||
| 442 | Node4 values; | 446 | Node4 values; |
| 443 | u32 dest_elem = 0; | 447 | u32 dest_elem = 0; |
| 444 | for (u32 component = 0; component < 4; ++component) { | 448 | for (u32 component = 0; component < 4; ++component) { |
| 445 | if (!instr.texs.IsComponentEnabled(component)) | 449 | if (!instr.texs.IsComponentEnabled(component) && !ignore_mask) |
| 446 | continue; | 450 | continue; |
| 447 | values[dest_elem++] = components[component]; | 451 | values[dest_elem++] = components[component]; |
| 448 | } | 452 | } |
| @@ -525,7 +529,6 @@ Node4 ShaderIR::GetTextureCode(Instruction instr, TextureType texture_type, | |||
| 525 | } | 529 | } |
| 526 | } | 530 | } |
| 527 | 531 | ||
| 528 | |||
| 529 | for (u32 element = 0; element < values.size(); ++element) { | 532 | for (u32 element = 0; element < values.size(); ++element) { |
| 530 | auto copy_coords = coords; | 533 | auto copy_coords = coords; |
| 531 | MetaTexture meta{*sampler, array, depth_compare, aoffi, {}, bias, lod, {}, element}; | 534 | MetaTexture meta{*sampler, array, depth_compare, aoffi, {}, bias, lod, {}, element}; |
| @@ -642,7 +645,7 @@ Node4 ShaderIR::GetTld4Code(Instruction instr, TextureType texture_type, bool de | |||
| 642 | 645 | ||
| 643 | const SamplerInfo info{texture_type, is_array, depth_compare, false}; | 646 | const SamplerInfo info{texture_type, is_array, depth_compare, false}; |
| 644 | const Sampler* sampler = is_bindless ? GetBindlessSampler(parameter_register++, info) | 647 | const Sampler* sampler = is_bindless ? GetBindlessSampler(parameter_register++, info) |
| 645 | : GetSampler(instr.sampler, info); | 648 | : GetSampler(instr.sampler, info); |
| 646 | Node4 values; | 649 | Node4 values; |
| 647 | if (sampler == nullptr) { | 650 | if (sampler == nullptr) { |
| 648 | for (u32 element = 0; element < values.size(); ++element) { | 651 | for (u32 element = 0; element < values.size(); ++element) { |
diff --git a/src/video_core/shader/shader_ir.h b/src/video_core/shader/shader_ir.h index 8324432ae..04ae5f822 100644 --- a/src/video_core/shader/shader_ir.h +++ b/src/video_core/shader/shader_ir.h | |||
| @@ -338,7 +338,7 @@ private: | |||
| 338 | void WriteTexsInstructionFloat(NodeBlock& bb, Tegra::Shader::Instruction instr, | 338 | void WriteTexsInstructionFloat(NodeBlock& bb, Tegra::Shader::Instruction instr, |
| 339 | const Node4& components, bool ignore_mask = false); | 339 | const Node4& components, bool ignore_mask = false); |
| 340 | void WriteTexsInstructionHalfFloat(NodeBlock& bb, Tegra::Shader::Instruction instr, | 340 | void WriteTexsInstructionHalfFloat(NodeBlock& bb, Tegra::Shader::Instruction instr, |
| 341 | const Node4& components); | 341 | const Node4& components, bool ignore_mask = false); |
| 342 | 342 | ||
| 343 | Node4 GetTexCode(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type, | 343 | Node4 GetTexCode(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type, |
| 344 | Tegra::Shader::TextureProcessMode process_mode, bool depth_compare, | 344 | Tegra::Shader::TextureProcessMode process_mode, bool depth_compare, |